CN118511288A

CN118511288A - Semiconductor package device and method of manufacturing the same

Info

Publication number: CN118511288A
Application number: CN202280087666.8A
Authority: CN
Inventors: 陈邦星; 曹凯
Original assignee: Innoscience Suzhou Semiconductor Co Ltd
Current assignee: Innoscience Suzhou Semiconductor Co Ltd
Priority date: 2022-11-22
Filing date: 2022-11-22
Publication date: 2024-08-16
Also published as: WO2024108369A1

Abstract

A semiconductor package device includes a lead frame, a semiconductor die, a metal layer, a plating layer, and a plurality of connection structures. The leadframe has a die pad and a plurality of leads adjacent to the die pad. The semiconductor die is disposed on the die pad. A metal layer is disposed on the top surface of the semiconductor die. The plating layer covers the first region of the metal layer. The second region of the metal layer is not covered by the metal layer. Each connecting structure connects one of the leads to the second region of the metal layer.

Description

Semiconductor package device and method of manufacturing the same

Technical Field

In general, the present invention relates to nitride-based semiconductor package devices. More particularly, the present invention relates to a nitride-based semiconductor package device having a metal layer stacked with a plating layer.

Background

In recent years, research into High Electron Mobility Transistors (HEMTs) has been increasingly popular, particularly for high power switches and high frequency applications. Group III nitride based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region to meet the needs of high power/frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs) and modulation doped FETs (MODFETs) in addition to HEMTs.

Disclosure of Invention

In one aspect, the present invention provides a semiconductor package device. The semiconductor package device includes a lead frame, a semiconductor die, a metal layer, a plating layer, and a plurality of connection structures. The leadframe has a die pad and a plurality of leads adjacent to the die pad. The semiconductor die is disposed on the die pad. A metal layer is disposed on the top surface of the semiconductor die. The plating layer covers the first region of the metal layer. The second region of the metal layer is not covered by the metal layer. Each connecting structure connects one of the leads to the second region of the metal layer.

In another aspect, the present invention provides a method for manufacturing a semiconductor package device. The method comprises the following steps. A metal layer is formed on the semiconductor die. The semiconductor die is attached to the die pad of the leadframe. A plating layer is formed to cover the first region of the metal layer. The second region of the metal layer not covered by the plating layer is connected to one of the leads by a connection structure.

In yet another aspect, the present invention provides a semiconductor package device. The semiconductor package device includes a leadframe, a semiconductor die, a metal layer, a first set of conductive structures, and a second set of conductive structures. The lead frame has a die pad, and first and second leads disposed on two opposite sides of the die pad. The semiconductor die is attached to the die pad. The metal layer is disposed on the semiconductor die and has a plurality of first strips and a plurality of second strips alternately arranged. The first strip is electrically connected to a first electrode of a semiconductor die having a first voltage level and the second strip is electrically connected to a second electrode of the semiconductor die having a second voltage level different from the first voltage level. The first set of conductive structures connects the first lead to a connection region of the first strip adjacent to the first lead. The second set of conductive structures connects the second lead to a connection region of a second strip adjacent to the second lead.

With the above configuration, in the present invention, a metal layer having a plurality of stripes is formed on the top surface of the semiconductor die. One portion of the strip is connected to the source of the semiconductor die and another portion of the strip is connected to the drain of the semiconductor die. For each strip, a plating is formed on a region of the metal layer, which region may serve as a plating region. By forming a plating layer on the metal layer, the total resistance of the semiconductor package device can be reduced. Therefore, the semiconductor package device of the present invention can have better performance.

Drawings

Various aspects of the invention can be readily appreciated from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity. Embodiments of the invention are described in more detail below with reference to the attached drawing figures, wherein:

fig. 1A is a top view of a semiconductor package device according to some embodiments of the present invention;

FIG. 1B is a vertical cross-sectional view of the semiconductor package device of FIG. 1A taken along line A-A';

FIG. 1C is a vertical cross-sectional view of a semiconductor die in the semiconductor package device of FIG. 1A;

fig. 2A, 2B, 2C and 2D illustrate various stages of a method for fabricating a semiconductor packaged device according to some embodiments of the invention;

fig. 3 is a vertical cross-sectional view of a semiconductor package device according to some embodiments of the invention; and

Fig. 4 is a vertical cross-sectional view of a semiconductor package device according to some embodiments of the invention.

Detailed Description

The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present invention will be readily understood from the following detailed description in conjunction with the accompanying drawings.

Spatial descriptions such as "upper," "lower," "left," "right," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," etc., are intended to be relative to a certain component or group of components, or a plane of a component or group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that specific implementations of the structures described herein may be spatially arranged in any orientation or manner without departing from the spirit of the present invention.

Further, it should be noted that, subject to device manufacturing conditions, in an actual device, the actual shape of the various structures depicted as being approximately rectangular may be curved, or have rounded corners, or have a slightly non-uniform thickness, etc. Straight lines and right angles are only used to facilitate the presentation of layers and features.

In the following description, a semiconductor device/die/package and a method for manufacturing the same are set forth as preferred examples. It will be apparent that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring. However, the present invention was written in order to enable any person skilled in the art to practice the teachings thereof without undue experimentation.

In conventional semiconductor package devices, the die is typically formed with a top metal layer on its top surface. The die is then connected to the pins/leads by a routing method. However, such packaged devices still have high resistance, which limits the performance of the overall device.

At least to avoid the above problems, the present invention provides a novel structure/arrangement for a semiconductor package device.

Fig. 1A is a top view of a semiconductor package device 1A according to some embodiments of the present invention. Fig. 1B is a vertical sectional view of the semiconductor package device 1A of fig. 1A along the line A-A'.

Referring to fig. 1A and 1B, a semiconductor package device 1A includes a lead frame 10, a semiconductor die 20, a metal layer 30, a plurality of plating layers 40, a plurality of solder layers 50, a plurality of connection structures CS, and an encapsulant 60. The detailed configuration will be described below.

The lead frame 10 includes a die pad 12 and a plurality of leads SL, DL, GL. The leads SL are disposed on the source side SS of the die pad 12. The leads DL and GL are disposed on the drain side DS of the die pad 12 opposite the source side SS. The lead DL is disposed adjacent one corner of the die pad 12 and the lead GL is disposed adjacent the other corner of the die pad 12.

Semiconductor die 20 is disposed on die pad 12. The semiconductor die 20 has a top surface TS and a bottom surface BS opposite each other. The top surface TS of the semiconductor die 20 may include analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, or other circuit elements formed within the top surface TS to implement analog or digital circuits, so the top surface TS may be the active surface of the semiconductor die 20. On the other hand, the semiconductor die 20 is attached to (or in contact with) the die pad 12 through its bottom surface BS.

In some embodiments, semiconductor die 20 may include transistors. A transistor may be formed adjacent to the top surface TS of the semiconductor die 20. In some embodiments, the transistor is a GaN-based transistor. Fig. 1C is a vertical sectional view of a semiconductor die in the semiconductor package device 1A of fig. 1A. Referring to fig. 1C, the transistor includes a substrate 202, a nitride-based semiconductor layer 203, a nitride-based semiconductor layer 204, electrodes 205, 206, a doped nitride-based semiconductor layer 207, and a gate 208. The detailed structure of the transistor 1A is shown in fig. 1B.

Referring to fig. 1C, the substrate 202 may be a semiconductor substrate. Exemplary materials for substrate 202 may include, but are not limited to, si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) or other suitable substrate materials. In some embodiments, the substrate 202 may include, but is not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 202 may include, but is not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.

In some embodiments, the transistor may include a buffer layer (not shown). A buffer layer (not shown) may be disposed on the substrate 202. A buffer layer may be disposed between the substrate 202 and the nitride-based semiconductor layer 203. The buffer layer may be configured to reduce lattice and thermal mismatch between the substrate 202 and the nitride-based semiconductor layer 203, thereby overcoming defects caused by mismatch/difference. The buffer layer may include a III-V compound. The III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for the buffer layer may further include, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.

In some embodiments, the transistor may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 202 and the buffer layer. The nucleation layer may be configured to provide a transition to accommodate the mismatch/difference between the substrate 202 and the group III nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, but are not limited to, alN or any alloy thereof.

A nitride-based semiconductor layer 203 is provided on the substrate 202. The nitride-based semiconductor layer 204 is provided on the nitride-based semiconductor layer 203. Exemplary materials for nitride-based semiconductor layer 203 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _xAl_yGa_(1-x-y) N (where x+y.ltoreq.1), or Al _xGa_(1-x) N (where x.ltoreq.1). Exemplary materials for nitride-based semiconductor layer 204 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _xAl_yGa_(1-x-y) N (where x+y.ltoreq.1), or Al _yGa_(1-y) N (where y.ltoreq.1).

The exemplary materials of the nitride-based semiconductor layers 203 and 204 are selected such that the nitride-based semiconductor layer 204 has a larger band gap (i.e., a forbidden band width) than the nitride-based semiconductor layer 203, thereby making their electron affinities different from each other and forming a heterojunction therebetween. For example, when the nitride-based semiconductor layer 203 is an undoped GaN layer having a band gap of about 3.4eV, the nitride-based semiconductor layer 204 may be selected to be an AlGaN layer having a band gap of about 4.0 eV. In this way, the nitride-based semiconductor layers 203 and 204 can function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Thus, the transistor may be used to include at least one GaN-based High Electron Mobility Transistor (HEMT).

Electrodes 205 and 206 are provided on the nitride-based semiconductor layer 204. Electrodes 205 and 206 are provided on the nitride-based semiconductor layer 204. The electrodes 205 and 206 may be in contact with the nitride-based semiconductor layer 204. In some embodiments, electrode 205 may serve as a source. In some embodiments, electrode 205 may function as a drain. In some embodiments, electrode 206 may serve as a source. In some embodiments, electrode 206 may function as a drain. The role of electrodes 205 and 206 depends on the device design.

In some embodiments, electrodes 205 and 206 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds (e.g., silicides and nitrides), other conductor materials, or combinations thereof. Exemplary materials for electrodes 205 and 206 may include, but are not limited to, ti, alSi, tiN, or combinations thereof. Each of the electrodes 205 and 206 may be a single layer or multiple layers of the same or different composition. The electrodes 205 and 206 form ohmic contacts with the nitride-based semiconductor layer 204. In addition, ohmic contact may be achieved by applying Ti, al, or other suitable materials to the electrodes 205 and 206.

In some embodiments, each electrode 205 and 206 is formed from at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer may include, but are not limited to, ti, ta, tiN, al, au, alSi, ni, pt, or combinations thereof. Exemplary materials for the conductive filler may include, but are not limited to AlSi, alCu, or combinations thereof.

A doped nitride-based semiconductor layer 207 is disposed on the nitride-based semiconductor layer 204. A gate electrode 208 is disposed/stacked on the doped nitride-based semiconductor layer 207. A doped nitride-based semiconductor layer 207 and a gate 2027 are disposed between the electrodes 205 and 206.

The width of the doped nitride-based semiconductor layer 207 is greater than the width of the gate electrode 208. In some embodiments, the width of the doped nitride-based semiconductor layer 207 is substantially the same as the width of the gate 208. The relationship of the widths of the doped nitride-based semiconductor layer 207 and the gate electrode 208 may depend on the device design.

In the exemplary illustration of fig. 1C, the transistor is an enhancement mode device that is in a normally off state when the gate 208 is at approximately zero bias. In particular, doped nitride-based semiconductor layer 207 may create at least one p-n junction with nitride-based semiconductor layer 204 to deplete the 2DEG region such that at least one zone of the 2DEG region corresponding to a location below gate 208 has a different characteristic (e.g., a different electron concentration) than the rest of the 2DEG region, and is thus blocked.

Due to this mechanism, the transistor has normally-off characteristics. In other words, when no voltage is applied to the gate 208 or the voltage applied to the gate 208 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate 208), the band of the 2DEG region under the gate 208 remains blocked, so no current flows.

In some embodiments, the doped nitride-based semiconductor layer 207 may be omitted such that the transistor is a depletion mode device, meaning that the transistor is in an on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 207 may be a p-type doped III-V semiconductor layer. Exemplary materials for the doped nitride-based semiconductor layer 207 may include, but are not limited to, p-doped group III-V nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities (e.g., be, zn, cd, and Mg). In some embodiments, nitride-based semiconductor layer 203 includes undoped GaN, nitride-based semiconductor layer 204 includes AlGaN, and doped nitride-based semiconductor layer 207 is a p-type GaN layer that can bend the underlying band structure upward and deplete the corresponding band of the 2DEG region, thereby placing the transistor in an off state.

Exemplary materials for gate 208 may include metals or metal compounds. The gate electrode 208 may be formed as a single layer, or as multiple layers of the same or different composition. Exemplary materials for the metal or metal compound may include, but are not limited to, W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.

Referring again to fig. 1A and 1B, a metal layer 30 is disposed on the top surface TS of the semiconductor die 20. The metal layer 30 is in contact with the top surface TS of the semiconductor die 20. The metal layer 30 includes a plurality of source portions SP, a plurality of drain portions DP, and a gate portion GP. The source portion SP is electrically connected to the source of the semiconductor die 20 having a source voltage level. Each source portion SP extends in the direction D1 to form a stripe. The drain portion DP is electrically connected to the drain of the semiconductor die 20 having a drain voltage level different from the source voltage level. Each drain portion DP extends in the direction D1 to form a stripe. That is, the extending direction of the source portion SP is the same as the extending direction of the drain portion DP. The gate portion GP is disposed at a corner of the semiconductor die 20. The source portions SP and the drain portions DP are alternately arranged in a direction D2 different from the direction D1. For example, direction D2 is perpendicular to direction D1. The gate portion GP is electrically connected to the gate of the semiconductor die 20.

Exemplary materials for metal layer 30 may include, but are not limited to, metals.

Each drain portion DP has a region R1 and a region R2 adjacent to the region R1. Some of the plating layers 40 are respectively disposed on the regions R1 of the drain electrode portions DP. These plating layers 40 contact the region R1 to define the location and size of the region R1. Therefore, the region R1 of the drain portion DP may serve as a plating region of the drain portion DP. On the other hand, the region R2 of each drain portion DP is defined as a region not covered by the corresponding plating layer 40 or the sealant 60. Referring to fig. 1A, a region R1 of the drain portion DP where the plating layer 40 is disposed is distant from the lead DL, and a region R2 of the drain portion DP where the plating layer 40 or the sealant 60 is not adjacent to the lead DL.

Each source portion SP has a region R1 and a region R2 adjacent to the region R1. Some of the plating layers 40 are respectively disposed on the regions R1 of the source portions SP. These plating layers 40 contact the region R1 to define the location and size of the region R1. Therefore, the region R1 of the source portion SP may serve as a plating region of the source portion SP. On the other hand, the region R2 of each source portion SP is defined as a region not covered by the corresponding plating layer 40 or the sealant 60. Referring to fig. 1A, a region R1 of the source portion SP provided with the plating layer 40 is distant from the lead SL, and a region R2 of the source portion DP without the plating layer 40 or the sealant 60 is adjacent to the lead SL.

Exemplary materials for the plating 40 may include, but are not limited to, ni, sn, or combinations thereof.

The solder layers 50 are disposed on the plating layers 40 of the drain and source portions DP and SP, respectively. The solder layer 50 contacts the top surfaces of the plating layers 40 of the drain and source portions DP and SP, respectively. The width of the solder layer 50 is smaller than the width of the plating layer 40 (see fig. 1A). Referring to fig. 1B, the thickness of the solder layer 50 is greater than the thickness of the plating layer 40 (see fig. 1B).

Exemplary materials for the solder layer 50 may include, but are not limited to, sn, ag, au, or combinations thereof.

The connection structures CS can be divided into three groups, CS1, CS2, CS3. The conductive structure CS1 connects the lead DL to the region R2 of the drain portion DP, wherein the region R2 of the drain portion DP is adjacent to the lead DL. The conductive structure CS2 connects the lead SL to the region R2 of the source portion SP, wherein the region R2 of the source portion SP is adjacent to the lead SL. Therefore, the region R2 of the drain portion DP and the region R2 of the source portion SP without the plating layer 40 or the sealant 60 may be used as a connection region. The conductive structure CS3 connects the lead GL to the gate portion GP.

In the present invention, the connection structures CS may be divided into three groups according to electrical characteristics. The connection structure CS1 is configured to connect the region R2 of the drain portion DP to the lead DL (e.g., drain lead) at the drain side DS, the connection structure CS2 is configured to connect the region R2 of the source portion SP to the lead SL (e.g., source lead) at the source side SS, and the connection structure CS3 is configured to connect the gate portion GP to the gate lead GL. The connection structure CS1 is located at the drain side DS, and the connection structure CS2 is located at the source side SS opposite to the drain side DS. If the connection structures CS1, CS2 are disposed in the same area, in some cases, the connection structures CS1, CS2 configured to transmit different electrical signals may contact each other, thereby causing a short circuit problem. In the present invention, by disposing the connection structures CS1, CS2 in the drain side region (i.e., the upper side region in fig. 1A) and the source side region (i.e., the lower side region in fig. 1A) respectively instead of disposing them in the same region, a possible short-circuit problem can be avoided.

Further, taking fig. 1B as an example, the semiconductor die 20 may have pads in different regions R1, R2. An electrical signal needs to be transmitted from the pads of the semiconductor die 20 in the region R1 and the pads of the semiconductor die 20 in the region R2 to the leads DL through the metal layer 30 and the connection structure CS. Since the distance between the region R1 and the lead DL is greater than the distance between the region R2 and the lead DL, a resistance difference may be generated. To compensate for this resistance difference, the region R1 distant from the drain portion DP of the lead DL has the plated layer 40 and the solder layer 50 stacked. The resistance of region R1 may be considered as the parallel resistance of metal layer 30, plating layer 40 and solder layer 50, and thus the resistance of region R1 may be reduced so as to be compatible with the resistance of region R2. Further, the resistance of the electric signal transmission path can be reduced, and thus the semiconductor package device 1A can have better performance.

Further, two adjacent drain portions DP may be separated by one source portion SP, and two adjacent drain portions SP may be separated by one drain portion DP. With this structure, an appropriate distance can be maintained between two adjacent connection structures CS1 (or CS 2). With the above configuration, signal interference can be avoided, thereby enabling the semiconductor package device 1A to have better performance.

The encapsulant 60 covers the semiconductor die 20 and a portion of the metal layer 30 to encapsulate the semiconductor die 20. At least a portion of the encapsulant 60 extends from the top surface of the metal layer 30 to contact the top surface TS of the semiconductor die 20. Exemplary materials for the encapsulant 60 may include, but are not limited to, polyimide (PI) or Epoxy Molding Compound (EMC).

Fig. 2A, 2B, 2C and 2D show different stages of a method for manufacturing a semiconductor package device 1A.

Referring to fig. 2A, a semiconductor die 20 is provided, wherein the semiconductor die 1 has a rectangular outline. A metal layer 30 is formed on the top surface of the semiconductor die 20. The encapsulant 60 is formed to cover/encapsulate the semiconductor die 20 and a portion of the metal layer 30.

Referring to fig. 2B, the plating layer 40 is formed to cover the region R1 of the metal layer 30, wherein the size and position of the region R1 are defined by the plating layer 40.

Referring to fig. 2C, a lead frame 10 including a die pad 12 and a plurality of leads SL, DL is provided. The semiconductor die 20 is attached to the die pad 12 of the leadframe 10.

Referring to fig. 2D, a solder layer 50 is formed on the plating layer 40 using a reflow method, wherein the solder layer 50 has a thickness greater than the plating layer 40. The region R2 of the metal layer 30 not covered by the plating layer 40 is connected to the lead DL through the connection structure CS. In some embodiments, the connection structure CS includes bonding wires. In this way, the semiconductor package device 1A in fig. 1A can be obtained.

Fig. 3 is a vertical cross-sectional view of a semiconductor package device 1B according to some embodiments of the present invention. The semiconductor package device 1B is similar to the semiconductor package device 1A in fig. 1A except that the solder layer 50B extends from the top surface of the plating layer 40 along the side surface of the plating layer 40 to be in contact with the top surface of the semiconductor die 20. This structure can further reduce the total resistance of the semiconductor package device 1B.

Fig. 4 is a vertical cross-sectional view of a semiconductor package device 1C according to some embodiments of the present invention. The semiconductor package device 1C is similar to the semiconductor package device 1A described and illustrated with reference to fig. 1A, except that the connection structure CS may be a conductive clip. Exemplary materials for the conductive clip may include, but are not limited to, conductive materials. This configuration may meet specific equipment requirements.

Based on the above, in the present invention, a metal layer having a plurality of stripes is formed on the top surface of the semiconductor die. One portion of the strip is connected to the source of the semiconductor die and another portion of the strip is connected to the drain of the semiconductor die. For each strip, a plating layer is formed on the area of the metal layer, thereby serving as a plating layer area. By forming a plating layer on the metal layer, the total resistance of the semiconductor package device can be reduced.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially," "essentially," "about," and "approximately" are used to describe and illustrate minor variations. When used in connection with an event or circumstance, the term can include instances where the event or circumstance occurs precisely and instances where it occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying along a same plane within a micrometer-scale distance, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm lying along the same plane.

As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass a situation in which a previous component is disposed directly on (e.g., in physical contact with) a subsequent component, as well as a situation in which one or more intermediate components are located between the previous component and the subsequent component.

While the invention has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be a distinction between artistic reproductions and actual devices in the present invention due to manufacturing processes and tolerances. Further, it should be understood that the actual devices and layers may deviate from the rectangular layer depiction of the drawings due to fabrication processes such as conformal deposition, etching, etc., and may include corner surfaces or edges, rounded corners, etc. Other embodiments of the invention not specifically shown are possible. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present invention. All such modifications are intended to be included within the scope of the following claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Thus, unless specifically indicated herein, the order and grouping of operations is not limiting.

Claims

1. A semiconductor package device comprising:

a lead frame having a die pad and a plurality of leads adjacent to the die pad;

A semiconductor die disposed on the die pad;

a metal layer disposed on a top surface of the semiconductor die;

A plating layer covering a first region of the metal layer, wherein a second region of the metal layer is not covered by the metal layer; and

A plurality of connection structures, wherein each of the connection structures connects one of the leads to the second region of the metal layer.

2. The semiconductor package device of any of the preceding claims, wherein in a top view of the semiconductor package device, the metal layer further comprises:

A plurality of source portions connected to sources of the semiconductor die and extending in a first direction; and

A plurality of drain portions connected to the drains of the semiconductor die and extending in the first direction,

Wherein the source portions and the drain portions are alternately arranged in a second direction different from the first direction, and each of the source portions and the drain portions has the first region and the second region.

3. A semiconductor package according to any one of the preceding claims, wherein the leads comprise source and drain leads at the source and drain sides of the die pad, respectively,

Wherein a second portion of the source portion is adjacent the source side and at least a portion of the connection structure connects the second portion of source portion to the source lead; and

A second portion of the drain portion is adjacent the drain side, and at least a portion of the connection structure connects the second portion of the source portion to the drain lead.

4. The semiconductor package device of any of the preceding claims, wherein the first direction is perpendicular to the second direction.

5. A semiconductor package device according to any preceding claim, further comprising a solder layer disposed on the plating layer.

6. A semiconductor package device according to any preceding claim, wherein the solder layer is in contact with a top surface of the plating layer.

7. A semiconductor package device according to any of the preceding claims, wherein the solder layer extends along a side surface of the plating layer to contact the top surface of the semiconductor die.

8. A semiconductor package device according to any of the preceding claims, wherein the thickness of the solder layer is greater than the thickness of the plating layer.

9. The semiconductor package device of any of the preceding claims, wherein in a top view of the semiconductor package device, the metal layer further comprises a gate portion connected to a gate of the semiconductor die through the conductive structure.

10. A semiconductor package device according to any preceding claim, further comprising an encapsulant covering the semiconductor die.

11. The semiconductor package device of any of the preceding claims, wherein at least a portion of the encapsulant extends from a top surface of the metal layer to contact a top surface of the semiconductor die.

12. A semiconductor package device according to any of the preceding claims, wherein the thickness of the plating layer is less than the thickness of the metal layer.

13. A semiconductor package device according to any of the preceding claims, wherein the semiconductor die has a bottom surface opposite the top surface thereof, and the bottom surface is in contact with the die pad.

14. A semiconductor package according to any of the preceding claims, wherein the connection structure comprises a wire bond.

15. A semiconductor package device according to any of the preceding claims, wherein the connection structure comprises a conductive clip.

16. A method of manufacturing a semiconductor package device, comprising:

Forming a metal layer on the semiconductor die;

forming a plating layer to cover the first region of the metal layer;

Attaching the semiconductor die to a die pad of a leadframe; and

The second region of the metal layer not covered by the plating layer is connected to a lead wire by a connection structure.

17. The method of any preceding claim, further comprising forming a solder layer on the plating layer using a reflow process.

18. The method of any preceding claim, wherein the thickness of the solder layer is greater than the thickness of the plating layer.

19. The method of any of the preceding claims, further comprising encapsulating the metal layer and the semiconductor die.

20. The method of any one of the preceding claims, wherein the connection structure further comprises a wire bond or a conductive clip.

21. A semiconductor package device comprising:

A lead frame having a die pad, first and second leads disposed on two opposite sides of the die pad;

a semiconductor die attached to the die pad;

a metal layer disposed on the semiconductor die and having a plurality of first strips and a plurality of second strips alternately arranged, wherein the first strips are electrically connected to a first electrode of the semiconductor die having a first voltage level and the second strips are electrically connected to a second electrode of the semiconductor die having a second voltage level different from the first voltage level;

a first set of conductive structures connecting the first lead to a connection region of the first strip adjacent to the first lead; and

A second set of conductive structures connecting the second lead to a connection region of the second strip adjacent to the second lead.

22. The semiconductor package device according to any one of the preceding claims, further comprising a plurality of plating layers disposed on the plated regions of the first and second strips, respectively,

Wherein the plated regions of the first strip are remote from the first leads, the plated regions of the first strip being adjacent to the connection regions of the first strip, respectively; and

The plated regions of the second strip are remote from the second leads, the plated regions of the second strip being adjacent to the connection regions of the second strip, respectively.

23. A semiconductor package device according to any of the preceding claims, wherein the first electrode is a source and the second electrode is a drain.

24. A semiconductor package device according to any preceding claim, further comprising an encapsulant covering the semiconductor die.

25. A semiconductor package device according to any of the preceding claims, wherein the first set of conductive structures and the second set of conductive structures comprise conductive clips or bond wires.