CN118507592A - Solar cell, manufacturing method thereof and photovoltaic module - Google Patents

Abstract

The present invention relates to a solar cell and a method for manufacturing the same, and a photovoltaic module. The method for manufacturing the solar cell comprises: sequentially forming a first tunneling oxide material layer and a first crystalline silicon material layer on a first surface of a substrate; using a laser to process a metal contact area of the first crystalline silicon material layer to form a first mask layer covering the metal contact area on a surface of the first crystalline silicon material layer away from the substrate; removing the first tunneling oxide material layer and the first crystalline silicon material layer, the portions outside the coverage of the first mask layer, and retaining the portions between the first mask layer and the substrate. In the solar cell and the method for manufacturing the same, and the photovoltaic module of the present invention, the number of processes is small, the process is simple, and the cost is low.

Description

Solar cell and manufacturing method thereof, photovoltaic module

Technical Field

The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module.

Background Art

With the continuous development of photovoltaic technology, people have higher and higher requirements for the photoelectric conversion efficiency of crystalline silicon solar cells, but the current industrialization of solar cell efficiency improvement still faces many challenges. In solar cells of related technologies, in order to reduce the recombination rate, extend the minority carrier lifetime, and improve the photoelectric conversion efficiency of solar cells, the substrate is generally passivated to form a local passivation contact structure under the metal area to achieve surface passivation and reduce metal recombination. However, most solar cells with local passivation contact structures require multiple deposition of mask layers to produce local passivation contact structures during the manufacturing process, which requires more processes and higher costs.

Summary of the invention

Based on this, it is necessary to provide a solar cell and a method for manufacturing the same, as well as a photovoltaic module, which have a small number of steps, a simple process, and a low cost.

An embodiment of the present application provides a method for manufacturing a solar cell, comprising:

sequentially forming a first tunneling oxide material layer and a first crystalline silicon material layer on a first surface of the substrate;

Processing the metal contact region of the first crystalline silicon material layer by laser to form a first mask layer covering the metal contact region on the surface of the first crystalline silicon material layer facing away from the substrate;

The portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer are removed, and the portions that are between the first mask layer and the substrate are retained.

In one embodiment, the material of the first mask layer includes silicon oxide.

In one embodiment, during the laser treatment:

The power of the laser is: 30 watts-100 watts, and the laser spot size is: 20 microns-100 microns.

In one embodiment, a first oxide layer is formed on the surface of the first crystalline silicon material layer;

The step of using laser to process the metal contact region of the first crystalline silicon material layer also includes:

The first oxide layer on the surface of the first crystalline silicon material layer is removed.

In one embodiment, the step of removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer and retaining the portions between the first mask layer and the substrate specifically includes:

The portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer are removed by using KOH.

In one embodiment, the first crystalline silicon material layer is made of intrinsic amorphous silicon;

After the step of removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer and retaining the portions between the first mask layer and the substrate, the method further includes:

The first surface of the substrate is doped with elements and annealed to form a first doped conductive layer and a first oxide material layer in sequence on the first surface of the substrate, and the first tunneling oxide material layer and the first crystalline silicon material layer, the portion located between the first mask layer and the substrate, are formed into a first tunneling oxide layer and a first polysilicon doped conductive layer, respectively.

In one embodiment, the substrate further includes a second surface disposed opposite to the first surface and a side surface adjacent to the first surface and the second surface;

After the step of diffusing the doping element on the first surface of the substrate and annealing, the method further comprises:

removing the first oxide material layer plated around the second surface and the side surface to expose the second surface;

Forming a second tunneling oxide material layer, a second polysilicon doped material layer and a second oxide material layer in sequence on the second surface;

The second oxide material layer, the second polysilicon doped material layer and the second tunneling oxide material layer coated on one side and the side of the first surface of the substrate are removed; the first oxide material layer and the first mask layer on one side of the first surface of the substrate, and the second oxide material layer on the second side of the substrate are removed to form a second tunneling oxide layer and a second polysilicon doped conductive layer stacked in sequence on the second surface of the substrate.

In one embodiment, after removing the first oxide material layer and the first mask layer on the first surface side of the substrate and the second oxide material layer on the second surface side of the substrate, the step further includes:

Forming a first passivation layer on one side of the first surface of the substrate, the first passivation layer covering the first doped conductive layer and the first polysilicon doped conductive layer;

forming a second passivation layer on a surface of the second polysilicon-doped conductive layer facing away from the substrate;

A first electrode is formed on the first passivation layer, and a second electrode is formed on the second passivation layer, wherein the first electrode passes through the first passivation layer and is in ohmic contact with the first polysilicon doped conductive layer, and the second electrode passes through the second passivation layer and is in ohmic contact with the second polysilicon doped conductive layer.

In one of the embodiments, the first crystalline silicon material layer is a first polycrystalline silicon doped material layer;

The step of sequentially forming a first tunneling oxide material and a first crystalline silicon material layer on the first surface of the substrate specifically includes:

sequentially forming a first tunneling oxide material layer and a first amorphous silicon doping material layer on a first surface of the substrate;

Annealing is performed to form the first amorphous silicon doping material layer into a first polycrystalline silicon doping material layer.

In one embodiment, the substrate further includes a second surface disposed opposite to the first surface, and a side surface adjacent to the first surface and the second surface;

Before the step of sequentially forming a first tunneling oxide material layer and a first crystalline silicon material layer on the first surface of the substrate, the step further includes:

Forming a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer in sequence on the second surface of the substrate;

The second mask material layer, the second polysilicon doping material layer and the second tunneling oxide material layer plated on the first surface and the side surface of the substrate are removed to form a second tunneling oxide layer and a second polysilicon doped conductive layer on the second surface respectively.

In one embodiment, after the step of removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer and retaining the portions between the first mask layer and the substrate, the step further includes:

The first mask layer and the second mask material layer on one side of the second surface of the substrate are removed.

In one embodiment, after removing the first mask layer and the second mask material layer on the second surface of the substrate, the step further includes:

forming a first passivation layer on one side of the first surface of the substrate, wherein the first passivation layer covers the first surface and the first crystalline silicon material layer;

forming a second passivation layer on a surface of the second polysilicon-doped conductive layer facing away from the substrate;

A first electrode is formed on the first passivation layer, and a second electrode is formed on the second passivation layer, wherein the first electrode passes through the first passivation layer and is in ohmic contact with the first polysilicon doped conductive material layer, and the second electrode passes through the second passivation layer and is in ohmic contact with the second polysilicon doped conductive layer.

In one embodiment, the step of sequentially stacking a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer on the second surface of the substrate specifically includes:

A second tunneling oxide material layer and a second intrinsic amorphous silicon material layer are sequentially stacked on the second surface of the substrate;

The second intrinsic amorphous silicon material layer is doped with elements and annealed to form a second polysilicon doped material layer from the second intrinsic amorphous silicon material layer, and a second mask material layer is formed on a surface of the second polysilicon doped material layer away from the substrate.

In one embodiment, the step of sequentially stacking a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer on the second surface of the substrate specifically includes:

A second tunneling oxide material layer, a second amorphous silicon doping material layer and a second mask material layer are sequentially stacked on the second surface of the substrate, and annealing is performed to form the second amorphous silicon doping material layer into a second polysilicon doping material layer.

A second aspect of an embodiment of the present application provides a solar cell, which is manufactured using the above-mentioned method for manufacturing a solar cell.

A third aspect of an embodiment of the present application provides a photovoltaic assembly, comprising at least one battery string, wherein the battery string comprises at least two of the above-mentioned solar cells.

The above-mentioned solar cell and its manufacturing method, photovoltaic module have the following beneficial effects:

The metal contact area of the first crystalline silicon material layer is processed by laser to form a first mask layer covering the metal contact area on the surface of the first crystalline silicon material layer facing away from the substrate. Compared with forming a whole layer of mask material on the surface of the first crystalline silicon material layer and then forming the first mask layer covering the metal contact area by etching, since only the corresponding area needs to be laser processed to form the first mask layer covering the metal contact area, the number of steps is significantly reduced, the process is simple, and the cost is also reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a solar cell provided in Example 1 of the present application;

FIG2 is a schematic diagram of the structure of a solar cell provided in Example 2 of the present application;

FIG3 is a schematic diagram of a process of manufacturing a solar cell provided in Example 3 of the present application;

4 is a schematic diagram of a first mask layer formed in the method for manufacturing a solar cell provided in Example 3 of the present application;

FIG5 is a schematic diagram of a first doped conductive layer formed in the method for manufacturing a solar cell provided in Example 3 of the present application;

6 is a schematic diagram of a second tunneling oxide layer and a second polysilicon doped conductive layer formed in the method for manufacturing a solar cell provided in Example 3 of the present application;

FIG7 is a schematic diagram of the structure of a solar cell formed in the method for manufacturing a solar cell provided in Example 3 of the present application;

FIG8 is a schematic diagram of a process of manufacturing a solar cell provided in Example 4 of the present application;

9 is a schematic diagram of a second tunneling oxide layer, a second polysilicon doped conductive layer, and a second mask material layer formed in a method for manufacturing a solar cell provided in Embodiment 4 of the present application;

10 is a schematic diagram of a first tunneling oxide layer, a first polysilicon doped conductive layer, and a first mask layer formed in the method for manufacturing a solar cell provided in Example 4 of the present application;

FIG. 11 is a schematic diagram of the structure of a solar cell formed in the method for manufacturing a solar cell provided in Example 4 of the present application.

Description of Figure Numbers:

100, 200, solar cells;

101, 201, local passivation contact structure; 102, 202, first mask layer; 203, second mask material layer; 110, 210, substrate; 120, first doped conductive layer; 121, first oxide material layer; 130, 230, first tunneling oxide layer; 131, first tunneling oxide material layer; 140, 240, first polysilicon doped conductive layer; 141, first crystalline silicon material layer; 150, 250, first passivation layer; 160, 260, second tunneling oxide layer; 170, 270, second polysilicon doped conductive layer; 180, 280, second passivation layer; 191, 291, first electrode; 192, 292, second electrode;

F, first surface; S, second surface; C, side surface.

DETAILED DESCRIPTION

In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and are not intended to be the only implementation method.

The following is a description of the solar cell and its manufacturing method and photovoltaic module of the embodiment of the present application in conjunction with the accompanying drawings. It should be noted that the solar cell is a double-sided passivated TOPCon cell as an example for description in the present application. The case of other types of solar cells is similar and will not be repeated here.

In addition, in the solar cell provided in this embodiment, the substrate may include a first surface F and a second surface S that are arranged opposite to each other, and a side surface C adjacent to the first surface F and the second surface S. In the embodiment of the present application, the first surface F corresponds to the front side of the solar cell, and the second surface S corresponds to the back side of the solar cell. In addition, the side of the substrate where the first surface F is located is referred to as the first surface F side, and the side where the second surface S is located is referred to as the second surface S side.

Embodiment 1

FIG. 1 is a schematic structural diagram of a solar cell 100 provided in Embodiment 1 of the present application.

1 , the solar cell 100 includes a substrate 110, and a first doped conductive layer 120 disposed on a first surface F of the substrate 110. When the substrate 110 is of N-type, the first doped conductive layer 120 may be, for example, a conductive layer doped with boron. A local passivation contact structure 101 is also disposed on one side of the first surface F of the solar cell 100. The local passivation contact structure 101 is disposed corresponding to a first electrode 191 on one side of the first surface F. The local passivation contact structure 101 is located below the first electrode 191. The local passivation contact structure 101 has a slightly larger setting range than the first electrode 191, or is the same as the first electrode 191. The local passivation contact structure 101 may include a first tunneling oxide layer 130 and a first polysilicon doped conductive layer 140 stacked on each other. The first tunneling oxide layer 130 is disposed on a surface of the first doped conductive layer 120 that is away from the substrate 110, and the first polysilicon doped conductive layer 140 is disposed on a surface of the first tunneling oxide layer 130 that is away from the substrate 110. The type of doping element in the first polysilicon doped conductive layer 140 is the same as that in the first doped conductive layer 120 , for example, it may be P-type boron element.

The solar cell 100 further includes a first passivation layer 150 and a first electrode 191. The first passivation layer 150 covers the first doped conductive layer 120 and the first polysilicon doped conductive layer 140. The first passivation layer 150 may include, for example, a stack of aluminum oxide and silicon nitride to perform passivation and anti-reflection functions. The first electrode 191 is disposed on the first passivation layer 150, and the first electrode 191 passes through the first passivation layer 150 and is in ohmic contact with the first polysilicon doped conductive layer 140.

The solar cell 100 further includes a second electrode 192, and a second tunneling oxide layer 160, a second polysilicon doped conductive layer 170, and a second passivation layer 180 sequentially stacked on the second surface S of the substrate 110. The second tunneling oxide layer 160, the second polysilicon doped conductive layer 170, and the second passivation layer 180 all cover the second surface S in their entirety.

The doping type of the doping element of the second polysilicon doped conductive layer 170 is opposite to the type of the doping element of the first polysilicon doped conductive layer 140 . For example, the doping element of the second polysilicon doped conductive layer 170 may be phosphorus.

The second electrode 192 passes through the second passivation layer 180 and makes ohmic contact with the second polysilicon doped conductive layer 170 .

Embodiment 2

FIG. 2 is a schematic diagram of the structure of a solar cell 200 provided in the second embodiment of the present application.

2 , the solar cell 200 includes a substrate 210, and a local passivation contact structure 201 disposed on a first surface F of the substrate 210. The local passivation contact structure 201 is disposed corresponding to a first electrode 291 on one side of the first surface F, and the local passivation contact structure 201 is located below the first electrode 291. The local passivation contact structure 201 has a slightly larger setting range than the first electrode 291, or is the same as the first electrode 291. The local passivation contact structure 201 may include a first tunneling oxide layer 230 and a first polysilicon doped conductive layer 240 stacked on each other. The first tunneling oxide layer 230 is disposed on the first surface F, and the first polysilicon doped conductive layer 240 is disposed on a surface of the first tunneling oxide layer 230 away from the substrate 210. The doping element type in the first polysilicon doped conductive layer 240 is consistent with the type of the substrate 210. For example, when the substrate 210 is an N-type substrate, the doping element in the first polysilicon doped conductive layer 240 includes phosphorus.

The solar cell 200 further includes a first passivation layer 250 and a first electrode 291. The first passivation layer 250 covers the first surface F and the first polysilicon doped conductive layer 240. The first passivation layer 250 may include, for example, a stack of aluminum oxide and silicon nitride to perform passivation and anti-reflection functions. The first electrode 291 is disposed on the first passivation layer 250, and the first electrode 291 passes through the first passivation layer 250 and is in ohmic contact with the first polysilicon doped conductive layer 240.

The solar cell 200 further includes a second electrode 292, and a second tunneling oxide layer 260, a second polysilicon doped conductive layer 270, and a second passivation layer 280 sequentially stacked on the second surface S of the substrate 210. The second tunneling oxide layer 260, the second polysilicon doped conductive layer 270, and the second passivation layer 280 all cover the second surface S in their entirety.

The doping type of the doping element of the second polysilicon doped conductive layer 270 is opposite to the type of the doping element of the first polysilicon doped conductive layer 240 . For example, the doping element of the second polysilicon doped conductive layer 270 may be boron.

The second electrode 292 passes through the second passivation layer 280 and makes ohmic contact with the second polysilicon doped conductive layer 270 .

Embodiment 3

3 is a schematic flow chart of a method for manufacturing a solar cell provided in the third embodiment of the present application. The method for manufacturing a solar cell provided in the third embodiment is used to manufacture the solar cell 100 in the first embodiment.

3 , the method for manufacturing a solar cell provided in the third embodiment includes:

S10 , sequentially forming a first tunneling oxide material layer and a first crystalline silicon material layer on a first surface of the substrate 110 .

S20, processing the metal contact region of the first crystalline silicon material layer by using laser to form a first mask layer covering the metal contact region on a surface of the first crystalline silicon material layer facing away from the substrate.

S30, removing portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer, and retaining portions between the first mask layer and the substrate.

By retaining the portion of the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 located between the first mask layer 102 and the substrate 110, the retained portion of the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 can function as a local passivation contact structure 101. Compared with a solution in which the passivation contact material is provided on the entire layer of the substrate 110, the setting area of the passivation contact material is reduced, and the absorption of incident light is reduced, thereby increasing the photocurrent of the solar cell 100 and improving the efficiency of the solar cell 100.

In addition, the metal contact area of the first crystalline silicon material layer 141 is processed by laser to form a first mask layer 102 covering the metal contact area on the surface of the first crystalline silicon material layer 141 away from the substrate 110. Compared with forming a whole layer of mask material on the surface of the first crystalline silicon material layer 141 and then forming the first mask layer covering the metal contact area by etching, since only the corresponding area on the surface of the first crystalline silicon material layer 141 needs to be laser processed to form the first mask layer 102 covering the metal contact area, the number of steps is significantly reduced, the process is simple, and the cost is also reduced.

The metal contact region is used to make ohmic contact with the first electrode 191 to be formed on the first surface F of the substrate 110, that is, the portion of the first crystalline silicon material layer 141 below the first electrode 191. The setting range of the metal contact region can be greater than or equal to the setting range of the first electrode 191.

In addition, generally speaking, while the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 are formed on the first surface F, the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 are also formed by plating on the side surface C and the second surface S of the substrate 110. Therefore, removing the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 that are located outside the coverage of the first mask layer 102 means that not only the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 on the first surface F that are not covered by the first mask layer 102 are removed, but also the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 on the side surface C and the second surface S that are not covered by the first mask layer 102 are removed.

Furthermore, when the metal contact area is processed by laser, the crystalline silicon material in the metal contact area is modified, so that the crystalline silicon material in the metal contact area is formed into a modified crystalline silicon material, thereby further improving and reducing the contact resistance.

In the embodiment of the present application, the material of the first mask layer 102 includes silicon oxide. The first mask layer 102 is formed corresponding to a plurality of metal contact regions on the first crystalline silicon material layer 141 and may include a plurality of mask patterns, each mask pattern corresponding to a metal contact region.

Furthermore, in the laser processing: the laser power is: 30 watts-100 watts, and the laser spot size is: 20 microns-100 microns.

Of course, the type of laser can be selected as needed, for example, it can be ultraviolet picosecond.

In the embodiment of the present application, a first oxide layer is formed on the surface of the first crystalline silicon material layer 141, and before the step of “processing the metal contact area of the first crystalline silicon material layer 141 by laser”, the following steps are also included:

The first oxide layer on the surface of the first crystalline silicon material layer 141 is removed.

In a specific implementation, the step of removing the first oxide layer on the surface of the first crystalline silicon material layer 141 specifically includes:

The first oxide layer on the surface of the first crystalline silicon material layer is removed by using HF acid.

The first oxide layer here can be, for example, a material such as silicon oxide formed on the surface of the first crystalline silicon material layer 141. The first oxide layer can be an oxide layer naturally formed on the surface of the first crystalline silicon material layer 141.

In this embodiment, the step of “removing the portions of the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 that are outside the coverage of the first mask layer 102 and retaining the portions between the first mask layer 102 and the substrate 110” specifically includes:

The portions of the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 that are outside the coverage of the first mask layer 102 are removed using KOH.

In the embodiment of the present application, referring to FIG. 3 , the material of the first crystalline silicon material layer 141 is intrinsic amorphous silicon;

In step S30, after the step of “removing the portions of the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 that are outside the coverage of the first mask layer 102, and retaining the portions between the first mask layer 102 and the substrate 110”, the following steps are further included:

S40, diffusing doping elements on the first surface of the substrate and annealing to sequentially form a first doped conductive layer and a first oxide material layer on the first surface of the substrate, and forming the first tunneling oxide material layer and the first crystalline silicon material layer, the portion located between the first mask layer and the substrate, as the first tunneling oxide layer and the first polysilicon doped conductive layer, respectively.

Here, the doping element diffusion may be boron diffusion, so that the doping element can pass through the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141 and enter the substrate 110 for doping. The doping element can also dope the first crystalline silicon material layer 141. The first oxide material layer 121 may be BSG, for example.

In this embodiment, as mentioned above, the substrate 110 further includes a second surface S disposed opposite to the first surface F.

In step S40, after the step of “diffusing doping elements on the first surface F of the substrate 110 and annealing”, the following steps are further included:

The first oxide material layer 121 plated around the second surface S and the side surface C is removed to expose the second surface S. For example, HF acid is used to remove the BSG layer on the second surface S and the side surface C, and then polishing is performed.

A second tunneling oxide material layer, a second polysilicon doping material layer and a second oxide material layer are sequentially stacked on the second surface S. Here, the second polysilicon doping material layer may be doped with phosphorus, for example, and the second oxide material layer may be PSG, for example.

The second oxide material layer, the second polysilicon doped material layer and the second tunneling oxide material layer coated on one side of the first surface F and the side C of the substrate 110 are removed; the first oxide material layer and the first mask layer 102 on one side of the first surface F of the substrate 110, and the second oxide material layer on the second side of the substrate 110 are removed to form a second tunneling oxide layer 160 and a second polysilicon doped conductive layer 170 stacked in sequence on the second surface S of the substrate 110.

In this embodiment, after the step of “removing the first oxide material layer and the first mask layer 102 on the first surface F of the substrate 110, and the second oxide material layer on the second surface of the substrate 110”, the following steps are further performed:

A first passivation layer 150 is formed on one side of the first surface F of the substrate 110 . The first passivation layer 150 covers the first doped conductive layer 120 and the first polysilicon doped conductive layer 140 . The first passivation layer 150 may include, for example, a stack of aluminum oxide and silicon nitride.

A second passivation layer 180 is formed on a surface of the second polysilicon doped conductive layer 170 facing away from the substrate 110 . The second passivation layer 180 may include a stacked layer of aluminum oxide and silicon nitride.

A first electrode 191 is formed on the first passivation layer 150 , and a second electrode 192 is formed on the second passivation layer 180 , wherein the first electrode 191 passes through the first passivation layer 150 and makes ohmic contact with the first polysilicon doped conductive layer 140 , and the second electrode 192 passes through the second passivation layer 180 and makes ohmic contact with the second polysilicon doped conductive layer 170 .

Figure 4 is a schematic diagram of the first mask layer 102 formed in the method for manufacturing a solar cell provided in Example 3 of the present application; Figure 5 is a schematic diagram of the first doped conductive layer 120 formed in the method for manufacturing a solar cell provided in Example 3 of the present application; Figure 6 is a schematic diagram of the second tunneling oxide layer 160 and the second polysilicon doped conductive layer 170 formed in the method for manufacturing a solar cell provided in Example 3 of the present application; Figure 7 is a schematic diagram of the structure of the solar cell 100 formed in the method for manufacturing a solar cell provided in Example 3 of the present application.

4 to 7, a specific example is given below to illustrate the method for manufacturing a solar cell according to an embodiment of the present application. The method comprises:

Step 1: Use an N-type silicon wafer as a substrate 110 and perform pretreatment and texturing on the substrate 110. The first surface F of the substrate 110 corresponds to the front side of the solar cell 100, and the second surface S of the substrate 110 corresponds to the back side of the solar cell 100.

Step 2: forming a first tunneling oxide material layer 131 and a first crystalline silicon material layer 141 in sequence on the first surface F of the substrate 110 . Here, the first crystalline silicon material layer 141 is intrinsic amorphous silicon.

Step 3: Use HF cleaning to remove the first oxide layer on the surface of the first crystalline silicon material layer 141. Use laser to process the metal contact area of the first crystalline silicon material layer 141 to form a first mask layer 102 covering the metal contact area on the surface of the first crystalline silicon material layer 141 away from the substrate 110. And remove the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141, the part outside the coverage of the first mask layer 102, and retain the part between the first mask layer 102 and the substrate 110, as shown in FIG. 4.

Step 4: The first surface F of the substrate 110 is doped with a doping element (the doping element is boron) and annealed to sequentially form a first doped conductive layer 120 and a first oxide material layer 121 (for example, BSG) on the first surface F of the substrate 110, and the first tunneling oxide material layer 131 and the first crystalline silicon material layer 141, the portions located between the first mask layer 102 and the substrate 110, are formed into the first tunneling oxide layer 130 and the first polysilicon doped conductive layer 140, respectively.

Step 5: remove the first oxide material layer 121 plated on the second surface S and the side surface C to expose the second surface S, for example, by removing the BSG layer on the second surface S and the side surface C using HF acid, and then polishing, as shown in FIG. 5 .

Step six: A second tunneling oxide material layer, a second polysilicon doping material layer and a second oxide material layer (not shown) are sequentially stacked on the second surface S. The second polysilicon doping material layer may be doped with phosphorus, for example, and the second oxide material layer may be PSG, for example.

Step 7: Use HF cleaning to remove the second oxide material layer plated around the first surface F side and the side C of the substrate 110 and perform polishing. Use KOH cleaning to remove the second polysilicon doped material layer and the second tunneling oxide material layer plated around the first surface F side and the side C of the substrate 110, and use HF cleaning to remove the first oxide material layer and the first mask layer 102 on the first surface F side of the substrate 110, as well as the second oxide material layer on the second side of the substrate 110, so as to form a second tunneling oxide layer 160 and a second polysilicon doped conductive layer 170 stacked in sequence on the second surface S of the substrate 110, as shown in FIG. 6 .

Step eight: forming a first passivation layer 150 on one side of the first surface F of the substrate 110 , the first passivation layer 150 covers the first doped conductive layer 120 and the first polysilicon doped conductive layer 140 , and the first passivation layer 150 may include, for example, a stack of aluminum oxide and silicon nitride.

Step nine: forming a second passivation layer 180 on the surface of the second polysilicon doped conductive layer 170 facing away from the substrate 110 . The second passivation layer 180 may include a stack of aluminum oxide and silicon nitride.

Step 10: Form a first electrode 191 on the first passivation layer 150, and form a second electrode 192 on the second passivation layer 180, wherein the first electrode 191 passes through the first passivation layer 150 and makes ohmic contact with the first polysilicon doped conductive layer 140, and the second electrode 192 passes through the second passivation layer 180 and makes ohmic contact with the second polysilicon doped conductive layer 170, as shown in FIG. 7.

Embodiment 4

Fig. 8 is a schematic flow chart of a method for manufacturing a solar cell provided in the fourth embodiment of the present application. The method for manufacturing a solar cell provided in the fourth embodiment is used to manufacture the solar cell 200 in the second embodiment.

8 , the method for manufacturing a solar cell provided in the fourth embodiment includes:

S10, forming a first tunneling oxide material layer and a first crystalline silicon material layer in sequence on a first surface of the substrate.

S20, processing the metal contact region of the first crystalline silicon material layer by using laser to form a first mask layer covering the metal contact region on a surface of the first crystalline silicon material layer facing away from the substrate.

S30, removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer, and retaining the portions between the first mask layer and the substrate.

Referring to the description in Example 3, the metal contact area of the first crystalline silicon material layer is processed by laser to form a first mask layer 202 covering the metal contact area on the surface of the first crystalline silicon material layer away from the substrate 210. Compared with forming a whole layer of mask material on the surface of the first crystalline silicon material layer and then forming the first mask layer 202 covering the metal contact area by etching, since only the corresponding area needs to be laser processed to form the first mask layer 202 covering the metal contact area, the number of steps is significantly reduced, the process is simple, and the cost is also reduced.

Furthermore, the material of the first mask layer 202 includes silicon oxide. The first mask layer 202 is formed corresponding to the metal contact region and may include a plurality of mask patterns, each of which corresponds to a metal contact region.

During laser processing: the laser power is: 30 watts-100 watts, and the laser spot size is: 20 microns-100 microns.

In addition, a first oxide layer is formed on the surface of the first crystalline silicon material layer, and before the step of "processing the metal contact area of the first crystalline silicon material layer using laser", the step also includes: removing the first oxide layer on the surface of the first crystalline silicon material layer.

In a specific implementation, the step of removing the first oxide layer on the surface of the first crystalline silicon material layer specifically includes:

The first oxide layer on the surface of the first crystalline silicon material layer is removed by using HF acid.

The first oxide layer here can be, for example, a material such as silicon oxide formed by natural oxidation of the surface of the first crystalline silicon material layer.

In this embodiment, the step of “removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer 202 and retaining the portions between the first mask layer 202 and the substrate 210” specifically includes:

The portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer 202 are removed using KOH.

In this embodiment, the first crystalline silicon material layer is a first polysilicon doped material layer. The step of “forming a first tunneling oxide material and a first crystalline silicon material layer in sequence on the first surface F of the substrate 210” specifically includes:

Forming a first tunneling oxide material layer and a first amorphous silicon doping material layer in sequence on the first surface F of the substrate 210;

Annealing is performed to form the first amorphous silicon doping material layer into a first polycrystalline silicon doping material layer.

In this embodiment, referring to FIG. 8 , before the step of sequentially forming the first tunneling oxide material layer and the first crystalline silicon material layer on the first surface F of the substrate 210 , the following steps are further included:

S01 , forming a second tunneling oxide material layer, a second polysilicon doping material layer and a second mask material layer 203 in sequence on a second surface S of the substrate 210 .

S02, removing the second mask material layer 203, the second polysilicon doped material layer and the second tunneling oxide material layer coated around the first surface F and the side C of the substrate 210 to form a second tunneling oxide layer 260 and a second polysilicon doped conductive layer 270 on the second surface S.

In specific implementation, the second mask material layer 203 coated around the first surface F and the side C can be removed by HF acid cleaning, and the second polysilicon doping material layer and the second tunneling oxide material layer coated around the first surface F and the side C can be removed by KOH cleaning.

In this embodiment, after the step of “removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer 202 and retaining the portions between the first mask layer 202 and the substrate 210”, the following steps are further performed:

The first mask layer 202 and the second mask material layer on the second surface S of the substrate 210 are removed.

Further, after the step of “removing the first mask layer 202 and the second mask material layer on one side of the second surface of the substrate 210”, the method further includes:

A first passivation layer 250 is formed on one side of the first surface F of the substrate 210 . The first passivation layer 250 covers the first surface F and the first polysilicon-doped conductive layer 240 . The first passivation layer 250 may include, for example, a stack of aluminum oxide and silicon nitride.

A second passivation layer 280 is formed on a surface of the second polysilicon-doped conductive layer 270 facing away from the substrate 210 . The second passivation layer 280 may include a stacked layer of aluminum oxide and silicon nitride.

A first electrode 291 is formed on the first passivation layer 250 , and a second electrode 292 is formed on the second passivation layer 280 , wherein the first electrode 291 passes through the first passivation layer 250 and makes ohmic contact with the first polysilicon-doped conductive material layer, and the second electrode 292 passes through the second passivation layer 280 and makes ohmic contact with the second polysilicon-doped conductive layer 270 .

In this embodiment, in step S01, the step of sequentially stacking and forming a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer 203 on the second surface S of the substrate 210 specifically includes:

A second tunneling oxide material layer and a second intrinsic amorphous silicon material layer are sequentially stacked on the second surface S of the substrate 210;

The second intrinsic amorphous silicon material layer is doped with elements and annealed to form a second polysilicon doping material layer from the second intrinsic amorphous silicon material layer, and a second mask material layer 203 is formed on a surface of the second polysilicon doping material layer away from the substrate 210 .

The second mask material layer 203 may be BSG.

Alternatively, in another embodiment, in step S01, the step of sequentially stacking a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer 203 on the second surface S of the substrate 210 specifically includes:

A second tunneling oxide material layer, a second amorphous silicon doping material layer and a second mask material layer 203 are sequentially stacked on the second surface S of the substrate 210 and annealed to form the second amorphous silicon doping material layer into a second polysilicon doping material layer.

The second mask material layer 203 may be silicon oxide.

A specific example is given below to illustrate the method for manufacturing the solar cell according to the embodiment of the present application.

Figure 9 is a schematic diagram of the second tunneling oxide layer 260, the second polysilicon doped conductive layer 270 and the second mask material layer 203 formed in the method for manufacturing a solar cell provided in Example 4 of the present application; Figure 10 is a schematic diagram of the first tunneling oxide layer 230, the first polysilicon doped conductive layer 240, and the first mask layer 202 formed in the method for manufacturing a solar cell provided in Example 4 of the present application; Figure 11 is a schematic diagram of the structure of the solar cell 200 formed in the method for manufacturing a solar cell provided in Example 4 of the present application.

In conjunction with FIG. 9 to FIG. 11 , the method includes:

Step 1: Use an N-type silicon wafer as a substrate 210 and perform pretreatment and polishing on the substrate 210 , wherein the first surface F of the substrate 210 corresponds to the front side of the solar cell 200 , and the second surface S of the substrate 210 corresponds to the back side of the solar cell 200 .

Step 2: depositing a second tunneling oxide material layer, a second polysilicon doping material layer and a second mask material layer 203 in sequence on the second surface S of the polished substrate 210. Here, the doping element in the second polysilicon doping material layer may be boron.

Of course, when the second polysilicon doping material layer 203 is generated by the in-situ method, a second tunneling oxide material layer, a second amorphous silicon doping material layer (doping element is boron) and a second mask material layer 203 may be sequentially stacked on the second surface S of the substrate 210, and annealed to form the second amorphous silicon doping material layer into a second polysilicon doping material layer. At this time, the second mask material layer may be silicon oxide.

Alternatively, a second tunneling oxide material layer and a second intrinsic amorphous silicon material layer may be sequentially stacked on the second surface S of the substrate 210. The second intrinsic amorphous silicon material layer is diffused with a doping element (the doping element is boron) and annealed to form a second polysilicon doping material layer from the second intrinsic amorphous silicon material layer, and a second mask material layer 203 is formed on the surface of the second polysilicon doping material layer away from the substrate 210. At this time, the second mask material layer 203 may be BSG.

Step 3: Clean the first surface F of the substrate 210 with HF to remove the second mask material layer 203 coated around the first surface F and the side C of the substrate 210, and remove the second polysilicon doping material layer and the second tunneling oxide material layer coated around one side of the first surface F and the side C with KOH to form a second tunneling oxide layer 260 and a second polysilicon doped conductive layer 270 on the second surface S. Of course, the surface of the second polysilicon doped conductive layer 270 facing away from the substrate 210 is also covered with the second mask material layer 203, as shown in FIG9 .

Step 4: A first tunneling oxide material layer and a first crystalline silicon material layer are sequentially formed on the first surface F of the substrate 210. Here, the first crystalline silicon material layer may be a first polycrystalline silicon doped material layer (the doping element is phosphorus). In specific implementation, a first tunneling oxide material layer and a first amorphous silicon doped material layer may be sequentially formed on the first surface F of the substrate 210, and annealed to form the first amorphous silicon doped material layer into a first polycrystalline silicon doped material layer.

Step 5: Use HF cleaning to remove the first oxide layer on the surface of the first crystalline silicon material layer. Use laser to process the metal contact area of the first crystalline silicon material layer to form a first mask layer 202 covering the metal contact area on the surface of the first crystalline silicon material layer away from the substrate 210. And use KOH cleaning to remove the first tunneling oxide material layer and the first crystalline silicon material layer, the part outside the coverage of the first mask layer 202, the part between the first mask layer 202 and the substrate 210 is first retained, and the first tunneling oxide material layer and the first crystalline silicon material layer are respectively formed into a first tunneling oxide layer 230 and a first polysilicon doped conductive layer 240, as shown in FIG. 10, forming a local passivation contact structure 201 on the first surface F. The setting range of the first mask layer 202 is the same as the setting range of the first electrode 291. After the solar cell 200 is formed, the metal contact area is located below the first electrode 291. The first mask layer 202 can be silicon oxide.

Step 6: Use HF to remove the first mask layer 202 on the first surface F and the second mask material layer 203 on the second surface S. In other words, the second mask material layer 203 covering the surface of the second polysilicon doped conductive layer 270 away from the substrate 210 is removed.

Step seven: forming a first passivation layer 250 on one side of the first surface F of the substrate 210 . The first passivation layer 250 covers the first surface F and the first polysilicon doped conductive layer 240 . The first passivation layer 250 may include, for example, a stack of aluminum oxide and silicon nitride.

A second passivation layer 280 is formed on a surface of the second polysilicon-doped conductive layer 270 facing away from the substrate 210 . The second passivation layer 280 may include a stacked layer of aluminum oxide and silicon nitride.

A first electrode 291 is formed on the first passivation layer 250, and a second electrode 292 is formed on the second passivation layer 280, wherein the first electrode 291 passes through the first passivation layer 250 and makes ohmic contact with the first polysilicon doped conductive layer 240, and the second electrode 292 passes through the second passivation layer 280 and makes ohmic contact with the second polysilicon doped conductive layer 270, thereby forming the solar cell 200 shown in FIG. 11.

Embodiment 5

Embodiment 5 of the present application provides a photovoltaic module (not shown), including at least one battery string, the battery string includes at least two solar cells 200 as described above, and the solar cells 200 can be connected together by serial welding.

Embodiment 5 of the present application further provides a photovoltaic system (not shown), comprising the above-mentioned photovoltaic assembly.

Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is to say, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array may be an array combination of multiple photovoltaic components. For example, multiple photovoltaic components can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter and is converted into the alternating current required by the mains power grid, and then connected to the mains network to realize solar power supply.

The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims (16)

1. A method for manufacturing a solar cell, comprising: sequentially forming a first tunneling oxide material layer and a first crystalline silicon material layer on a first surface of the substrate; Processing the metal contact region of the first crystalline silicon material layer by laser to form a first mask layer covering the metal contact region on a surface of the first crystalline silicon material layer facing away from the substrate; Portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer are removed, and portions between the first mask layer and the substrate are retained. 2 . The method for manufacturing a solar cell according to claim 1 , wherein the material of the first mask layer comprises silicon oxide. 3. The method for manufacturing a solar cell according to claim 1, wherein during the laser processing: The power of the laser is: 30 watts-100 watts, and the laser spot size is: 20 microns-100 microns. 4. The method for manufacturing a solar cell according to claim 1, wherein a first oxide layer is formed on the surface of the first crystalline silicon material layer; Before the step of processing the metal contact area of the first crystalline silicon material layer by laser, the step further includes: The first oxide layer on the surface of the first crystalline silicon material layer is removed. 5. The method for manufacturing a solar cell according to claim 1, characterized in that the step of removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer and retaining the portions between the first mask layer and the substrate specifically comprises: The portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer are removed by using KOH. 6. The method for manufacturing a solar cell according to any one of claims 1 to 5, characterized in that the material of the first crystalline silicon material layer is intrinsic amorphous silicon; After the step of removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer and retaining the portions between the first mask layer and the substrate, the method further includes: The first surface of the substrate is doped with elements and annealed to form a first doped conductive layer and a first oxide material layer in sequence on the first surface of the substrate, and the first tunneling oxide material layer and the first crystalline silicon material layer, the portion located between the first mask layer and the substrate, are formed into a first tunneling oxide layer and a first polysilicon doped conductive layer, respectively. 7. The method for manufacturing a solar cell according to claim 6, wherein the substrate further comprises a second surface disposed opposite to the first surface and a side surface adjacent to the first surface and the second surface; After the step of diffusing the doping elements on the first surface of the substrate and annealing, the method further comprises: removing the first oxide material layer plated around the second surface and the side surface to expose the second surface; Forming a second tunneling oxide material layer, a second polysilicon doping material layer and a second oxide material layer in sequence on the second surface; The second oxide material layer, the second polysilicon doped material layer and the second tunneling oxide material layer coated on one side and the side of the first surface of the substrate are removed; the first oxide material layer and the first mask layer on one side of the first surface of the substrate, and the second oxide material layer on the second side of the substrate are removed to form a second tunneling oxide layer and a second polysilicon doped conductive layer stacked in sequence on the second surface of the substrate. 8. The method for manufacturing a solar cell according to claim 7, characterized in that after the step of removing the first oxide material layer and the first mask layer on the first surface side of the substrate and the second oxide material layer on the second surface side of the substrate, the method further comprises: forming a first passivation layer on one side of the first surface of the substrate, wherein the first passivation layer covers the first doped conductive layer and the first polysilicon doped conductive layer; forming a second passivation layer on a surface of the second polysilicon-doped conductive layer away from the substrate; A first electrode is formed on the first passivation layer, and a second electrode is formed on the second passivation layer, wherein the first electrode passes through the first passivation layer and is in ohmic contact with the first polysilicon doped conductive layer, and the second electrode passes through the second passivation layer and is in ohmic contact with the second polysilicon doped conductive layer. 9. The method for manufacturing a solar cell according to any one of claims 1 to 5, characterized in that the first crystalline silicon material layer is a first polycrystalline silicon doped material layer; The step of sequentially forming a first tunneling oxide material and a first crystalline silicon material layer on the first surface of the substrate specifically includes: sequentially forming a first tunneling oxide material layer and a first amorphous silicon doping material layer on the first surface of the substrate; Annealing is performed to form the first amorphous silicon doping material layer into a first polycrystalline silicon doping material layer. 10. The method for manufacturing a solar cell according to claim 9, wherein the substrate further comprises a second surface disposed opposite to the first surface, and a side surface adjacent to the first surface and the second surface; Before the step of sequentially forming a first tunneling oxide material layer and a first crystalline silicon material layer on the first surface of the substrate, the step further includes: Forming a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer in sequence on the second surface of the substrate; The second mask material layer, the second polysilicon doping material layer and the second tunneling oxide material layer plated on the first surface and the side of the substrate are removed to form a second tunneling oxide layer and a second polysilicon doped conductive layer on the second surface respectively. 11. The method for manufacturing a solar cell according to claim 10, characterized in that after the step of removing the portions of the first tunneling oxide material layer and the first crystalline silicon material layer that are outside the coverage of the first mask layer and retaining the portions between the first mask layer and the substrate, the method further comprises: The first mask layer and the second mask material layer on the second surface side of the substrate are removed. 12. The method for manufacturing a solar cell according to claim 11, characterized in that after the step of removing the first mask layer and the second mask material layer on the second surface side of the substrate, the method further comprises: forming a first passivation layer on one side of the first surface of the substrate, wherein the first passivation layer covers the first surface and the first crystalline silicon material layer; forming a second passivation layer on a surface of the second polysilicon-doped conductive layer away from the substrate; A first electrode is formed on the first passivation layer, and a second electrode is formed on the second passivation layer, wherein the first electrode passes through the first passivation layer and is in ohmic contact with the first polysilicon-doped conductive material layer, and the second electrode passes through the second passivation layer and is in ohmic contact with the second polysilicon-doped conductive layer. 13. The method for manufacturing a solar cell according to claim 10, wherein the step of sequentially stacking a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer on the second surface of the substrate specifically comprises: Forming a second tunneling oxide material layer and a second intrinsic amorphous silicon material layer in sequence on the second surface of the substrate; The second intrinsic amorphous silicon material layer is doped with elements and annealed to form a second polysilicon doping material layer from the second intrinsic amorphous silicon material layer, and a second mask material layer is formed on a surface of the second polysilicon doping material layer away from the substrate. 14. The method for manufacturing a solar cell according to claim 10, wherein the step of sequentially stacking a second tunneling oxide material layer, a second polysilicon doping material layer, and a second mask material layer on the second surface of the substrate specifically comprises: A second tunneling oxide material layer, a second amorphous silicon doping material layer and a second mask material layer are sequentially stacked on the second surface of the substrate, and annealing is performed to form the second amorphous silicon doping material layer into a second polysilicon doping material layer. 15. A solar cell, characterized in that it is manufactured by the method for manufacturing a solar cell according to any one of claims 1 to 14. 16 . A photovoltaic module, comprising at least one battery string, wherein the battery string comprises at least two solar cells according to claim 15 .