CN119317245A - Solar cell and preparation method thereof, photovoltaic module - Google Patents

Abstract

The embodiment of the present application provides a solar cell and a method for preparing the same, and a photovoltaic module. The solar cell comprises: a silicon substrate, the silicon substrate having a first surface and a second surface arranged opposite to each other, the first surface having a first region and a second region arranged alternately; a tunneling oxide layer, a doped polysilicon layer, and a SiN _x mask layer located in the first region and stacked in sequence in a direction away from the silicon substrate; a silicon oxide layer and an anti-reflection layer located in the second region and stacked in sequence in a direction away from the silicon substrate; an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer located on the second surface and stacked in sequence in a direction away from the silicon substrate; the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polycrystalline silicon layer. The solar cell of the technical solution of the present application can effectively improve the bifaciality and photoelectric conversion efficiency of the cell through the specific structure of the first surface and the second surface.

Description

Solar cell, preparation method thereof and photovoltaic module

Technical Field

The application relates to the technical field of solar cells, in particular to a solar cell, a preparation method thereof and a photovoltaic module.

Background

Along with the large-scale development of clean energy, the consumption proportion of the photovoltaic at the terminal energy is continuously improved, and the photovoltaic is expected to become a clean energy power generation mode with the largest installation amount due to the advantages of mature application mode, wide resource distribution, continuous optimization of technology and the like in the future.

Currently, the main current photovoltaic crystalline silicon is PERC (emitter and back passivation cell), topCon (tunnel oxide passivation contact cell), HJT (heterojunction cell), IBC (interdigital back contact cell), and the like. In the present stage, PERC is used as a main current battery in a p-type stage, the conversion efficiency is relatively low, the productivity is accelerating, topCon is used as a transition technology, the efficiency cannot reach the ceiling of a crystalline silicon battery, the initial investment cost of HJT equipment is high, ITO (noble metal indium exists) and high-consumption silver paste are used, the cost is high, the large-scale mass production is difficult, the IBC battery has complex procedures, the yield is low, the cost is high, the double-sided rate is low, and the IBC battery is difficult to apply to a centralized photovoltaic project all the time.

It should be noted that the foregoing is not necessarily prior art, and is not intended to limit the scope of the present application.

Disclosure of Invention

The embodiment of the application provides a solar cell, a preparation method thereof and a photovoltaic module, and aims to solve the technical problems. The solar cell provided by the embodiment of the application can effectively improve the double-sided rate and the photoelectric conversion efficiency of the cell through the specific structures of the first surface and the second surface.

In a first aspect, an embodiment of the present application provides a solar cell, including:

a silicon substrate having a first face and a second face disposed opposite each other, the first face having alternately disposed first and second regions;

The tunneling oxide layer, the doped polysilicon layer and the SiN _x mask layer are positioned in the first region and are sequentially stacked along the direction away from the silicon substrate;

A silicon oxide layer and an antireflection layer which are positioned in the second region and are sequentially laminated along a direction away from the silicon substrate;

The intrinsic amorphous silicon layer, the doped microcrystalline silicon layer and the transparent conductive oxide layer are positioned on the second surface and sequentially stacked along the direction far away from the silicon substrate, wherein the doping type of the doped microcrystalline silicon layer is opposite to that of the doped polycrystalline silicon layer;

A first electrode on the SiN _x mask layer;

And a second electrode on the transparent conductive oxide layer.

Optionally, the width of the doped polysilicon layer is the same as the width of the SiN _x mask layer, and the width of the doped polysilicon layer is 40-50 μm.

Optionally, the doping concentration of the doped polysilicon layer is 1E20-2E20/cm ³.

Optionally, the tunneling oxide layer has a thickness of 1.3-2.0nm, the doped polysilicon layer has a thickness of 90-120nm, the SiN _x mask layer has a thickness of 60-70nm, and/or

The thickness of the silicon oxide layer is 1.3-2.0nm, and the thickness of the anti-reflection layer is 60-70nm.

Optionally, the thickness of the intrinsic amorphous silicon layer is 5-7nm, the thickness of the doped microcrystalline silicon layer is 20-25nm, and the thickness of the transparent conductive oxide layer is 45-60nm.

In a second aspect, an embodiment of the present application provides a method for manufacturing a solar cell, including:

Providing a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a first area and a second area which are alternately arranged;

Forming a tunneling oxide layer, a doped polysilicon layer and a SiN _x mask layer which are sequentially stacked along the direction away from the silicon substrate in the first region;

forming a silicon oxide layer and an anti-reflection layer sequentially stacked in a direction away from the silicon substrate in the second region;

Sequentially forming an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer and a transparent conductive oxide layer on the second surface, wherein the doping type of the doped microcrystalline silicon layer is opposite to that of the doped polycrystalline silicon layer;

And forming a first electrode on the SiN _x mask layer and forming a second electrode on the transparent conductive oxide layer.

Optionally, forming a tunneling oxide layer, a doped polysilicon layer, and a SiN _x mask layer sequentially stacked in a direction away from the silicon substrate in the first region includes:

sequentially forming an initial tunneling oxide layer, an initial doped polysilicon layer and an initial SiN _x mask layer on the first surface;

And sequentially removing the initial SiN _x mask layer, the initial doped polysilicon layer and the initial tunneling oxide layer which are positioned in the second region by adopting a first laser etching process, and reserving the initial SiN _x mask layer, the initial doped polysilicon layer and the initial tunneling oxide layer which are positioned in the first region to form the SiN _x mask layer, the doped polysilicon layer and the tunneling oxide layer.

Optionally, forming the initially doped polysilicon layer includes:

forming an initial intrinsic polysilicon layer on the initial tunneling oxide layer;

And doping the initial intrinsic polycrystalline silicon layer to form the initial doped polycrystalline silicon layer.

Optionally, the forming, in the second region, a silicon oxide layer and an anti-reflection layer sequentially stacked in a direction away from the silicon substrate includes:

sequentially forming an initial silicon oxide layer and an initial antireflection layer on a first surface with the tunneling oxide layer, the doped polysilicon layer and the SiN _x mask layer;

And removing the initial silicon oxide layer and the initial antireflection layer which are positioned in the first region by adopting a second laser etching process, exposing the SiN _x mask layer, and reserving the initial silicon oxide layer and the initial antireflection layer which are positioned in the second region to form the silicon oxide layer and the antireflection layer.

Optionally, in the second laser etching process, the laser wavelength is 520-540nm, the etching time is 0.7-0.8s, and the laser power is 30-40W.

In a third aspect, an embodiment of the present application provides a photovoltaic module, including the solar cell according to any one of the embodiments above.

The embodiment of the application adopts the technical scheme and can have the following advantages:

in the solar cell, a tunneling oxide layer, a doped polycrystalline silicon layer, a SiN _x mask layer and a first electrode which are sequentially stacked are arranged in a first area of a first surface, a silicon oxide layer and an antireflection layer which are sequentially stacked are arranged in a second area of the first surface, the doped polycrystalline silicon layer is only arranged in the first area, the doped polycrystalline silicon layer is not arranged in the second area of the solar cell, parasitic absorption loss is reduced, and an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer and a transparent conductive oxide layer which are sequentially stacked are arranged in a second surface of the solar cell, so that passivation effect is improved, and cell conversion efficiency is improved. The solar cell provided by the embodiment of the application can effectively improve the double-sided rate and the photoelectric conversion efficiency of the cell through the specific structures of the first surface and the second surface.

Drawings

In the drawings, the same reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily drawn to scale. It is appreciated that these drawings depict only some embodiments according to the disclosure and are not therefore to be considered limiting of its scope.

Fig. 1 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a product of forming an initial tunneling oxide layer, an initial doped polysilicon layer, and an initial SiN _x mask layer in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of a product of forming a tunnel oxide layer, a doped polysilicon layer, and a SiN _x mask layer in an embodiment of the present application;

FIG. 4 is a schematic illustration of a product of forming an initial silicon oxide layer and an initial anti-reflective layer in an embodiment of the application;

FIG. 5 is a schematic diagram of a product of forming a silicon oxide layer, an anti-reflection layer, an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, and a transparent conductive oxide layer in an embodiment of the application;

FIG. 6 is a schematic diagram of a product for forming a photosensitive mask layer according to an embodiment of the present application;

fig. 7 is a schematic diagram of a product in which a first electrode and a second electrode are formed in an embodiment of the application.

Reference numerals illustrate:

10. A silicon substrate, 11, a first region, 12, a second region;

21a, an initial tunneling oxide layer, 21b, a tunneling oxide layer, 22a, an initial doped polysilicon layer, 22b, a doped polysilicon layer, 23a, an initial SiN _x mask layer, 23b, a SiN _x mask layer, 24a, an initial silicon oxide layer, 24b, a silicon oxide layer, 25a, an initial antireflection layer, 25b, an antireflection layer, 26, a photosensitive mask layer;

31. An intrinsic amorphous silicon layer, a doped microcrystalline silicon layer, a transparent conductive oxide layer, and a transparent conductive oxide layer;

41. first electrode, 42, second electrode.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings. In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.

As shown in fig. 7, an embodiment of the present application provides a solar cell, including:

A silicon substrate 10, the silicon substrate 10 having a first face and a second face disposed opposite to each other, the first face having a first region 11 and a second region 12 disposed alternately;

A tunnel oxide layer 21b, a doped polysilicon layer 22b, and a SiN _x mask layer 23b, which are located in the first region 11 and are sequentially stacked in a direction away from the silicon substrate 10;

a silicon oxide layer 24b and an antireflection layer 25b which are located in the second region 12 and are sequentially laminated in a direction away from the silicon substrate 10;

An intrinsic amorphous silicon layer 31, a doped microcrystalline silicon layer 32, and a transparent conductive oxide layer 33, which are sequentially stacked in a direction away from the silicon substrate 10, on the second surface, the doped microcrystalline silicon layer 32 having a doping type opposite to that of the doped polycrystalline silicon layer 22 b;

a first electrode 41 located on the SiN _x mask layer 23 b;

a second electrode 42 located on the transparent conductive oxide layer 33.

The silicon substrate can be an N-type silicon substrate or a P-type silicon substrate, and the doped polysilicon layer can also be an N-type doped polysilicon layer or a P-type doped polysilicon layer. The doping type of the silicon substrate and the doping type of the doped polysilicon layer can be the same or opposite, when the doping type of the silicon substrate and the doping type of the doped polysilicon layer are the same, the doping type of the doped microcrystalline silicon layer is opposite to the doping type of the doped polysilicon layer, the substrate and the doped microcrystalline silicon layer form a PN junction, and when the doping type of the silicon substrate and the doping type of the doped polysilicon layer are opposite, the doping type of the doped microcrystalline silicon layer is the same as the doping type of the substrate, and the substrate and the doped polysilicon layer form a PN junction. The N-type doping element can comprise one or more of phosphorus element, arsenic element and antimony element, and the P-type doping element can comprise one or more of boron element, gallium element and indium element.

The first electrode and the second electrode may each be a metal electrode, the material of which includes, but is not limited to, one of Au, ag, al, cu.

In some embodiments, the width of the doped polysilicon layer is the same as the width of the SiN _x mask layer, and the width of the doped polysilicon layer is 40-50 μm.

The doped polysilicon layer is located in the first region and the doped polysilicon layer is absent in the second region. When the doped polysilicon layer is wider, more areas on the surface of the battery are shielded, the surface active area irradiated by light is reduced, so that the photoelectric conversion efficiency is reduced, and when the doped polysilicon layer is narrower, the resistance is increased, and the electrical property is influenced. When the width of the doped polysilicon layer is 40-50 mu m, the battery has good photoelectric conversion efficiency and lower resistance, and is beneficial to improving the overall performance of the solar battery. Specifically, the width of the doped polysilicon layer may be 40 μm, 45 μm or 50 μm.

In some embodiments, the doped polysilicon layer has a doping concentration of 1E20-2E20/cm ³.

When the doping concentration of the doped polysilicon layer is 1E20-2E20/cm ³, the conductivity of the doped polysilicon layer can be reasonably controlled, the charge collection efficiency can be improved, the loss of charges in the transmission process can be reduced, and the contact resistance can be optimized. Specifically, the doping concentration of the doped polysilicon layer may be 1E20/cm ³、1.2E20/cm³、1.5E20/cm³、1.8E20/cm³ or 2E20/cm ³

In some embodiments, the tunneling oxide layer has a thickness of 1.3-2.0nm, the doped polysilicon layer has a thickness of 90-120nm, the SiN _x mask layer has a thickness of 60-70nm, and/or

The thickness of the silicon oxide layer is 1.3-2.0nm, and the thickness of the antireflection layer is 60-70nm.

The tunneling oxide layer belongs to an ultrathin passivation layer, so that the electrons are blocked from being compounded by minority carriers when tunneling into the doped polysilicon layer, and then electrons are transversely transmitted and collected by the electrode in the polysilicon layer, thereby greatly reducing metal contact compound current, and improving open-circuit voltage and short-circuit current of the battery, and further improving the battery efficiency. When the thickness of the tunneling oxide layer is 1.3-2.0nm, not only can the effective tunneling and passivation effects be ensured, but also the problems of discontinuous or uneven film layers and the like caused by the excessively thin tunneling oxide layer are avoided. Specifically, the thickness of the tunnel oxide layer may be 1.3nm, 1.5nm, 1.7nm, or 2.0nm.

The doped polysilicon layer is used as a collecting layer of charge carriers, so that the filling factor and open-circuit voltage of the battery can be improved. If the thickness of the doped polysilicon layer is too small to form efficient electron collection, too large a thickness increases resistance and parasitic absorption, allowing for sufficient lateral electron transport paths to be provided to enable electrons to be efficiently collected by the electrode while maintaining a low contact resistance when the thickness of the doped polysilicon layer is 90-120 nm. Specifically, the thickness of the doped polysilicon layer may be 90nm, 100nm or 120nm.

The tunneling oxide layer is combined with the doped polysilicon layer to form a passivation contact structure, so that surface recombination of the first surface is reduced, and the overall efficiency of the battery is improved.

The SiN _x mask layer is a protective layer for passivating the contact structure and is used for protecting the structures such as the tunneling oxide layer, the doped polysilicon layer and the like. When the thickness of the SiN _x mask layer is 60-70nm, the SiN _x layer can be ensured to provide protection, and meanwhile, parasitic absorption is prevented from being increased or the optical transmittance of the battery is prevented from being reduced due to the excessively thick SiN _x mask layer. Specifically, the thickness of the SiN _x mask layer may be 60nm, 65nm, or 70nm.

The thicknesses of the tunneling oxide layer, the doped polysilicon layer and the SiN _x mask layer cooperate to further improve passivation, improve charge transfer, and provide good optical performance and structural protection, thereby improving the performance and reliability of the cell.

When the thickness of the silicon oxide layer is 1.3-2.0nm, effective surface passivation can be provided, suspension bonds on the surface of a silicon wafer are reduced, the surface recombination rate is reduced, and the open-circuit voltage of a battery is improved. Specifically, the thickness of the silicon oxide layer may be 1.3nm, 1.5nm, 1.7nm, or 2.0nm.

When the thickness of the anti-reflection layer is 60-70nm, the reflection of light on the surface of the battery can be effectively reduced, the light transmittance is increased, and the short-circuit current of the battery is improved. Wherein, the material of the anti-reflection layer can comprise one or more of silicon nitride, aluminum oxide and titanium oxide. Specifically, the thickness of the antireflection layer may be 60nm, 65nm, or 70nm.

The thicknesses of the silicon oxide layer and the anti-reflection layer cooperate to reduce the recombination of charge surfaces and improve the light utilization rate at the same time, thereby improving the overall photoelectric conversion efficiency of the battery.

In some embodiments, the intrinsic amorphous silicon layer has a thickness of 5-7nm, the doped microcrystalline silicon layer has a thickness of 20-25nm, and the transparent conductive oxide layer has a thickness of 45-60nm.

When the thickness of the doped microcrystalline silicon layer is 20-25nm, good conductivity and effective charge collection can be ensured, and excessive parasitic absorption is avoided. Specifically, the thickness of the doped microcrystalline silicon layer may be 20nm, 23nm, or 25nm.

An undoped intrinsic amorphous silicon layer is arranged between the silicon substrate and the doped microcrystalline silicon layer, so that the passivation effect can be improved, dangling bonds on the surface of the silicon wafer can be reduced, and the surface recombination rate can be reduced. When the thickness of the intrinsic amorphous silicon layer is 5-7nm, the second surface of the silicon substrate has good passivation effect, parasitic absorption of materials to light can be reduced, and the performance of the battery is improved. Specifically, the intrinsic amorphous silicon layer may have a thickness of 5nm, 6nm, or 7nm.

The transparent conductive oxide layer can collect and transmit current generated by photo-generated carriers, allow sunlight to pass through, reduce reflection and absorption loss of light, and improve photoelectric conversion efficiency of the battery. When the thickness of the transparent conductive oxide layer is 45-60nm, the conductivity and transparency can be balanced, and the high photoelectric conversion efficiency of the battery can be ensured. The material of the transparent conductive oxide layer may include one or more of Indium Tin Oxide (ITO), aluminum Zinc Oxide (AZO), fluorine doped tin oxide (FTO), among others. Specifically, the thickness of the transparent conductive oxide layer may be 45nm, 50nm, 55nm, or 60nm.

The thicknesses of the intrinsic amorphous silicon layer, the doped microcrystalline silicon layer and the transparent conductive oxide layer are mutually coordinated, so that surface recombination can be reduced, selective transmission of charges is realized, the light utilization rate is improved, the photoelectric conversion efficiency of the battery is improved, and the electrical performance of the battery is optimized.

As shown in fig. 1 to 7, the embodiment of the application further provides a method for preparing a solar cell, which includes:

S100, providing a silicon substrate 10, wherein the silicon substrate 10 is provided with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a first area 11 and a second area 12 which are alternately arranged;

S200, forming a tunneling oxide layer 21b, a doped polysilicon layer 22b and a SiN _x mask layer 23b which are sequentially stacked along the direction away from the silicon substrate 10 in the first region 11;

s300 forming a silicon oxide layer 24b and an antireflection layer 25b sequentially stacked in a direction away from the silicon substrate 10 in the second region 12;

S400, sequentially forming an intrinsic amorphous silicon layer 31, a doped microcrystalline silicon layer 32 and a transparent conductive oxide layer 33 on the second surface, wherein the doping type of the doped microcrystalline silicon layer 32 is opposite to that of the doped polycrystalline silicon layer 22 b;

S500, forming the first electrode 41 on the SiN _x mask layer 23b and forming the second electrode 42 on the transparent conductive oxide layer 33.

The silicon substrate can be subjected to texturing treatment, the size of the textured pyramid is 3-5 mu m, the textured structure can increase the roughness of the surface of the silicon substrate, the pulling-out force between the metal electrode and the silicon substrate can be improved, and the mechanical stability of the battery in long-term operation is ensured.

As shown in fig. 2 and 3, in some embodiments, in step S200, forming a tunnel oxide layer 21b, a doped polysilicon layer 22b, and a SiN _x mask layer 23b sequentially stacked in a direction away from the silicon substrate 10 in the first region 11 includes:

S210, sequentially forming an initial tunneling oxide layer 21a, an initial doped polysilicon layer 22a and an initial SiN _x mask layer 23a on a first surface;

And S220, sequentially removing the initial SiN _x mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a which are positioned in the second region 12 by adopting a first laser etching process, and reserving the initial SiN _x mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a which are positioned in the first region 11 to form a SiN _x mask layer 23b, a doped polysilicon layer 22b and a tunneling oxide layer 21b.

In step S210, an initial tunneling oxide layer and an initial doped polysilicon layer may be formed on the first surface using an LPCVD (low pressure chemical vapor deposition) method.

In some embodiments, the first laser etching process has a laser wavelength of 450-550nm and a laser power of 35-45W, specifically, a laser wavelength of 450nm, 500nm or 550nm and a laser power of 35W, 40W or 45W.

In some embodiments, in step S210, forming the initial doped polysilicon layer 22a includes:

s211, forming an initial intrinsic polycrystalline silicon layer on the initial tunneling oxide layer 21 a;

the initial intrinsic polysilicon layer is subjected to a doping process to form an initial doped polysilicon layer 22a S212.

In step S212, the doping process may be a P-type dopant element diffusion process to form a P-type initially doped polysilicon layer, and the doping process may also be an N-type dopant element diffusion process to form an N-type initially doped polysilicon layer.

In an alternative embodiment, when an initial tunneling oxide layer and an initial intrinsic polysilicon layer are formed on a first surface of a silicon substrate, an initial tunneling oxide layer and an initial intrinsic polysilicon layer are formed on a second surface and a side surface of the silicon substrate, doping treatment is performed on only the initial intrinsic polysilicon layer on the first surface to form an initial doped polysilicon layer, and after a SiN _x mask layer, the doped polysilicon layer and the tunneling oxide layer are formed, a chemical etching process is adopted to remove the initial tunneling oxide layer and the initial intrinsic polysilicon layer on the second surface and the side surface of the silicon substrate. The etching liquid in the chemical etching process can be SC1 cleaning liquid (including potassium hydroxide and isopropanol) or SC2 cleaning liquid (including sodium hydroxide, hydrogen peroxide and water).

As shown in fig. 4 and 5, in some embodiments, in step S300, forming a silicon oxide layer 24b and an antireflection layer 25b sequentially stacked in a direction away from the silicon substrate 10 in the second region 12 includes:

S310, sequentially forming an initial silicon oxide layer 24a and an initial antireflection layer 25a on a first surface with a tunneling oxide layer 21b, a doped polysilicon layer 22b and a SiN _x mask layer 23 b;

And S320, removing the initial silicon oxide layer 24a and the initial anti-reflection layer 25a which are positioned in the first region 11 by adopting a second laser etching process, exposing the SiN _x mask layer 23b, and reserving the initial silicon oxide layer 24a and the initial anti-reflection layer 25a which are positioned in the second region 12 to form a silicon oxide layer 24b and an anti-reflection layer 25b.

After the SiN _x mask layer, the doped polysilicon layer and the tunneling oxide layer are formed, before the silicon oxide layer is formed, the second area of the first surface is subjected to texturing treatment, the size of a textured pyramid is 2-3 mu m, and laser damage is treated.

After the silicon oxide layer and the anti-reflection layer are formed, the silicon substrate with the silicon oxide layer and the anti-reflection layer can be annealed to repair the damage of the second laser etching process to the silicon substrate, wherein the annealing temperature is 600-700 ℃ and the annealing time is 30-45min.

In some embodiments, in the second laser etching process, the laser wavelength is 520-540nm, the etching time is 0.7-0.8s, and the laser power is 30-40W. By adopting the parameters, the initial silicon oxide layer and the initial anti-reflection layer of the first region can be removed, but the SiN _x mask layer is not removed, so that the problems of over etching or insufficient etching are avoided. Specifically, in the second laser etching process, the laser wavelength may be 520nm, 532nm or 540nm, the etching time may be 0.7s, 0.75s or 0.8s, and the laser power may be 30W, 35W or 40W.

In step S400, a stacked intrinsic amorphous silicon layer and a doped microcrystalline silicon layer may be sequentially formed on the second surface using a PECVD (plasma enhanced chemical vapor deposition) method.

In step S400, a transparent conductive oxide layer may be formed on the doped microcrystalline silicon layer using a PVD (physical vapor deposition) method.

Before the intrinsic amorphous silicon layer is formed on the second surface, the second surface can be polished and surface treated to enhance the passivation effect of the second surface and make the reflectivity of the second surface 38-40%.

As shown in fig. 6 and 7, in step S500, the first electrode 41 is formed on the SiN _x mask layer 23b by electroplating. A photosensitive mask layer 26 may be disposed on the anti-reflection layer before the first electrode 41 is formed. The photosensitive mask layer 26 covers the anti-reflection layer 25b, the SiN _x mask layer 23b is exposed, pollution of electrode materials to the anti-reflection layer can be effectively avoided when the first electrode is formed, and the photosensitive mask layer is removed after the first electrode is formed.

As shown in fig. 7, in step S500, the second electrode 42 is formed on the transparent conductive oxide layer 33 using a screen printing method.

The following specific examples illustrate the application in further detail, but are not to be construed as limiting the application. Modifications and substitutions to methods, procedures, or conditions of the present application without departing from the spirit and nature of the application are intended to be within the scope of the present application.

Example 1

The solar cell of embodiment 1 includes:

A silicon substrate 10 (N-type silicon substrate), the silicon substrate 10 having a first face and a second face disposed opposite to each other, the first face having a first region 11 and a second region 12 disposed alternately;

A tunnel oxide layer 21b, a doped polysilicon layer 22b (N-type doped polysilicon layer), and a SiN _x mask layer 23b, which are located in the first region 11 and are sequentially stacked in a direction away from the silicon substrate 10;

a silicon oxide layer 24b and an antireflection layer 25b which are located in the second region 12 and are sequentially laminated in a direction away from the silicon substrate 10;

An intrinsic amorphous silicon layer 31, a doped microcrystalline silicon layer 32 (P-doped microcrystalline silicon layer), and a transparent conductive oxide layer 33, which are located on the second surface and are sequentially stacked in a direction away from the silicon substrate 10;

a first electrode 41 located on the SiN _x mask layer 23 b;

a second electrode 42 located on the transparent conductive oxide layer 33.

The method for manufacturing a solar cell of example 1 includes:

s100a, providing a silicon substrate 10, wherein the silicon substrate 10 is provided with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a first area 11 and a second area 12 which are alternately arranged;

s210a, sequentially forming an initial tunneling oxide layer 21a and an initial intrinsic polycrystalline silicon layer on a first surface by an LPCVD method;

s220a, carrying out doping treatment on the initial intrinsic polycrystalline silicon layer to form an initial doped polycrystalline silicon layer 22a;

S230a, forming an initial SiN _x mask layer 23a on the initial doped polysilicon layer 22 a;

S240a, sequentially removing the initial SiN _x mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a which are positioned in the second region 12 by adopting a first laser etching process, and reserving the initial SiN _x mask layer 23a, the initial doped polysilicon layer 22a and the initial tunneling oxide layer 21a which are positioned in the first region 11 to form a SiN _x mask layer 23b (45 mu m in width and 65nm in thickness), a doped polysilicon layer 22b (45 mu m in width and 100nm in thickness and 1.5E20/cm ³ in doping concentration) and a tunneling oxide layer 21b (1.3 nm in thickness), wherein in the first laser etching process, the laser wavelength is 500nm and the laser power is 40W;

S310a, sequentially forming an initial silicon oxide layer 24a and an initial anti-reflection layer 25a on a first surface with a tunneling oxide layer 21b, a doped polysilicon layer 22b and a SiN _x mask layer 23 b;

S320a, removing the initial silicon oxide layer 24a and the initial antireflection layer 25a which are positioned in the first region 11 by adopting a second laser etching process, exposing the SiN _x mask layer 23b, and reserving the initial silicon oxide layer 24a and the initial antireflection layer 25a which are positioned in the second region 12 to form a silicon oxide layer 24b (with the thickness of 1.6 nm) and an antireflection layer 25b (with the thickness of 70 nm), wherein in the second laser etching process, the laser wavelength is 532nm, the etching time is 0.75S, and the laser power is 35W);

s400a, sequentially forming an intrinsic amorphous silicon layer 31 (with the thickness of 5 nm) and a doped microcrystalline silicon layer 32 (with the thickness of 22 nm) on a second surface by adopting a PECVD method, forming a transparent conductive oxide layer 33 (with the thickness of 50 nm) on the doped microcrystalline silicon layer 32 by adopting a PVD method, wherein the doping type of the doped microcrystalline silicon layer 32 is opposite to that of the doped polycrystalline silicon layer 22 b;

S500a, forming a first electrode 41 on the SiN _x mask layer 23b by electroplating and forming a second electrode 42 on the transparent conductive oxide layer 33 by screen printing.

Example 2

The solar cell of example 2 was prepared with reference to the preparation method of example 1, except that the doped polysilicon layer was a P-type doped polysilicon layer and the doped microcrystalline silicon layer was an N-type doped microcrystalline silicon layer.

Example 3

The solar cell of example 3 was prepared with reference to the preparation method of example 1, except that the silicon substrate was a P-type silicon substrate.

Example 4

The solar cell of example 4 was prepared with reference to the preparation method of example 2, except that the silicon substrate was a P-type silicon substrate.

Example 5

The solar cell of example 5 was prepared with reference to the preparation method of example 1, except that,

The width of the SiN _x mask layer is 50 mu m, and the thickness of the SiN _x mask layer is 60nm;

The width of the doped polysilicon layer is 50 mu m, the thickness of the doped polysilicon layer is 110nm, and the doping concentration of the doped polysilicon layer is 1.2E20/cm ³;

the thickness of the tunneling oxide layer is 1.5nm;

The thickness of the silicon oxide layer is 1.8nm, and the thickness of the antireflection layer is 65nm;

The thickness of the intrinsic amorphous silicon layer is 6nm, the thickness of the doped microcrystalline silicon layer is 25nm, and the thickness of the transparent conductive oxide layer is 55nm.

Example 6

The solar cell of example 6 was prepared with reference to the preparation method of example 1, except that,

The width of the SiN _x mask layer is 40 mu m, and the thickness of the SiN _x mask layer is 68nm;

the width of the doped polysilicon layer is 40 mu m, the thickness of the doped polysilicon layer is 100nm, and the doping concentration of the doped polysilicon layer is 1.8E20/cm ³;

the thickness of the tunneling oxide layer is 2.0nm;

The thickness of the silicon oxide layer is 1.5nm, and the thickness of the antireflection layer is 65nm;

the intrinsic amorphous silicon layer has a thickness of 7nm, the doped microcrystalline silicon layer has a thickness of 23nm, and the transparent conductive oxide layer has a thickness of 55nm.

In order to more clearly illustrate the technical effects of the embodiments of the present application, the present application also indicates the solar cells of comparative examples 1 and 2.

Comparative example 1

Comparative example 1 is a TOPCon solar cell comprising:

A silicon substrate (N-type silicon substrate) having a first face and a second face disposed opposite to each other;

the P-type emitter, the anti-reflection layer and the first electrode are positioned on the first surface and are sequentially stacked along the direction far away from the silicon substrate;

the tunneling oxide layer, the N-type doped polycrystalline silicon layer, the anti-reflection layer and the second electrode are sequentially stacked on the second surface along the direction away from the silicon substrate.

Comparative example 2

Comparative example 2 is a silicon heterojunction solar cell comprising:

A silicon substrate (N-type silicon substrate) having a first face and a second face disposed opposite to each other;

The intrinsic amorphous silicon layer, the P-type doped amorphous silicon layer, the transparent conductive oxide layer and the first electrode are positioned on the first surface and are sequentially stacked along the direction far away from the silicon substrate;

the intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer, the transparent conductive oxide layer and the second electrode are sequentially stacked on the second surface along the direction far away from the silicon substrate.

The device performance of the solar cells of examples 1 to 6 and comparative examples 1 to 2 of the present application was tested below to obtain a short-circuit current density Jsc, an open-circuit voltage Voc, a fill factor FF, and a photoelectric conversion efficiency PCE of the respective cell devices, and the test results thereof are shown in table 1.

TABLE 1

As can be seen from the data in table 1, the short-circuit current density, the fill factor and the photoelectric conversion efficiency of the solar cell devices of examples 1 to 6 are all significantly improved compared with those of comparative examples 1 and 2, and the passivation materials of the solar cells of examples 1 to 6 have lower parasitic absorption, so that the current density is greatly improved, and the photoelectric conversion efficiency is also advantageous compared with that of conventional HJT.

In summary, in the solar cell in the embodiment of the application, the tunneling oxide layer, the doped polysilicon layer, the SiN _x mask layer and the first electrode are sequentially stacked in the first area of the first surface, the silicon oxide layer and the antireflection layer are sequentially stacked in the second area of the first surface, the doped polysilicon layer is only arranged in the first area of the solar cell, the doped polysilicon layer is not arranged in the second area of the solar cell, which is conducive to reducing parasitic absorption loss, and the intrinsic amorphous silicon layer, the doped microcrystalline silicon layer and the transparent conductive oxide layer are sequentially stacked in the second surface of the solar cell, so that passivation effect is improved, and cell conversion efficiency is improved. The solar cell provided by the embodiment of the application can effectively improve the double-sided rate and the photoelectric conversion efficiency of the cell through the specific structures of the first surface and the second surface.

An embodiment of the present application provides a photovoltaic module (not shown) including the solar cell according to any one of the embodiments above.

The embodiment of the application can provide a photovoltaic system which comprises the photovoltaic module in the embodiment. The photovoltaic module has the advantages that the photovoltaic system also has, and the description thereof is omitted. The photovoltaic system has wide application fields, and is not limited to photovoltaic power stations, such as ground power stations, roof power stations and water surface power stations, but also comprises various devices and apparatuses for generating power by utilizing solar energy, such as a user solar power supply, a solar street lamp, a solar automobile, a solar building and the like. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system may be applied to all fields where solar energy is required to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system can comprise a photovoltaic array, a confluence box and an inverter, wherein the photovoltaic array can be an array combination of a plurality of photovoltaic modules, for example, the photovoltaic modules can form a plurality of photovoltaic arrays, the photovoltaic arrays are connected with the confluence box, the confluence box can confluence currents generated by the photovoltaic arrays, and the confluence currents flow through the inverter to be converted into alternating currents required by a commercial power grid and then are connected with the commercial power network so as to realize solar power supply.

It is noted that the terms "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience of description and to simplify the description, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application. The orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the terms "first," "second," "front," "back," and the like in the description and claims of the present application and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should also be noted that references to "one embodiment," "another embodiment," "an embodiment," etc., in the present application mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application as broadly described. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with any embodiment, it is intended that such feature, structure, or characteristic be implemented within the scope of the application.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

It should be noted that the foregoing is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present application.

Claims (11)

1. A solar cell, comprising:

a silicon substrate having a first face and a second face disposed opposite each other, the first face having alternately disposed first and second regions;

The tunneling oxide layer, the doped polysilicon layer and the SiN _x mask layer are positioned in the first region and are sequentially stacked along the direction away from the silicon substrate;

A silicon oxide layer and an antireflection layer which are positioned in the second region and are sequentially laminated along a direction away from the silicon substrate;

The intrinsic amorphous silicon layer, the doped microcrystalline silicon layer and the transparent conductive oxide layer are positioned on the second surface and sequentially stacked along the direction far away from the silicon substrate, wherein the doping type of the doped microcrystalline silicon layer is opposite to that of the doped polycrystalline silicon layer;

A first electrode on the SiN _x mask layer;

And a second electrode on the transparent conductive oxide layer.

2. The solar cell of claim 1, wherein the width of the doped polysilicon layer is the same as the width of the SiN _x mask layer, the width of the doped polysilicon layer being 40-50 μm.

3. The solar cell of claim 1, wherein the doped polysilicon layer has a doping concentration of 1E20-2E20/cm ³.

4. A solar cell according to any one of claims 1 to 3, wherein the tunneling oxide layer has a thickness of 1.3-2.0nm, the doped polysilicon layer has a thickness of 90-120nm, the SiN _x mask layer has a thickness of 60-70nm, and/or

The thickness of the silicon oxide layer is 1.3-2.0nm, and the thickness of the anti-reflection layer is 60-70nm.

5. A solar cell according to any of claims 1 to 3, wherein the intrinsic amorphous silicon layer has a thickness of 5-7nm, the doped microcrystalline silicon layer has a thickness of 20-25nm, and the transparent conductive oxide layer has a thickness of 45-60nm.

6. A method of manufacturing a solar cell, comprising:

Providing a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface which are oppositely arranged, and the first surface is provided with a first area and a second area which are alternately arranged;

Forming a tunneling oxide layer, a doped polysilicon layer and a SiN _x mask layer which are sequentially stacked along the direction away from the silicon substrate in the first region;

forming a silicon oxide layer and an anti-reflection layer sequentially stacked in a direction away from the silicon substrate in the second region;

Sequentially forming an intrinsic amorphous silicon layer, a doped microcrystalline silicon layer and a transparent conductive oxide layer on the second surface, wherein the doping type of the doped microcrystalline silicon layer is opposite to that of the doped polycrystalline silicon layer;

And forming a first electrode on the SiN _x mask layer and forming a second electrode on the transparent conductive oxide layer.

7. The method of manufacturing a solar cell according to claim 6, wherein forming a tunnel oxide layer, a doped polysilicon layer, and a SiN _x mask layer sequentially stacked in a direction away from the silicon substrate in the first region comprises:

sequentially forming an initial tunneling oxide layer, an initial doped polysilicon layer and an initial SiN _x mask layer on the first surface;

And sequentially removing the initial SiN _x mask layer, the initial doped polysilicon layer and the initial tunneling oxide layer which are positioned in the second region by adopting a first laser etching process, and reserving the initial SiN _x mask layer, the initial doped polysilicon layer and the initial tunneling oxide layer which are positioned in the first region to form the SiN _x mask layer, the doped polysilicon layer and the tunneling oxide layer.

8. The method of claim 7, wherein forming the initially doped polysilicon layer comprises:

forming an initial intrinsic polysilicon layer on the initial tunneling oxide layer;

And doping the initial intrinsic polycrystalline silicon layer to form the initial doped polycrystalline silicon layer.

9. The method of manufacturing a solar cell according to claim 6, wherein forming a silicon oxide layer and an antireflection layer sequentially stacked in a direction away from the silicon substrate in the second region comprises:

sequentially forming an initial silicon oxide layer and an initial antireflection layer on a first surface with the tunneling oxide layer, the doped polysilicon layer and the SiN _x mask layer;

And removing the initial silicon oxide layer and the initial antireflection layer which are positioned in the first region by adopting a second laser etching process, exposing the SiN _x mask layer, and reserving the initial silicon oxide layer and the initial antireflection layer which are positioned in the second region to form the silicon oxide layer and the antireflection layer.

10. The method of claim 9, wherein in the second laser etching process, the laser wavelength is 520-540nm, the etching time is 0.7-0.8s, and the laser power is 30-40W.

11. A photovoltaic module comprising a solar cell according to any one of claims 1-5.