CN118507445B - Chip packaging structure and preparation method thereof - Google Patents
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 47
- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 230000017525 heat dissipation Effects 0.000 claims abstract description 224
- 229910000679 solder Inorganic materials 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 22
- 230000007423 decrease Effects 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 10
- 238000012546 transfer Methods 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 5
- 239000003292 glue Substances 0.000 abstract description 47
- 238000011049 filling Methods 0.000 abstract description 40
- 230000000694 effects Effects 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 150
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 7
- 230000035882 stress Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 4
- 230000032798 delamination Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 1
- 101000827703 Homo sapiens Polyphosphoinositide phosphatase Proteins 0.000 description 1
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 102100023591 Polyphosphoinositide phosphatase Human genes 0.000 description 1
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001393 microlithography Methods 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000013517 stratification Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
技术领域Technical Field
本发明涉及芯片封装领域，具体而言，涉及一种芯片封装结构和芯片封装结构的制备方法。The present invention relates to the field of chip packaging, and in particular to a chip packaging structure and a method for preparing the chip packaging structure.
背景技术Background Art
随着半导体行业的快速发展，chiplet技术新的设计方式，将不同功能的小芯片封装在一起，形成异构集成芯片封装结构，随着芯片的输入/输出密度越来越高造成集成在单个封装件内的数量已经显著增加。各种2.5D和3D封装技术作为多芯片封装方案来连接单个封装件内的相邻芯片焊盘线路，通常的技术是将多个芯片采用倒装方式直接贴装在转接板上，其倒装芯片采用微凸点设计，其凸点直径较小(例如直径小于50um)以及凸点的间隙较小(例如小于50um)，以提升倒装芯片凸点输出I/O端数量。With the rapid development of the semiconductor industry, the new design of chiplet technology packages small chips with different functions together to form a heterogeneous integrated chip packaging structure. As the input/output density of chips increases, the number of chips integrated in a single package has increased significantly. Various 2.5D and 3D packaging technologies are used as multi-chip packaging solutions to connect adjacent chip pad lines in a single package. The usual technology is to directly mount multiple chips on the adapter board in a flip-chip manner. The flip chip adopts a micro-bump design with a small bump diameter (e.g., less than 50um in diameter) and a small bump gap (e.g., less than 50um) to increase the number of flip chip bump output I/O terminals.
然而转接板上的I/O端数量也随之增加，且转接板上的芯片集成度提升，导致其芯片受热冲击影响更大，故散热需求越来越高，目前的设计难以满足散热需求。并且，在上板时，封装体与PCB板之间需要通过填充胶固定，其结合力较差，导致容易出现脱落。However, the number of I/O terminals on the adapter board has also increased, and the integration of chips on the adapter board has increased, resulting in greater thermal shock to the chips, so the heat dissipation requirements are getting higher and higher, and the current design is difficult to meet the heat dissipation requirements. In addition, when mounting the board, the package body and the PCB board need to be fixed with filling glue, and the bonding strength is poor, which makes it easy to fall off.
发明内容Summary of the invention
本发明的目的包括，例如，提供了一种芯片封装结构和芯片封装结构的制备方法，其能够有效地对芯片和线路进行散热，提升散热效果，并能够避免胶层受应力分层，提升上板时的结合力。The objectives of the present invention include, for example, providing a chip packaging structure and a method for preparing the chip packaging structure, which can effectively dissipate heat from chips and circuits, improve the heat dissipation effect, and avoid stress delamination of the adhesive layer, thereby improving the bonding force when mounting the board.
本发明的实施例可以这样实现：The embodiments of the present invention can be implemented as follows:
第一方面，本发明提供一种芯片封装结构，包括：In a first aspect, the present invention provides a chip packaging structure, comprising:
基底转接板，所述基底转接板具有第一表面和第二表面，所述第一表面设置有朝向所述第二表面的第一散热凹槽，所述第二表面设置有朝向所述第一表面并与所述第一散热凹槽对应的第二散热凹槽；A base adapter plate, the base adapter plate having a first surface and a second surface, the first surface being provided with a first heat dissipation groove facing the second surface, and the second surface being provided with a second heat dissipation groove facing the first surface and corresponding to the first heat dissipation groove;
第一布线层，所述第一布线层设置在所述第一表面，并覆盖在所述第一散热凹槽上；A first wiring layer, the first wiring layer is arranged on the first surface and covers the first heat dissipation groove;
第二布线层，所述第二布线层设置在所述第二表面，并覆盖在所述第二散热凹槽上；A second wiring layer, the second wiring layer is arranged on the second surface and covers the second heat dissipation groove;
导电柱，所述导电柱设置在所述基底转接板内，并与所述第一散热凹槽和所述第二散热凹槽间隔设置，且所述导电柱的两端分别连接至所述第一布线层和所述第二布线层；A conductive column, wherein the conductive column is disposed in the base adapter plate and is spaced apart from the first heat dissipation groove and the second heat dissipation groove, and two ends of the conductive column are respectively connected to the first wiring layer and the second wiring layer;
封装芯片，所述封装芯片贴设在所述第一布线层远离所述基底转接板的一侧表面；A packaged chip, wherein the packaged chip is attached to a surface of the first wiring layer on a side away from the base adapter plate;
第一焊球，所述第一焊球设置在所述第二布线层远离所述基底转接板的一侧表面。A first solder ball is disposed on a surface of the second wiring layer on a side away from the base transfer board.
在可选的实施方式中，所述第一散热凹槽的宽度沿朝向所述第二表面的方向逐渐减小；所述第二散热凹槽的宽度沿朝向所述第一表面的方向逐渐减小。In an optional embodiment, the width of the first heat dissipation groove gradually decreases in a direction toward the second surface; and the width of the second heat dissipation groove gradually decreases in a direction toward the first surface.
在可选的实施方式中，所述第一散热凹槽的侧壁形成有多个第一边沿台阶，多个所述第一边沿台阶的宽度朝向第二表面的方向逐渐减小；所述第二散热凹槽的侧壁形成有多个第二边沿台阶，多个所述第二边沿台阶的宽度朝向第一表面的方向逐渐减小。In an optional embodiment, the side wall of the first heat dissipation groove is formed with a plurality of first edge steps, and the width of the plurality of first edge steps gradually decreases toward the direction of the second surface; the side wall of the second heat dissipation groove is formed with a plurality of second edge steps, and the width of the plurality of second edge steps gradually decreases toward the direction of the first surface.
在可选的实施方式中，所述第一边沿台阶和所述第二边沿台阶对称设置。In an optional embodiment, the first edge step and the second edge step are symmetrically arranged.
在可选的实施方式中，所述第一散热凹槽和所述第二散热凹槽对应连通。In an optional embodiment, the first heat dissipation groove and the second heat dissipation groove are correspondingly connected.
在可选的实施方式中，所述封装芯片包括间隔设置在所述第一布线层上的第一芯片和第二芯片，所述第一芯片和所述第二芯片之间的所述第一布线层上设置有第一缺口，所述第一缺口与位于中部的所述第一散热凹槽连通，所述第二布线层上设置有第二缺口，所述第二缺口与位于中部的第二散热凹槽连通。In an optional embodiment, the packaged chip includes a first chip and a second chip spaced apart on the first wiring layer, a first notch is provided on the first wiring layer between the first chip and the second chip, the first notch is connected to the first heat dissipation groove located in the middle, and a second notch is provided on the second wiring layer, the second notch is connected to the second heat dissipation groove located in the middle.
在可选的实施方式中，所述第一布线层上还设置有第一填充胶层，所述第一填充胶层至少部分包覆于所述第一芯片和所述第二芯片，并至少部分填充至位于中部的所述第一散热凹槽，所述第二布线层外还设置有第二填充胶层，所述第二填充胶层包覆在所述第一焊球外，用于接合至电路板，且所述第二填充胶层填充至位于边缘的所述第一散热凹槽和所述第二散热凹槽，并部分填充至位于中部的所述第二散热凹槽。In an optional embodiment, a first filling glue layer is also provided on the first wiring layer, and the first filling glue layer at least partially covers the first chip and the second chip, and at least partially fills the first heat dissipation groove located in the middle. A second filling glue layer is also provided outside the second wiring layer, and the second filling glue layer covers the outside of the first solder ball for bonding to the circuit board, and the second filling glue layer fills the first heat dissipation groove and the second heat dissipation groove located at the edge, and partially fills the second heat dissipation groove located in the middle.
在可选的实施方式中，位于中部的所述第一散热凹槽内的所述第一填充胶层与位于中部的所述第二散热凹槽内的所述第二填充胶层相接，且所述第二填充胶层相对于所述第二表面的高度大于所述第一填充胶层相对于所述第一表面的高度。In an optional embodiment, the first filling glue layer in the first heat dissipation groove located in the middle is connected to the second filling glue layer in the second heat dissipation groove located in the middle, and the height of the second filling glue layer relative to the second surface is greater than the height of the first filling glue layer relative to the first surface.
在可选的实施方式中，所述第一散热凹槽的深度和所述第二散热凹槽的深度均小于所述基底转接板的厚度的一半，以使所述第一散热凹槽和所述第二散热凹槽相互隔离。In an optional embodiment, a depth of the first heat dissipation groove and a depth of the second heat dissipation groove are both less than half of a thickness of the base adapter plate, so that the first heat dissipation groove and the second heat dissipation groove are isolated from each other.
在可选的实施方式中，所述基底转接板内还设置有散热层，所述散热层位于所述第一散热凹槽和所述第二散热凹槽之间，且所述散热层靠近所述第一表面的一侧被配置为所述第一散热凹槽的底壁，所述散热层靠近所述第二表面的一侧被配置为所述第二散热凹槽的底壁。In an optional embodiment, a heat dissipation layer is also provided in the base adapter plate, and the heat dissipation layer is located between the first heat dissipation groove and the second heat dissipation groove, and the side of the heat dissipation layer close to the first surface is configured as the bottom wall of the first heat dissipation groove, and the side of the heat dissipation layer close to the second surface is configured as the bottom wall of the second heat dissipation groove.
在可选的实施方式中，所述封装芯片背离所述基底转接板的一侧还设置有堆叠转接板，所述堆叠转接板具有第三表面和第四表面，所述第三表面设置有朝向所述第四表面的第三散热凹槽，所述第四表面设置有朝向所述第三表面并与所述第三散热凹槽对应的第四散热凹槽，所述第三表面设置有第三布线层，所述第四表面设置有第四布线层，所述第三布线层远离所述堆叠转接板的一侧设置有堆叠芯片，所述堆叠芯片与所述封装芯片相贴合，所述第三布线层上还设置有第二焊球，所述第二焊球与所述第一布线层连接。In an optional embodiment, a stacking adapter board is also provided on the side of the packaged chip facing away from the base adapter board, the stacking adapter board having a third surface and a fourth surface, the third surface is provided with a third heat dissipation groove facing the fourth surface, the fourth surface is provided with a fourth heat dissipation groove facing the third surface and corresponding to the third heat dissipation groove, the third surface is provided with a third wiring layer, the fourth surface is provided with a fourth wiring layer, a stacked chip is provided on the side of the third wiring layer away from the stacking adapter board, the stacked chip is bonded to the packaged chip, and a second solder ball is also provided on the third wiring layer, and the second solder ball is connected to the first wiring layer.
第二方面，本发明提供一种芯片封装结构的制备方法，用于制备如前述实施方式任一项所述的芯片封装结构，所述制备方法包括：In a second aspect, the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure as described in any one of the above embodiments, and the preparation method comprises:
在基底转接板的第一表面刻蚀开孔后电镀形成导电柱；A hole is etched on the first surface of the base adapter plate and then electroplated to form a conductive column;
在所述第一表面刻蚀形成第一散热凹槽；Etching a first heat dissipation groove on the first surface;
在所述第一表面形成覆盖所述第一散热凹槽，并与所述导电柱连接的第一布线层；forming a first wiring layer on the first surface covering the first heat dissipation groove and connected to the conductive column;
在所述第一布线层远离所述第一表面的一侧贴设载具；A carrier is attached to a side of the first wiring layer away from the first surface;
研磨所述基底转接板远离所述第一表面的一侧，以形成第二表面并露出所述导电柱；Grinding a side of the substrate transfer plate away from the first surface to form a second surface and expose the conductive column;
在所述第二表面刻蚀形成第二散热凹槽；Etching a second heat dissipation groove on the second surface;
在所述第二表面形成覆盖所述第二散热凹槽，并与所述导电柱连接的第二布线层；forming a second wiring layer on the second surface covering the second heat dissipation groove and connected to the conductive column;
去除所述载具；removing the carrier;
在所述第一布线层贴设封装芯片；Attaching a packaged chip to the first wiring layer;
在所述第二布线层形成第一焊球。A first solder ball is formed on the second wiring layer.
本发明实施例的有益效果包括，例如：The beneficial effects of the embodiments of the present invention include, for example:
本发明实施例提供的芯片封装结构和芯片封装结构的制备方法，在基底转接板的第一表面设置第一散热凹槽，在基底转接板的第二表面设置第二散热凹槽，第一散热凹槽和第二散热凹槽对应，第一布线层和第二布线层分别分布在第一表面和第二表面，并分别覆盖第一散热凹槽和第二散热凹槽，而基底转接板中还设只有连接第一布线层和第二布线层的导电柱。相较于现有技术，本发明实施例通过增设第一散热凹槽和第二散热凹槽，位于中部的第一散热凹槽和第二散热凹槽能够在覆盖布线结构后形成内部空心结构，从而大幅提升散热效果，而位于边缘的第一散热凹槽和第二散热凹槽则可以在上板时增大与底部填充胶的接触面积，提升上板的结合力。The chip packaging structure and the preparation method of the chip packaging structure provided by the embodiment of the present invention are as follows: a first heat dissipation groove is set on the first surface of the base adapter plate, and a second heat dissipation groove is set on the second surface of the base adapter plate, the first heat dissipation groove and the second heat dissipation groove correspond to each other, the first wiring layer and the second wiring layer are respectively distributed on the first surface and the second surface, and respectively cover the first heat dissipation groove and the second heat dissipation groove, and the base adapter plate is also provided with a conductive column that only connects the first wiring layer and the second wiring layer. Compared with the prior art, the embodiment of the present invention adds the first heat dissipation groove and the second heat dissipation groove, and the first heat dissipation groove and the second heat dissipation groove located in the middle can form an internal hollow structure after covering the wiring structure, thereby greatly improving the heat dissipation effect, and the first heat dissipation groove and the second heat dissipation groove located at the edge can increase the contact area with the bottom filling glue when the board is mounted, thereby improving the bonding force of the board.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本发明的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
图1为本发明实施例提供的第一种芯片封装结构的示意图；FIG1 is a schematic diagram of a first chip packaging structure provided by an embodiment of the present invention;
图2为本发明实施例提供的第一种芯片封装结构的上板示意图；FIG2 is a schematic diagram of an upper plate of a first chip packaging structure provided by an embodiment of the present invention;
图3为本发明实施例提供的第二种芯片封装结构的上板示意图；FIG3 is a schematic diagram of an upper plate of a second chip packaging structure provided by an embodiment of the present invention;
图4为本发明实施例提供的第二种芯片封装结构的示意图；FIG4 is a schematic diagram of a second chip packaging structure provided by an embodiment of the present invention;
图5为本发明实施例提供的第三种芯片封装结构的示意图；FIG5 is a schematic diagram of a third chip packaging structure provided by an embodiment of the present invention;
图6为本发明实施例提供的第四种芯片封装结构的上板示意图；6 is a schematic diagram of an upper plate of a fourth chip packaging structure provided by an embodiment of the present invention;
图7为本发明实施例提供的第五种芯片封装结构的上板示意图；7 is a schematic diagram of an upper plate of a fifth chip packaging structure provided by an embodiment of the present invention;
图8至图17为本发明实施例提供的芯片封装结构的制备方法的工艺流程图。8 to 17 are process flow charts of a method for preparing a chip packaging structure provided in an embodiment of the present invention.
图标：100-芯片封装结构；110-基底转接板；111-第一表面；112-第二表面；113-第一散热凹槽；114-第二散热凹槽；115-第一边沿台阶；116-第二边沿台阶；117-散热层；120-第一布线层；121-第一填充胶层；122-第一缺口；130-第二布线层；131-第二填充胶层；132-第二缺口；140-导电柱；150-第一焊球；160-封装芯片；161-第一芯片；162-第二芯片；170-堆叠转接板；171-第三布线层；172-第四布线层；173-第二焊球；180-堆叠芯片；200-PCB板；300-载具。Icons: 100-chip packaging structure; 110-substrate adapter board; 111-first surface; 112-second surface; 113-first heat dissipation groove; 114-second heat dissipation groove; 115-first edge step; 116-second edge step; 117-heat dissipation layer; 120-first wiring layer; 121-first filling glue layer; 122-first notch; 130-second wiring layer; 131-second filling glue layer; 132-second notch; 140-conductive column; 150-first solder ball; 160-packaged chip; 161-first chip; 162-second chip; 170-stacked adapter board; 171-third wiring layer; 172-fourth wiring layer; 173-second solder ball; 180-stacked chip; 200-PCB board; 300-carrier.
具体实施方式DETAILED DESCRIPTION
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
在本发明的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.
正如背景技术中所公开的，现有技术中的转接板上的I/O端数量增加，且转接板上的芯片集成度提升，导致其芯片受热冲击影响更大，故散热需求越来越高，目前的设计难以满足散热需求。并且，在上板时，封装体与PCB板之间需要通过填充胶固定，其结合力较差，由于受其热膨胀系数不一致，容易导致其转接板边缘胶层分层，进而容易出现脱落。As disclosed in the background technology, the number of I/O terminals on the adapter board in the prior art increases, and the integration of the chip on the adapter board increases, resulting in a greater impact of thermal shock on the chip, so the heat dissipation requirements are getting higher and higher, and the current design is difficult to meet the heat dissipation requirements. In addition, when mounting the board, the package body and the PCB board need to be fixed by filling glue, and the bonding force is poor. Due to the inconsistency of their thermal expansion coefficients, it is easy to cause the glue layer at the edge of the adapter board to delaminate, and then it is easy to fall off.
进一步地，采用三维堆叠结构进行封装时，其堆叠结构锡球较大，且堆叠结构各个构件的材料热膨胀系数不一，容易导致其焊球裂痕或者焊点焊接IMC层裂痕，导致电性失效。Furthermore, when a three-dimensional stacking structure is used for packaging, the solder balls of the stacking structure are relatively large, and the thermal expansion coefficients of the materials of the various components of the stacking structure are different, which can easily lead to cracks in the solder balls or cracks in the IMC layer of the solder joints, resulting in electrical failure.
此外，现有技术中多颗倒装芯片贴装在转接板上后，需要利用底部填充胶体作为保护层，保护倒装芯片的焊点。然而在芯片和芯片之间存在沟道，底部填充胶体在沿着边缘芯片划胶时，依靠胶体的毛细作用填充多颗芯片底部，也必定会填充沟道，此时转接板容易受应力，并容易受胶体产生的应力导致芯片隐裂。In addition, in the prior art, after multiple flip chips are mounted on the adapter board, a bottom filler colloid is needed as a protective layer to protect the solder joints of the flip chips. However, there is a trench between the chips, and when the bottom filler colloid is glued along the edge chips, it relies on the capillary action of the colloid to fill the bottom of multiple chips, and it will definitely fill the trench. At this time, the adapter board is easily stressed, and the stress generated by the colloid is easily caused to cause hidden cracks in the chip.
为了解决上述问题，本发明实施例提供了一种新的芯片封装结构及其制备方法，需要说明的是，在不冲突的情况下，本发明的实施例中的特征可以相互结合。In order to solve the above problems, an embodiment of the present invention provides a new chip packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.
本发明实施例提供的芯片封装结构，其能够有效地对芯片和线路进行散热，提升散热效果，并能够避免胶层受应力分层，提升上板时的结合力。The chip packaging structure provided by the embodiment of the present invention can effectively dissipate heat from the chip and the circuit, thereby improving the heat dissipation effect, and can prevent the adhesive layer from being delaminated due to stress, thereby improving the bonding force when mounting the board.
参见图1和图2，本发明实施例提供的芯片封装结构100，包括基底转接板110、第一布线层120、第二布线层130、导电柱140、第一焊球150和封装芯片160，基底转接板110具有第一表面111和第二表面112，第一表面111设置有朝向第二表面112的第一散热凹槽113，第二表面112设置有朝向第一表面111并与第一散热凹槽113对应的第二散热凹槽114；第一布线层120设置在第一表面111，并覆盖在第一散热凹槽113上；第二布线层130设置在第二表面112，并覆盖在第二散热凹槽114上；导电柱140设置在基底转接板110内，并与第一散热凹槽113和第二散热凹槽114间隔设置，且导电柱140的两端分别连接至第一布线层120和第二布线层130；封装芯片160贴设在第一布线层120远离基底转接板110的一侧表面；第一焊球150设置在第二布线层130远离基底转接板110的一侧表面。1 and 2 , a chip packaging structure 100 provided in an embodiment of the present invention includes a base adapter plate 110, a first wiring layer 120, a second wiring layer 130, a conductive column 140, a first solder ball 150 and a packaged chip 160. The base adapter plate 110 has a first surface 111 and a second surface 112. The first surface 111 is provided with a first heat dissipation groove 113 facing the second surface 112, and the second surface 112 is provided with a second heat dissipation groove 114 facing the first surface 111 and corresponding to the first heat dissipation groove 113. The first wiring layer 120 is provided on the first surface 111. , and covers the first heat dissipation groove 113; the second wiring layer 130 is arranged on the second surface 112, and covers the second heat dissipation groove 114; the conductive column 140 is arranged in the base adapter board 110, and is spaced from the first heat dissipation groove 113 and the second heat dissipation groove 114, and the two ends of the conductive column 140 are respectively connected to the first wiring layer 120 and the second wiring layer 130; the packaged chip 160 is attached to a side surface of the first wiring layer 120 away from the base adapter board 110; the first solder ball 150 is arranged on a side surface of the second wiring layer 130 away from the base adapter board 110.
需要说明的是，第一散热凹槽113和第二散热凹槽114均可以分布在基底转接板110的边缘和中部，位于边缘的第一散热凹槽113和第二散热凹槽114呈开放槽口状，位于中间的第一散热凹槽113和第二散热凹槽114分布由第一布线层120和第二布线层130覆盖。通过增设第一散热凹槽113和第二散热凹槽114，位于中部的第一散热凹槽113和第二散热凹槽114能够在覆盖布线结构后形成内部空心结构，从而大幅提升散热效果，而位于边缘的第一散热凹槽113和第二散热凹槽114则可以在上板时增大与底部填充胶的接触面积，提升上板的结合力。It should be noted that the first heat dissipation groove 113 and the second heat dissipation groove 114 can be distributed at the edge and the middle of the base adapter plate 110. The first heat dissipation groove 113 and the second heat dissipation groove 114 located at the edge are in the shape of an open slot, and the first heat dissipation groove 113 and the second heat dissipation groove 114 located in the middle are covered by the first wiring layer 120 and the second wiring layer 130. By adding the first heat dissipation groove 113 and the second heat dissipation groove 114, the first heat dissipation groove 113 and the second heat dissipation groove 114 located in the middle can form an internal hollow structure after covering the wiring structure, thereby greatly improving the heat dissipation effect, while the first heat dissipation groove 113 and the second heat dissipation groove 114 located at the edge can increase the contact area with the bottom filling glue when the board is mounted, thereby improving the bonding force of the board.
值得注意的是，在上板时，可以将该芯片封装结构100贴设在一PCB板200上，具体地，可以将第一焊球150与PCB板200上的焊盘焊接，然后在芯片封装结构100的底部增设底部胶层，实现对焊接结构的保护。由于位于边缘的第一散热凹槽113和第二散热凹槽114为开放式槽口状，因此PCB板200上的胶层会延伸填充至第一散热凹槽113和第二散热凹槽114中，从而能够提升芯片封装结构100与PCB板200之间的结合力。It is worth noting that when mounting, the chip packaging structure 100 can be attached to a PCB board 200. Specifically, the first solder ball 150 can be soldered to the solder pad on the PCB board 200, and then a bottom glue layer is added at the bottom of the chip packaging structure 100 to protect the soldering structure. Since the first heat dissipation groove 113 and the second heat dissipation groove 114 located at the edge are open slot-shaped, the glue layer on the PCB board 200 will extend and fill the first heat dissipation groove 113 and the second heat dissipation groove 114, thereby improving the bonding force between the chip packaging structure 100 and the PCB board 200.
在一些实施例中，第一散热凹槽113的宽度沿朝向第二表面112的方向逐渐减小；第二散热凹槽114的宽度沿朝向第一表面111的方向逐渐减小。具体地，此处第一散热凹槽113和第二散热凹槽114的宽度，指的是第一散热凹槽113和第二散热凹槽114内沿水平方向的最大宽度，第一散热凹槽113靠近第一表面111的宽度最大，并朝向第二表面112宽度递减，在实际制备时可以在第一表面111开槽，一层一层依次制备尺寸逐渐减小的槽口；同样地，第二散热凹槽114靠近第二表面112的宽度最大，并朝向第一表面111宽度递减，在实际制备时可以在第二表面112开槽，一层一层依次制备尺寸逐渐减小的槽口。In some embodiments, the width of the first heat dissipation groove 113 gradually decreases in the direction toward the second surface 112; the width of the second heat dissipation groove 114 gradually decreases in the direction toward the first surface 111. Specifically, the width of the first heat dissipation groove 113 and the second heat dissipation groove 114 here refers to the maximum width in the first heat dissipation groove 113 and the second heat dissipation groove 114 along the horizontal direction. The width of the first heat dissipation groove 113 is the largest near the first surface 111, and the width decreases toward the second surface 112. In actual preparation, the first surface 111 can be grooved, and the grooves with gradually decreasing sizes can be prepared layer by layer. Similarly, the second heat dissipation groove 114 is the largest near the second surface 112, and the width decreases toward the first surface 111. In actual preparation, the second surface 112 can be grooved, and the grooves with gradually decreasing sizes can be prepared layer by layer.
在一些实施例中，第一散热凹槽113的侧壁形成有多个第一边沿台阶115，多个第一边沿台阶115的宽度朝向第二表面112的方向逐渐减小；第二散热凹槽114的侧壁形成有多个第二边沿台阶116，多个第二边沿台阶116的宽度朝向第一表面111的方向逐渐减小。具体地，位于中部的第一散热凹槽113内的第一边沿台阶115呈环状（矩形环或圆环），位于边缘的第一散热凹槽113内的第一边沿台阶115呈半环状，且宽度朝向第二表面112依次减小；位于中部的第二散热凹槽114的第二边沿台阶116呈环状，位于边缘的第二散热凹槽114的第二边沿台阶116呈半环状，且宽度朝向第一表面111依次减小。通过采用台阶状结构，在制备时可以一层一层依次制备，降低了制作难度。In some embodiments, the sidewall of the first heat dissipation groove 113 is formed with a plurality of first edge steps 115, and the width of the plurality of first edge steps 115 gradually decreases toward the direction of the second surface 112; the sidewall of the second heat dissipation groove 114 is formed with a plurality of second edge steps 116, and the width of the plurality of second edge steps 116 gradually decreases toward the direction of the first surface 111. Specifically, the first edge step 115 in the first heat dissipation groove 113 located in the middle is annular (rectangular ring or circular ring), and the first edge step 115 in the first heat dissipation groove 113 located at the edge is semi-annular, and the width decreases successively toward the second surface 112; the second edge step 116 in the second heat dissipation groove 114 located in the middle is annular, and the second edge step 116 in the second heat dissipation groove 114 located at the edge is semi-annular, and the width decreases successively toward the first surface 111. By adopting a step-shaped structure, it can be prepared layer by layer during preparation, which reduces the difficulty of production.
值得注意的是，本实施例中第一散热凹槽113和第二散热凹槽114均采用套娃式回形结构，并且槽口面积随着开槽深度的增加依次减小。需要说明的是，此处提及的宽度，指的是开槽过程中的开槽宽度。在本发明其他较佳的实施例中，第一散热凹槽113和第二散热凹槽114的侧壁也可以呈连续弧面，从而形成平滑的侧壁。It is worth noting that in this embodiment, both the first heat dissipation groove 113 and the second heat dissipation groove 114 adopt a nesting doll-shaped structure, and the notch area decreases with the increase of the groove depth. It should be noted that the width mentioned here refers to the groove width during the groove process. In other preferred embodiments of the present invention, the side walls of the first heat dissipation groove 113 and the second heat dissipation groove 114 can also be continuous arc surfaces to form smooth side walls.
在一些实施例中，第一边沿台阶115和第二边沿台阶116对称设置。具体地，第一边沿台阶115和第二边沿台阶116呈上下对称设计，一方面，在实际制备时可以采用同样的开槽参数开槽形成第一散热凹槽113和第二散热凹槽114，简化了制程。另一方面，采用对称设计也能够使得基底转接板110上下部分的散热能力相同，提升了散热均匀性。In some embodiments, the first edge step 115 and the second edge step 116 are symmetrically arranged. Specifically, the first edge step 115 and the second edge step 116 are designed to be symmetrical up and down. On the one hand, the same slotting parameters can be used to slot the first heat dissipation groove 113 and the second heat dissipation groove 114 in actual preparation, which simplifies the process. On the other hand, the symmetrical design can also make the heat dissipation capacity of the upper and lower parts of the base adapter plate 110 the same, thereby improving the heat dissipation uniformity.
在一些实施例中，第一散热凹槽113和第二散热凹槽114对应连通。具体地，第一散热凹槽113靠近第二表面112的一侧槽口和第二散热凹槽114靠近第一表面111的一侧槽口对应连通，从而使得第一表面111和第二表面112能够导通，在第一布线层120和第二布线层130分别覆盖第一散热凹槽113和第二散热凹槽114后，第一散热凹槽113和第二散热凹槽114能够共同形成空心结构，从而使得基底转接板110的中部和边缘均呈中空结构，一方面能够增大散热面积，方便进行散热，另一方面能够起到缓冲作用，减缓因内部热应力导致的翘曲现象。In some embodiments, the first heat dissipation groove 113 and the second heat dissipation groove 114 are connected to each other. Specifically, the notch on one side of the first heat dissipation groove 113 close to the second surface 112 and the notch on one side of the second heat dissipation groove 114 close to the first surface 111 are connected to each other, so that the first surface 111 and the second surface 112 can be connected, and after the first wiring layer 120 and the second wiring layer 130 cover the first heat dissipation groove 113 and the second heat dissipation groove 114 respectively, the first heat dissipation groove 113 and the second heat dissipation groove 114 can form a hollow structure together, so that the middle and the edge of the base adapter plate 110 are hollow structures, which can increase the heat dissipation area on the one hand and facilitate heat dissipation, and can play a buffering role on the other hand to reduce the warping phenomenon caused by internal thermal stress.
参见图3和图4，在一些实施例中，封装芯片160包括间隔设置在第一布线层120上的第一芯片161和第二芯片162，第一芯片161和第二芯片162之间的第一布线层120上设置有第一缺口122，第一缺口122与位于中部的第一散热凹槽113连通，第二布线层130上设置有第二缺口132，第二缺口132与位于中部的第二散热凹槽114连通。具体地，第一缺口122连通至第一表面111，第二缺口132连通至第二表面112，优选可以使得第一缺口122的宽度与第一散热凹槽113的最大宽度相同，同时第二缺口132的宽度与第二散热凹槽114的最大宽度相同。Referring to FIG. 3 and FIG. 4 , in some embodiments, the packaged chip 160 includes a first chip 161 and a second chip 162 arranged at intervals on the first wiring layer 120, a first notch 122 is arranged on the first wiring layer 120 between the first chip 161 and the second chip 162, the first notch 122 is connected to the first heat dissipation groove 113 located in the middle, and a second notch 132 is arranged on the second wiring layer 130, the second notch 132 is connected to the second heat dissipation groove 114 located in the middle. Specifically, the first notch 122 is connected to the first surface 111, and the second notch 132 is connected to the second surface 112, and preferably, the width of the first notch 122 can be the same as the maximum width of the first heat dissipation groove 113, and the width of the second notch 132 can be the same as the maximum width of the second heat dissipation groove 114.
进一步地，第一布线层120上还设置有第一填充胶层121，第一填充胶层121至少部分包覆于第一芯片161和第二芯片162，并至少部分填充至位于中部的第一散热凹槽113，第二布线层130外还设置有第二填充胶层131，第二填充胶层131包覆在第一焊球150外，用于接合至电路板，且第二填充胶层131填充至位于边缘的第一散热凹槽113和第二散热凹槽114，并部分填充至位于中部的第二散热凹槽114。具体地，第一填充胶层121通过第一缺口122进入到中部的第一散热凹槽113，第一填充胶层121能够将第一芯片161和第二芯片162的焊接结构包覆在内，从而起到保护作用，并且，第一填充胶层121进入第一散热凹槽113，能够大幅提升其与第一布线层120之间的结合力。第二填充胶层131用于包覆芯片封装结构100和PCB板200之间的焊球，从而在上板时起到固定焊球的作用，同时，第二填充胶层131还会通过第二缺口132进入位于中部的第二散热凹槽114，并与第一散热凹槽113中的第一填充胶层121接合，从而使得上下层的底部填充胶相互接合而提升其结合力，同时第二填充胶层131会填充在边缘的第一散热凹槽113和第二散热凹槽114中，进一步增强其结合力。Furthermore, a first filling glue layer 121 is also provided on the first wiring layer 120, and the first filling glue layer 121 at least partially covers the first chip 161 and the second chip 162, and at least partially fills the first heat dissipation groove 113 located in the middle. A second filling glue layer 131 is also provided outside the second wiring layer 130, and the second filling glue layer 131 covers the outside of the first solder ball 150, and is used to be bonded to the circuit board, and the second filling glue layer 131 fills the first heat dissipation groove 113 and the second heat dissipation groove 114 located at the edge, and partially fills the second heat dissipation groove 114 located in the middle. Specifically, the first filling glue layer 121 enters the first heat dissipation groove 113 in the middle through the first notch 122, and the first filling glue layer 121 can cover the soldering structure of the first chip 161 and the second chip 162 inside, so as to play a protective role, and the first filling glue layer 121 enters the first heat dissipation groove 113, which can greatly improve the bonding force between it and the first wiring layer 120. The second filling glue layer 131 is used to cover the solder balls between the chip packaging structure 100 and the PCB board 200, so as to fix the solder balls when the board is put on. At the same time, the second filling glue layer 131 will also enter the second heat dissipation groove 114 located in the middle through the second notch 132, and engage with the first filling glue layer 121 in the first heat dissipation groove 113, so that the bottom filling glue of the upper and lower layers is engaged with each other to enhance their bonding strength. At the same time, the second filling glue layer 131 will fill the first heat dissipation groove 113 and the second heat dissipation groove 114 at the edge to further enhance their bonding strength.
在一些实施例中，位于中部的第一散热凹槽113内的第一填充胶层121与位于中部的第二散热凹槽114内的第二填充胶层131相接，且第二填充胶层131相对于第二表面112的高度大于第一填充胶层121相对于第一表面111的高度。In some embodiments, the first filling glue layer 121 in the first heat dissipation groove 113 located in the middle is connected to the second filling glue layer 131 in the second heat dissipation groove 114 located in the middle, and the height of the second filling glue layer 131 relative to the second surface 112 is greater than the height of the first filling glue layer 121 relative to the first surface 111.
需要说明的是，通过设置第一缺口122和第二缺口132，能够使得第一填充胶层121和第二填充胶层131能够相互接合提升胶体的结合性，并防止基底转接板110受应力影响导致胶体与基底转接板110分层。同时第一散热凹槽113和第二散热凹槽114中的胶层相互接合，能够减少基底转接板110的应力，避免第一芯片161与第二芯片162之间受到基底转接板110的应力作用而影响芯片的焊接结构的稳定性，保证了第一芯片161和第二芯片162的导电性能。It should be noted that, by providing the first notch 122 and the second notch 132, the first filling glue layer 121 and the second filling glue layer 131 can be bonded to each other to improve the bonding of the glue, and prevent the base adapter plate 110 from being affected by stress, resulting in delamination of the glue and the base adapter plate 110. At the same time, the glue layers in the first heat dissipation groove 113 and the second heat dissipation groove 114 are bonded to each other, which can reduce the stress of the base adapter plate 110, avoid the first chip 161 and the second chip 162 being affected by the stress of the base adapter plate 110 and affecting the stability of the chip welding structure, and ensure the conductive performance of the first chip 161 and the second chip 162.
参见图5，在一些实施例中，第一散热凹槽113的深度和第二散热凹槽114的深度均小于基底转接板110的厚度的一半，以使第一散热凹槽113和第二散热凹槽114相互隔离。具体地，第一散热凹槽113和第二散热凹槽114相互间隔，且并不相互连通，能够避免贯穿基底转接板110而影响其结构强度。且第一散热凹槽113和第二散热凹槽114形成对称凹槽，能够平衡基底转接板110两侧的应力，避免布线结构与基底转接板110分层或胶层与基底转接板110分层。Referring to FIG. 5 , in some embodiments, the depth of the first heat dissipation groove 113 and the depth of the second heat dissipation groove 114 are both less than half the thickness of the base adapter plate 110, so that the first heat dissipation groove 113 and the second heat dissipation groove 114 are isolated from each other. Specifically, the first heat dissipation groove 113 and the second heat dissipation groove 114 are spaced apart from each other and are not connected to each other, which can avoid penetrating the base adapter plate 110 and affecting its structural strength. Moreover, the first heat dissipation groove 113 and the second heat dissipation groove 114 form symmetrical grooves, which can balance the stress on both sides of the base adapter plate 110 and avoid delamination of the wiring structure and the base adapter plate 110 or delamination of the adhesive layer and the base adapter plate 110.
参见图6，在一些实施例中，基底转接板110内还设置有散热层117，散热层117位于第一散热凹槽113和第二散热凹槽114之间，且散热层117靠近第一表面111的一侧被配置为第一散热凹槽113的底壁，散热层117靠近第二表面112的一侧被配置为第二散热凹槽114的底壁。具体地，在实际制备时，可以在形成第一散热凹槽113后，在底壁沉积或填充形成散热层117，散热层117可以是石墨烯/高导热环氧树脂/高分子聚合物/金属等，利用其高导热性能，实现高导热，提升散热效果的同时，解决分层问题。Referring to FIG. 6 , in some embodiments, a heat dissipation layer 117 is further provided in the base adapter plate 110. The heat dissipation layer 117 is located between the first heat dissipation groove 113 and the second heat dissipation groove 114, and the side of the heat dissipation layer 117 close to the first surface 111 is configured as the bottom wall of the first heat dissipation groove 113, and the side of the heat dissipation layer 117 close to the second surface 112 is configured as the bottom wall of the second heat dissipation groove 114. Specifically, in actual preparation, after forming the first heat dissipation groove 113, the heat dissipation layer 117 can be deposited or filled on the bottom wall to form the heat dissipation layer 117. The heat dissipation layer 117 can be graphene/high thermal conductivity epoxy resin/high molecular polymer/metal, etc., and its high thermal conductivity is used to achieve high thermal conductivity, improve the heat dissipation effect, and solve the stratification problem.
参见图7，在一些实施例中，封装芯片160背离基底转接板110的一侧还设置有堆叠转接板170，堆叠转接板170具有第三表面和第四表面，第三表面设置有朝向第四表面的第三散热凹槽，第四表面设置有朝向第三表面并与第三散热凹槽对应的第四散热凹槽，第三表面设置有第三布线层171，第四表面设置有第四布线层172，第三布线层171远离堆叠转接板170的一侧设置有堆叠芯片180，堆叠芯片180与封装芯片160相贴合，第三布线层171上还设置有第二焊球173，第二焊球173与第一布线层120连接。具体地，堆叠转接板170的构造与基底转接板110相同，堆叠芯片180与封装芯片160背对背利用胶层贴装，第二焊球173位于堆叠转接板170的边缘位置，可以是单颗焊球，也可以是两颗焊球焊接形成。Referring to FIG. 7 , in some embodiments, a stacking adapter board 170 is further provided on the side of the packaged chip 160 away from the base adapter board 110. The stacking adapter board 170 has a third surface and a fourth surface. The third surface is provided with a third heat dissipation groove facing the fourth surface. The fourth surface is provided with a fourth heat dissipation groove facing the third surface and corresponding to the third heat dissipation groove. The third surface is provided with a third wiring layer 171. The fourth surface is provided with a fourth wiring layer 172. A stacking chip 180 is provided on the side of the third wiring layer 171 away from the stacking adapter board 170. The stacking chip 180 is attached to the packaged chip 160. A second solder ball 173 is further provided on the third wiring layer 171. The second solder ball 173 is connected to the first wiring layer 120. Specifically, the structure of the stacking adapter board 170 is the same as that of the base adapter board 110. The stacking chip 180 and the packaged chip 160 are mounted back to back using a glue layer. The second solder ball 173 is located at the edge of the stacking adapter board 170 and may be a single solder ball or may be formed by welding two solder balls.
值得注意的是，在实际上板时，堆叠构造的芯片封装结构100需要通过第二填充胶层131来实现与PCB板200的固定，其中第二胶层可以侧爬至堆叠转接板170的侧壁，从而将第一焊球150和第二焊球173同时包覆在内，起到充分的保护作用。It is worth noting that when the board is actually mounted, the stacked chip packaging structure 100 needs to be fixed to the PCB board 200 through the second filling glue layer 131, wherein the second glue layer can crawl sideways to the side wall of the stacking adapter board 170, thereby covering the first solder ball 150 and the second solder ball 173 at the same time, thereby providing sufficient protection.
本发明实施例还提供了一种芯片封装结构100的制备方法，用于制备前述的芯片封装结构100，该制备方法包括以下步骤：The embodiment of the present invention further provides a method for preparing a chip packaging structure 100, which is used to prepare the aforementioned chip packaging structure 100. The method comprises the following steps:
S1：在基底转接板110的第一表面111刻蚀开孔后电镀形成导电柱140。S1: etching holes on the first surface 111 of the base transfer plate 110 and then electroplating to form conductive pillars 140 .
参见图8，具体地，首先取一基底转接板110，该基底转接板110可以采用玻璃材料、陶瓷材料、硅基底、锗基底、砷化镓、环氧树脂等高分子有机化合物等材料，也可以采用PCB板200、 引线框或玻纤布基板，优选为玻璃材料和硅基底。然后在基底转接板110上通过干法刻蚀方式、化学刻蚀方式或激光开槽方式在基底转接板110的第一表面111开槽形成盲孔，然后电镀形成导电柱140。Referring to FIG8 , specifically, firstly, a substrate adapter plate 110 is taken, and the substrate adapter plate 110 can be made of glass material, ceramic material, silicon substrate, germanium substrate, gallium arsenide, epoxy resin and other high molecular organic compounds, or a PCB board 200, a lead frame or a glass fiber cloth substrate, preferably a glass material and a silicon substrate. Then, a blind hole is formed on the first surface 111 of the substrate adapter plate 110 by dry etching, chemical etching or laser grooving, and then the conductive column 140 is formed by electroplating.
在实际开槽时，需要在底部预留一定厚度H，即开槽并未贯穿基底转接板110，降低蚀刻难度，同时也减少电镀填充时孔内出现的气泡问题。例如，此处基底转接板110的厚度为600-800mm，开孔深度可以是100-300mm，开孔深度即厚度减薄后的基底转接板110的厚度，通过控制开孔深度，能够控制后续基底转接板110的厚度。When actually grooving, a certain thickness H needs to be reserved at the bottom, that is, the grooving does not penetrate the substrate adapter plate 110, which reduces the difficulty of etching and also reduces the problem of bubbles in the hole during electroplating filling. For example, the thickness of the substrate adapter plate 110 here is 600-800mm, and the hole depth can be 100-300mm. The hole depth is the thickness of the substrate adapter plate 110 after the thickness is reduced. By controlling the hole depth, the thickness of the subsequent substrate adapter plate 110 can be controlled.
S2：在第一表面111刻蚀形成第一散热凹槽113。S2: etching the first surface 111 to form a first heat dissipation groove 113 .
参见图9，具体地，利用干法刻蚀方式、化学刻蚀方式或激光开槽方式在第一表面111多次开槽形成第一散热凹槽113，第一散热凹槽113采用回字形套接构造，多次开槽的宽度逐渐减小，从而形成台阶状的第一边沿台阶115，并使得第一散热凹槽113的宽度随着开槽进程逐渐减小。Referring to FIG9 , specifically, the first heat dissipation groove 113 is formed by multiple grooves on the first surface 111 by dry etching, chemical etching or laser grooving. The first heat dissipation groove 113 adopts a U-shaped socket structure, and the width of the multiple grooves gradually decreases, thereby forming a step-shaped first edge step 115, and the width of the first heat dissipation groove 113 gradually decreases with the grooving process.
S3：在第一表面111形成覆盖第一散热凹槽113，并与导电柱140连接的第一布线层120。S3 : forming a first wiring layer 120 on the first surface 111 , covering the first heat dissipation groove 113 and connected to the conductive pillar 140 .
参见图10，具体地，利用覆膜工艺，在第一表面111形成一层第一介质层，该介质材料可以是氮化硅、氮氧化硅、聚酰亚胺、苯并环丁烯等，然后再次将掩膜覆盖在介质层上，利用曝光显影工序形成图形层开口，再利用电镀工艺，在其图形层开口上形成电镀金属层形成布线结构，再次利用旋转涂敷工艺在第一介质层上形成第二介质层，再次利用干法刻蚀工艺在第二介质层上形成开孔露出底部布线结构，再次利用电镀工艺，在其孔上形成导电金属柱以及金属柱表面形成金属层（其材料可以为TI/TI/WU、NI等）通过金属层提升其锡球焊接性，完成第一布线层120的制备。Referring to FIG. 10 , specifically, a first dielectric layer is formed on the first surface 111 by a coating process. The dielectric material may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc., and then a mask is covered on the dielectric layer again. An exposure and development process is used to form a graphic layer opening. An electroplating process is used to form an electroplated metal layer on the graphic layer opening to form a wiring structure. A spin coating process is used to form a second dielectric layer on the first dielectric layer. A dry etching process is used to form an opening on the second dielectric layer to expose the bottom wiring structure. An electroplating process is used to form a conductive metal column on the hole and a metal layer (the material of which may be TI/TI/WU, NI, etc.) is formed on the surface of the metal column. The metal layer improves the solderability of the solder ball, and the preparation of the first wiring layer 120 is completed.
S4：在第一布线层120远离第一表面111的一侧贴设载具300。S4 : placing the carrier 300 on a side of the first wiring layer 120 away from the first surface 111 .
参见图11，具体地，取一载具300，并在载具300上涂覆UV胶层，载具300可以是玻璃、氧化硅、金属等材料，然后将基底转接板110具有第一布线层120的一侧贴装在该载具300上，进行烘烤，实现粘接固定。Referring to FIG. 11 , specifically, a carrier 300 is taken and a UV adhesive layer is coated on the carrier 300 . The carrier 300 may be made of glass, silicon oxide, metal or other materials. Then, the side of the base adapter plate 110 having the first wiring layer 120 is mounted on the carrier 300 and baked to achieve bonding and fixing.
S5：研磨基底转接板110远离第一表面111的一侧，以形成第二表面112并露出导电柱140。S5 : grinding a side of the substrate transfer plate 110 away from the first surface 111 to form a second surface 112 and expose the conductive pillars 140 .
参见图12，具体地，翻转载具300，将基底转接板110远离第一表面111的一侧朝上，并通过研磨工艺，将基底转接板110减薄，以导电柱140为研磨停止层，从而露出导电柱140的表面，并形成第二表面112。12 , specifically, the carrier 300 is flipped over, with the side of the substrate adapter plate 110 away from the first surface 111 facing upward, and the substrate adapter plate 110 is thinned through a grinding process, with the conductive column 140 as a grinding stop layer, thereby exposing the surface of the conductive column 140 and forming the second surface 112.
S6：在第二表面112刻蚀形成第二散热凹槽114。S6 : etching the second surface 112 to form a second heat dissipation groove 114 .
参见图13，具体地，在第二表面112重复第一散热凹槽113的制备过程，从而在第二表面112刻蚀形成第二散热凹槽114。需要说明的是，可以通过刻蚀深度的控制，能够使得第一散热凹槽113和第二散热凹槽114连通或者不连通，优选可以使得第一散热凹槽113和第二散热凹槽114连通。13, specifically, the preparation process of the first heat dissipation groove 113 is repeated on the second surface 112, so as to form the second heat dissipation groove 114 by etching the second surface 112. It should be noted that the first heat dissipation groove 113 and the second heat dissipation groove 114 can be connected or disconnected by controlling the etching depth, and preferably the first heat dissipation groove 113 and the second heat dissipation groove 114 can be connected.
S7：在第二表面112形成覆盖第二散热凹槽114，并与导电柱140连接的第二布线层130。S7 : forming a second wiring layer 130 on the second surface 112 , covering the second heat dissipation groove 114 and connected to the conductive pillar 140 .
参见图14，具体地，在完成第二散热凹槽114的制备后，再次通过覆膜工艺，在第二表面112形成第二布线层130，其中第二布线层130的制备过程可以参考第一布线层120的制备过程。14 , specifically, after the preparation of the second heat dissipation groove 114 is completed, a second wiring layer 130 is formed on the second surface 112 through a lamination process again, wherein the preparation process of the second wiring layer 130 may refer to the preparation process of the first wiring layer 120 .
值得注意的是，本实施例中第一布线层120和第二布线层130的制备过程中，均是利用曝光、显影工艺在介质层上实现图案化。在本发明其他较佳的实施例中，布线时也可以采用LDI（laser direct imaging，激光直接成像技术）来实现线路层的图案化。具体地，图案化是部分去除部分介质层材料的基本操作，从而为后续形成结构提供图案或电镀模板，例如图案化重分布层(RDL)、凸块下金属化(UBM)、铜柱等、垂直互连或其他所需的结构。在本实施例中，可以使用光刻、光掩模、掩模、氧化物或金属去除、照相和模板印刷以及微光刻来实现图案化。光刻包括通过激光直接成像(也称为直写或无掩模数字光刻)或在光掩模的掩模版中形成图案，并将图案转移到介质层的表面层中。It is worth noting that in the preparation process of the first wiring layer 120 and the second wiring layer 130 in this embodiment, patterning is achieved on the dielectric layer by using exposure and development processes. In other preferred embodiments of the present invention, LDI (laser direct imaging) can also be used to achieve patterning of the circuit layer during wiring. Specifically, patterning is a basic operation of partially removing part of the dielectric layer material, thereby providing a pattern or electroplating template for the subsequent formation of structures, such as patterned redistribution layer (RDL), under bump metallization (UBM), copper pillars, etc., vertical interconnection or other required structures. In this embodiment, patterning can be achieved using photolithography, photomasks, masks, oxide or metal removal, photography and template printing, and microlithography. Lithography includes forming a pattern by laser direct imaging (also known as direct writing or maskless digital lithography) or in a mask of a photomask, and transferring the pattern to the surface layer of the dielectric layer.
S8：去除载具300。S8: Remove the carrier 300.
参见图15，具体地，通过解键合的方式，将载具300去除，从而露出第一布线层120。Referring to FIG. 15 , specifically, the carrier 300 is removed by debonding, thereby exposing the first wiring layer 120 .
S9：在第一布线层120贴设封装芯片160。S9 : attaching the packaged chip 160 to the first wiring layer 120 .
参见图16，具体地，可以通过芯片贴装工艺，在第一布线层120上贴装封装芯片160，封装芯片160可以倒装贴设在第一布线层120上，并通过回流焊接于第一布线层120，然后在底部填充第一填充胶层121，利用第一填充胶层121保护焊接结构。Referring to FIG. 16 , specifically, the packaged chip 160 can be mounted on the first wiring layer 120 through a chip mounting process, the packaged chip 160 can be flip-chip mounted on the first wiring layer 120, and reflow soldered to the first wiring layer 120, and then filled with a first filling glue layer 121 at the bottom, and the first filling glue layer 121 is used to protect the welding structure.
S10：在第二布线层130形成第一焊球150。S10 : forming a first solder ball 150 on the second wiring layer 130 .
参见图17，具体地，可以利用印刷或电镀方式，在第二布线层130的表面形成锡层，然后通过回流工艺形成第一焊球150，最后通过切割工艺，将晶圆切割为单颗产品，完成制程。17 , specifically, a tin layer can be formed on the surface of the second wiring layer 130 by printing or electroplating, and then a first solder ball 150 is formed by a reflow process, and finally the wafer is cut into single products by a cutting process to complete the process.
综上所述，本发明实施例提供的芯片封装结构100和芯片封装结构100的制备方法，在基底转接板110的第一表面111设置第一散热凹槽113，在基底转接板110的第二表面112设置第二散热凹槽114，第一散热凹槽113和第二散热凹槽114对应，第一布线层120和第二布线层130分别分布在第一表面111和第二表面112，并分别覆盖第一散热凹槽113和第二散热凹槽114，而基底转接板110中还设只有连接第一布线层120和第二布线层130的导电柱140。相较于现有技术，本发明实施例通过增设第一散热凹槽113和第二散热凹槽114，位于中部的第一散热凹槽113和第二散热凹槽114能够在覆盖布线结构后形成内部空心结构，从而大幅提升散热效果，而位于边缘的第一散热凹槽113和第二散热凹槽114则可以在上板时增大与底部填充胶的接触面积，提升上板的结合力。In summary, the chip packaging structure 100 and the preparation method of the chip packaging structure 100 provided in the embodiments of the present invention are provided with a first heat dissipation groove 113 on the first surface 111 of the base adapter plate 110, and a second heat dissipation groove 114 on the second surface 112 of the base adapter plate 110, the first heat dissipation groove 113 and the second heat dissipation groove 114 correspond to each other, the first wiring layer 120 and the second wiring layer 130 are respectively distributed on the first surface 111 and the second surface 112, and respectively cover the first heat dissipation groove 113 and the second heat dissipation groove 114, and the base adapter plate 110 is also provided with a conductive column 140 which only connects the first wiring layer 120 and the second wiring layer 130. Compared with the prior art, the embodiment of the present invention adds a first heat dissipation groove 113 and a second heat dissipation groove 114. The first heat dissipation groove 113 and the second heat dissipation groove 114 located in the middle can form an internal hollow structure after covering the wiring structure, thereby greatly improving the heat dissipation effect. The first heat dissipation groove 113 and the second heat dissipation groove 114 located at the edge can increase the contact area with the bottom filling glue when the board is mounted, thereby improving the bonding force of the board.
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
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| US6507118B1 (en) * | 2000-07-14 | 2003-01-14 | 3M Innovative Properties Company | Multi-metal layer circuit |
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| JP5395412B2 (en) * | 2008-11-25 | 2014-01-22 | パナソニック株式会社 | Interposer |
| WO2019146039A1 (en) * | 2018-01-25 | 2019-08-01 | ソフトバンク株式会社 | Coolant-based cooling system for three-dimensional stacked integrated circuit, and three-dimensional stacked integrated circuit using same |
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