CN118502792A - Electronic product and memory firmware updating method thereof - Google Patents
Electronic product and memory firmware updating method thereof Download PDFInfo
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- CN118502792A CN118502792A CN202410962519.1A CN202410962519A CN118502792A CN 118502792 A CN118502792 A CN 118502792A CN 202410962519 A CN202410962519 A CN 202410962519A CN 118502792 A CN118502792 A CN 118502792A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000004891 communication Methods 0.000 claims abstract description 71
- 238000012545 processing Methods 0.000 claims abstract description 38
- 230000005540 biological transmission Effects 0.000 claims abstract description 34
- 238000000354 decomposition reaction Methods 0.000 claims description 22
- 230000009471 action Effects 0.000 claims description 18
- 230000008569 process Effects 0.000 claims description 13
- 230000003139 buffering effect Effects 0.000 claims description 10
- 230000002159 abnormal effect Effects 0.000 description 10
- 238000012423 maintenance Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- 125000004122 cyclic group Chemical group 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/45—Management operations performed by the client for facilitating the reception of or the interaction with the content or administrating data related to the end-user or to the client device itself, e.g. learning user preferences for recommending movies, resolving scheduling conflicts
- H04N21/458—Scheduling content for creating a personalised stream, e.g. by combining a locally stored advertisement with an incoming stream; Updating operations, e.g. for OS modules ; time-related management operations
- H04N21/4586—Content update operation triggered locally, e.g. by comparing the version of software modules in a DVB carousel to the version stored locally
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
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Abstract
The invention provides an electronic product and a memory firmware updating method thereof, comprising the following steps: the data transmission interface is in communication connection with the host end and is used for receiving the firmware update data packet burnt by the host end; the central controller is in communication connection with the data transmission interface through a serial communication protocol, and is in communication connection with the memory for carrying out power-on processing on the memory; the memory is in communication connection with the data transmission interface through a serial communication protocol and comprises a main control module and a flash memory module, wherein the main control module is internally provided with the serial communication interface and an analysis sub-module; the serial communication interface is used for receiving the firmware update data packet and sending the firmware update data packet to the analysis submodule; the analysis sub-module is used for processing the firmware update data packet to generate analysis data; the analysis sub-module is also used for updating the firmware in the flash memory module according to the analysis data. The invention can improve the firmware updating efficiency of the memory in the electronic product.
Description
Technical Field
The present invention relates to the field of electronic storage technologies, and in particular, to an electronic product and a method for updating firmware in a memory of the electronic product.
Background
Embedded memory (Embedded Multi MEDIA CARD, EMMC) and universal flash memory (Universal Flash Storage, UFS) are widely used in electronic products such as televisions, set-top boxes, tablet computers, mobile phones, and the like. eMMC is composed of an ARM CPU as a controller plus a flash block (NAND FLASH), where the ARM CPU runs controller software, commonly referred to as Firmware.
On the premise of the online upgrading technology of the eMMC of the electronic product, the electronic product can normally operate without data damage, however, in the actual repair process of a customer, the electronic product cannot be started, namely a central controller in the electronic product cannot be normally started and controlled, and a memory in the electronic product usually has the problem of locking cards. When the memory has the problem of locking, the forced updating of the memory firmware cannot be realized through the interface of the electronic product, the existing method for solving the problem of locking the memory can only replace the storage particles in the memory, so that the maintenance cost of the electronic product is increased, the maintenance period is longer, and the user experience is seriously reduced. Therefore, there is a need for improvement.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an electronic product and a method for updating firmware of a memory thereof, which improves the firmware updating efficiency of the memory in the electronic product.
In order to solve the technical problems, the invention is realized by the following technical scheme:
The invention provides an electronic product, comprising:
The data transmission interface is in communication connection with the host end and is used for receiving the firmware update data packet burnt by the host end;
The central controller is in communication connection with the data transmission interface through a serial communication protocol, and is in communication connection with the memory for carrying out power-on processing on the memory;
the memory is in communication connection with the data transmission interface through the serial communication protocol, the memory comprises a main control module and a flash memory module, and the main control module is internally provided with a serial communication interface and an analysis sub-module;
The serial communication interface is used for receiving the firmware update data packet and sending the firmware update data packet to the analysis submodule;
the analysis sub-module is used for processing the firmware update data packet to generate analysis data;
the analysis sub-module is also used for updating the firmware in the flash memory module according to the analysis data.
In an embodiment of the present invention, the parsing sub-module includes a data decomposition unit, where the data decomposition unit determines that, when the firmware update packet is received, the actions performed are:
and carrying out logic analysis processing on the firmware updating data packet to generate corresponding analysis data, wherein the analysis data comprises a starting address, a device address, a logic block address, a data length and updating data.
In an embodiment of the present invention, the parsing sub-module further includes a register unit and a buffer unit, and the data decomposition unit is further configured to perform the following actions when determining that the device address is the same as a preset write address:
And storing the logical block address and the data length into the corresponding register units respectively, and writing the updated data into the buffer units.
In an embodiment of the present invention, the parsing sub-module further includes a buffer enabling unit, and the data decomposing unit is further configured to determine whether the update data is completely written into the buffer unit;
If the updated data are all written into the buffer unit, generating a buffer ending instruction and sending the buffer ending instruction to the buffer enabling unit;
and if the updated data are not completely written into the buffer unit, continuing to perform buffer writing processing on the updated data, and repeating judgment until the updated data are completely written into the buffer unit.
In an embodiment of the present invention, the parsing sub-module further includes a read-write control unit, and when the buffering enabling unit determines that the buffering end instruction is received, the executing actions are: and performing potential switching processing on the read-write control unit according to the buffer ending instruction to generate a write-in potential signal.
In an embodiment of the present invention, when the read-write control unit determines that the write potential signal is generated, the action performed is: acquiring update data in the buffer unit according to the write-in potential signal;
Writing the updated data into the flash memory module, and acquiring writing reply information;
and uploading the write-in reply information to the host end through the serial communication interface.
The invention also provides a method for updating the memory firmware of the electronic product, which comprises the following steps:
powering up the memory;
the memory acquires a firmware update data packet;
the memory processes the firmware update data packet to generate analysis data;
and the memory updates the firmware in the flash memory module according to the analysis data.
In an embodiment of the present invention, the step of processing the firmware update data packet to generate the parsing data includes:
Performing logic analysis processing on the firmware update data packet to generate analysis data, wherein the analysis data comprises a starting address, a device address, a logic block address, a data length and update data;
based on the comparison result of the device address and the preset writing address, the logic block address and the data length are respectively stored in the corresponding register units, and the updated data are written into the buffer units.
In an embodiment of the present invention, the step of storing the logical block address and the data length in respective corresponding register units based on a comparison result between the device address and a preset write address, and writing the update data into a buffer unit includes:
Judging whether the device address is the same as a preset writing address;
If the device address is the same as the preset writing address, writing the logic block address into a logic block address register unit, writing the data length into a data length register unit, and writing the updated data into a buffer unit;
And if the device address is different from the preset write address, repeatedly acquiring a firmware update data packet, processing the firmware update data packet, acquiring analysis data, and repeatedly judging whether the device address in the analysis data is the same as the preset write address or not until the device address is the same as the preset write address.
In an embodiment of the present invention, the step of updating firmware in the flash memory module according to the parsing data includes:
Generating a buffering ending instruction based on a result of writing the update data into the buffer unit;
Performing potential switching processing on the read-write control unit according to the buffer ending instruction to generate a write-in potential signal;
And acquiring the update data in the buffer unit according to the write-in potential signal, and writing the update data into a flash memory module so as to update the firmware in the flash memory module.
As described above, the present invention provides an electronic product and a method for updating firmware of a memory thereof, which can realize forced updating of the firmware of the memory through an independent serial communication protocol when the electronic product cannot be started normally and the memory therein has a card locking problem, thereby effectively improving the firmware updating efficiency of the memory in the electronic product, reducing the maintenance cost and period of the electronic product and improving the user experience.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an electronic product according to the present invention;
FIG. 2 is a schematic view of the partial structure of FIG. 1;
FIG. 3 is a flowchart illustrating a method for updating memory firmware of an electronic product according to the present invention;
fig. 4 is a schematic flow chart of step S30 in fig. 3;
fig. 5 is a schematic flow chart of step S32 in fig. 4;
fig. 6 is a schematic flow chart of step S40 in fig. 3.
Description of element numbers:
10. An electronic product; 11. a data transmission interface; 12. a central controller;
13. a memory; 131. a main control module; 1311. a serial communication interface; 1312. a parsing sub-module; 1313. a flash memory input interface; 1314. a data decomposition unit; 1315. a read-write switching unit; 1316. a buffer unit; 1317. a read-write control unit; 1318. a buffer enabling unit; 132. a flash memory module;
14. A circuit board.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, the present invention provides an electronic product, which may have a data transmission interface (High-Definition Multimedia Interface, HDMI interface) to facilitate the forced update of the firmware of the internal memory thereof to clear the card lock of the memory, recover the brand new memory state, and improve the online upgrade efficiency of the memory in the electronic product.
Referring to fig. 1, in an embodiment of the present invention, the electronic product 10 may be a product with an internal memory that needs to be updated with firmware, and the type of the electronic product 10 may be various, as long as the electronic product 10 is provided with an HDMI interface. For example, the electronic product 10 may be a Television (TV) or a set top box (OTT). In addition, when the firmware of the memory in the electronic product 10 needs to be updated, at least one corresponding serial communication burner may be externally connected to the HDMI interface of the electronic product 10, and at least one host end may be externally connected to one end of the serial communication burner, so as to burn a corresponding firmware update data packet for the electronic product 10.
Further, when firmware update is required to be performed on the memories in the electronic products 10, a corresponding serial communication burner may be connected to the HDMI interface of each electronic product 10, and the serial communication burners may be connected to the same host end, so that firmware update on the memories in the electronic products 10 can be performed through one host end, and further firmware update efficiency of the memories in the electronic products 10 is improved.
Referring to fig. 1, in one embodiment of the present invention, an electronic product 10 may include, but is not limited to, a data transmission interface 11, a central controller 12, a memory 13, and a circuit board 14. The data transmission interface 11 may be an HDMI interface, and the data transmission interface 11 may be in communication connection with a host, for receiving a firmware update packet burned by the host. The HDMI interface is a widely used audio or video interface, allowing high definition video and digital audio to be transmitted over a single cable. The HDMI interface supports video transmission from standard definition to High Definition (HD), ultra high definition (4K), and even to 8K resolution, while supporting multiple audio formats, including stereo and multi-channel surround sound.
Referring to fig. 1, further, the HDMI interface may include a pair of serial communication pins Pin16 and Pin15, respectively, and the serial communication protocol (Inter-INTEGRATED CIRCUIT, I2C) between the host and the electronic product 10 may be supported by the pair of serial communication pins. Pin16 may be a serial data Pin (SERIAL DATA LINE, SDA) for bi-directional transfer of data, through which communication between the host side and the memory 13 within the electronic product 10 is required. Pin15 may be a serial clock Pin (Serial Clock Line, SCL) for providing a clock signal for data transfer, on which line the host side on the bus generates to synchronize data transfer for all devices on the bus. I2C is a serial communication protocol that allows multiple "slaves" (e.g., memory 13) to communicate with one or more "masters" (host-side) via two wires (SCL and SDA). Since the I2C protocol supports device addresses, a plurality of devices can be connected through a single I2C bus, and each device can be distinguished for instruction transmission and data transmission.
Referring to fig. 1, in an embodiment of the present invention, at least one serial communication burner may be configured to be communicatively connected to a data transmission interface 11 of an electronic product 10. The serial communication burner may have a burning interface capable of communicating with the data transmission interface 11 through a serial communication protocol at one end, and a data line capable of communicating with a data interface (Universal Serial Bus, USB) of the host end at the other end. Specifically, the SCL Pin in the writing interface of the serial communication writer may be connected to the Pin15 Pin in the data transmission interface 11 of the electronic product 10, and the SDA Pin in the writing interface of the serial communication writer may be connected to the Pin16 Pin in the data transmission interface 11 of the electronic product 10, so as to realize serial communication between the serial communication writer and the data transmission interface 11.
Referring to fig. 1, in an embodiment of the present invention, a host may be communicatively connected to a serial communication burner to supply power to an electronic product 10, and build a corresponding update environment according to a type of the electronic product 10 to select a corresponding firmware update data packet for burning.
Referring to fig. 1, in one embodiment of the present invention, the central controller 12 may be a System on Chip (SoC Chip), which is a device that integrates all or most of the components of a computer or other electronic System into a single Chip. SoC chips typically integrate a variety of functional modules including a Central Processing Unit (CPU), a Graphics Processor (GPU), a memory interface, an input/output interface, and a communication module (Wi-Fi, bluetooth), etc. A circuit board 14 (Printed Circuit Board, PCB) may be disposed between the central controller 12 and the data transmission interface 11, and serial communication protocol communication may be implemented between the central controller 12 and the data transmission interface 11 through the circuit board 14.
Referring to fig. 1, in an embodiment of the present invention, a circuit board 14 may be disposed between the memory 13 and the data transmission interface 11, and serial communication protocol communication may be implemented between the memory 13 and the data transmission interface 11 through the circuit board 14, so as to receive a firmware update data packet burned by a host through the data transmission interface 11, and perform firmware update processing according to the firmware update data packet. In addition, the central controller 12 is also in communication with the memory 13 to facilitate power-up processing and startup control of the memory 13.
Referring to fig. 1, specifically, an input terminal of a circuit board 14 between the memory 13 and the data transmission interface 11 may be connected to an output terminal of the circuit board 14 between the central controller 12 and the data transmission interface 11. That is, a circuit board 14 may be led out from the two serial communication pins Pin16 and Pin15 of the data transmission interface 11, and one end of the circuit board 14 may extend to the central controller 12, and the other end may extend to the memory 13, so as to realize independent communication between the host and the memory 13 when the central controller 12 cannot perform start control on the memory 13, thereby facilitating subsequent firmware update processing on the memory 13.
Referring to fig. 1, the eMMC memory is an embedded memory, and has a plurality of pins for power supply, data transmission, control signals, and the like. Some of these pins may be labeled as non-communication (NC) in a particular design, meaning that these pins are not assigned specific uses in standard eMMC functions and therefore are not connected under normal circumstances. Therefore, when the circuit board 14 extends onto the memory 13, the independent communication of the data transmission interface 11 with the memory 13 through the serial communication protocol can be achieved by respectively accessing the serial communication buses on the circuit board 14, which are connected to the two serial communication pins of the data transmission interface 11, into the NC pins of the eMMC memory.
Referring to fig. 1, the memory 13 may include, but is not limited to, a main control module 131 and a flash memory module 132. The main control module 131 is configured to process the firmware update data packet, and write the processed data into the flash memory module 132 to implement forced update of the firmware in the memory 13. The flash module 132 may be NAND FLASH, which uses NAND gates to complete the storage of data, meaning that data is retained even in the event of a power failure.
Referring to fig. 1 and 2, the main control module 131 may include, but is not limited to, a serial communication interface 1311, a parsing sub-module 1312, and a flash memory input interface 1313. Specifically, the serial communication interface 1311 may be an I2C interface, and the serial communication interface 1311 may communicate with the circuit board 14 through a serial communication protocol, to receive the firmware update data packet and send it to the parsing submodule 1312. The flash input interface 1313 may be a Nand interface, and the host module 131 is communicatively connected to the flash module 132 through the flash input interface 1313. The parsing sub-module 1312 may obtain the firmware update data packet from the serial communication interface 1311 and process it to generate parsing data. The parsing sub-module 1312 is further configured to write the parsing sub-module 1312 into the flash memory module 132 through the flash memory input interface 1313, so as to update the firmware in the flash memory module 132 according to the parsing data, thereby solving the problem of locking the card in the memory 13.
Referring to fig. 1 and 2, the parsing submodule 1312 may include, but is not limited to, a data decomposition unit 1314, a read/write switching unit 1315, a buffer unit 1316, a read/write control unit 1317, a buffer enabling unit 1318, and a register unit 1319. The data decomposition unit 1314 may communicate with the serial communication interface 1311 through a serial communication protocol, and when the data decomposition unit 1314 determines that the firmware update data packet is received, the action to be performed is to perform a logic parsing process on the firmware update data packet first to obtain corresponding parsed data. In particular, the resolved data may include, but is not limited to, a start address, a device address, a logical block address, a data length, and update data. For example, the parsed data may also include a cyclic redundancy check code (Cyclic Redundancy Check, CRC) and an end address.
Referring to fig. 1 and 2, the data decomposition unit 1314 is further configured to store the logical block address and the data length into the corresponding register unit 1319, and write the updated data into the buffer unit 1316 when the device address is determined to be the same as the predetermined write address. If the device address is different from the preset write address, repeatedly acquiring the firmware update data packet, processing the firmware update data packet to acquire the analysis data, and repeatedly judging whether the device address in the analysis data is the same as the preset write address until the device address is the same.
Referring to fig. 1 and 2, specifically, the data decomposition unit 1314 determining that the device address is the same as the preset write address means that the data decomposition unit 1314 determines whether the device address is the same as the preset write address. If the device address is the same as the preset write address, the data decomposition unit 1314 performs a write processing on the read-write switching unit 1315 to write the logical block address (Logical Block Addressing, LBA) into the logical block address register unit, and writes the data length into the corresponding data length register unit, so as to write the update data in the buffer unit 1316 into the flash memory module 132 according to the logical block address and the data length in the register unit 1319.
Referring to fig. 1 and 2, a buffer unit 1316 (Data buffer) is a temporary flash memory unit located in the memory 13 for buffering Data before the Data is sent to the flash memory module 132. The presence of the buffer unit 1316 can help cope with problems due to data transmission rate mismatch or processing speed difference, improving efficiency and stability of data processing.
Referring to fig. 1 and 2, in one embodiment of the present invention, for example, the length of the parsed data may be 8 bits, and each unit is 512 bytes (byte). In addition, the preset write address may be set to 0x56, and the data decomposition unit 1314 needs to determine whether the device address obtained after the logic analysis processing is 0x56, and if the device address is 0x56, the write/read switching unit 1315 will perform write processing to write the logical block address (Logical Block Addressing, LBA) into the logical block address register unit, and write the data length into the corresponding data length register unit. In addition, the read/write control unit 1317 is also configured to write update Data into the buffer unit 1316 (Data buffer), and to represent the update Data written into the buffer unit 1316 as update Data within the buffer unit 1316.
Referring to fig. 1 and 2, it should be further noted that the data decomposition unit 1314 is further configured to determine whether the updated data is completely written into the buffer unit 1316. If all the update data is written into the buffer unit 1316, a buffer end instruction is generated. If the update data is not completely written in the buffer unit 1316, the buffer writing process is continued for the update data, and the determination is repeated until the update data is completely written in the buffer unit 1316. Further, when the data decomposition unit 1314 determines to generate the buffering-end instruction, the action performed may be to send the buffering-end instruction to the buffering-enable unit 1318.
Referring to fig. 1 and 2, when the buffer enabling unit 1318 determines that the buffer end instruction is received, the action performed may be to perform a potential switching process on the read/write control unit 1317 according to the buffer end instruction, and generate a write potential signal. When the read-write control unit 1317 determines that the write-in potential signal is generated, the action is performed to obtain the update data in the buffer unit 1316 according to the write-in potential signal, and write the update data in the buffer unit 1316 into the flash memory module 132 to obtain the write-in reply information, and send the write-in reply information to the host through the serial communication interface 1311. The host side can generate a corresponding updating result based on the comparison of the written reply information and the preset reply information. Specifically, when the buffer enable unit 1318 determines that the buffer end instruction is received, the action performed may be to perform a potential pull-up process on the read-write control unit 1317 to generate a write potential signal.
Referring to fig. 1 and fig. 2, when the host determines that the write reply message is received, the action performed may be to generate an update result based on a comparison between the write reply message and the preset reply message. The preset reply information may include normal writing information and abnormal writing information, and the update result may include successful update and abnormal update. Specifically, the host side may determine whether the write reply information is the same as the normal write information/the abnormal write information. If the write-in reply information is the same as the normal write-in information, the update is successful, and the next firmware update data packet is continuously selected for burning until the firmware is completely updated. If the write-in reply information is the same as the abnormal write-in information, updating the abnormality, repeatedly selecting the corresponding firmware update data packet for burning, generating the firmware update data packet, and sending the firmware update data packet to the corresponding memory 13 for repeatedly carrying out firmware update processing until the acquired write-in reply information is the same as the normal write-in information.
Referring to fig. 1 and 2, for example, normal write information may be set to 0x00 and abnormal write information may be set to 0xFF. That is, when the write reply message is 0x00, it can be determined that the firmware update is successful, and the host side can continue to select the next firmware update data packet to burn until the firmware update is completed. When the write reply information is 0xFF, it can be determined that the firmware update is abnormal, the host side needs to repeatedly select the corresponding firmware update data packet to burn, generate the firmware update data packet, and send the firmware update data packet to the corresponding memory 13 to repeatedly perform the firmware update processing until the acquired write reply information is 0x00.
Referring to fig. 1 and 2, in another embodiment of the present invention, when the device address is different from the preset write address, it is further possible to continuously determine whether the device address is the same as the initial preset read address. If the device address is the same as the initial preset read address, the data decomposition unit 1314 may perform a read-setting process on the read-write switching unit 1315, write the logical block address (Logical Block Addressing, LBA) into the logical block address register unit, and write the data length into the corresponding data length register unit. In addition, the data decomposition unit 1314 may also control the buffer enabling unit 1318 to perform a potential switching process on the read-write control unit 1317 to generate a read potential signal. The read/write control unit 1317 may read the updated data from the flash memory module 132 into the logical block address register unit according to the read potential signal.
Referring to fig. 1 and 2, when the read/write control unit 1317 determines that the update data in the flash memory module 132 has been completely read into the logical block address register unit, the read/write control unit 1317 may generate and upload initial read reply information to the host side through the serial communication protocol. When the host determines that the initial read reply message is received, the action is to judge whether the initial read reply message is identical to the normal read message/the abnormal read message. If the initial read reply information is the same as the normal read information, the corresponding data read instruction packet is selected to be burned into the memory 13, and the data decomposition unit 1314 performs logic analysis processing on the data read instruction packet to generate the corresponding device address. If the initial read reply message is the same as the abnormal read reply message, the selected data packet is repeatedly burned into the memory 13, and logic analysis processing is performed on the selected data packet to obtain a corresponding device address, and the device address is repeatedly judged to be the same as the initial preset read address until the initial read reply message is the same as the normal read message.
Referring to fig. 1 and 2, further, the data decomposition unit 1314 may continue to determine whether the device address is the same as the target preset read address. If the device address is the same as the target preset read address, the data decomposition unit 1314 may perform a read-setting process on the read-write switching unit 1315 and control the buffer enabling unit 1318 to perform a potential switching process on the read-write control unit 1317 to generate a read potential signal. The read/write control unit 1317 may read the updated data in the logical block address register unit into the buffer unit 1316 according to the read potential signal.
Referring to fig. 1 and fig. 2, but not limited thereto, when the read/write control unit 1317 determines that the updated data in the logical block address register unit has been completely read into the buffer unit 1316, the performed actions generate the target read reply information, and upload it to the host side through the serial communication protocol. When the host determines that the target read reply information is received, the action is to judge whether the target read reply information is the same as the normal read information/the abnormal read information. If the target reading reply information is the same as the normal reading information, the reading is successful. If the target read reply information is the same as the abnormal read information, the read fails, the host side needs to repeatedly select the data read command packet corresponding to the selection and burn the data read command packet into the memory 13, and the data decomposition unit 1314 performs logic analysis processing on the data read command packet to generate a corresponding device address, and repeats the above steps until the generated target read reply information is the same as the normal read information.
Referring to fig. 1 and fig. 2, further, after the read-write control unit 1317 reads the updated data in the logical block address register unit to the buffer unit 1316 according to the read potential signal, the data decomposition unit 1314 is further configured to upload the updated data in the buffer unit 1316 to the host through the serial communication interface 1311, and when the host determines that the updated data is received, the host performs an action of parsing the updated data to obtain a corresponding verification result.
Referring to fig. 3, the present invention further provides a method for updating memory firmware of an electronic product, which can be applied to the above electronic product to update memory firmware of different electronic products. The updating method corresponds to the electronic products in the above embodiment one by one, and the updating method of the memory firmware may include the following steps:
and step S10, powering up the memory.
Step S20, the memory acquires a firmware update data packet.
And step S30, the memory processes the firmware update data packet to generate analysis data.
And S40, the memory updates the firmware in the flash memory module according to the analysis data.
Referring to fig. 4, in one embodiment of the present invention, when step S30 is performed, specifically, step S30 may include the following steps:
And S31, carrying out logic analysis processing on the firmware update data packet to generate analysis data, wherein the analysis data comprises a start address, a device address, a logic block address, a data length and update data.
Step S32, based on the comparison result of the device address and the preset writing address, the logic block address and the data length are respectively stored in the corresponding register units, and the updated data are written into the buffer units.
Referring to fig. 5, in one embodiment of the present invention, when step S32 is performed, specifically, step S32 may include the following steps:
step S321, judging whether the device address is the same as the preset writing address.
Step S322, if the device address is the same as the preset writing address, writing the logic block address into the logic block address register unit, writing the data length into the data length register unit, and writing the updated data into the buffer unit.
Step S323, if the device address is different from the preset writing address, repeatedly acquiring the firmware update data packet, processing the firmware update data packet to acquire analysis data, and repeatedly judging whether the device address in the analysis data is the same as the preset writing address or not until the device address is the same as the preset writing address.
Referring to fig. 6, in one embodiment of the present invention, when step S40 is performed, specifically, step S40 may include the following steps:
step S41, generating a buffering ending instruction based on the result of writing the updated data into the buffering unit.
Step S42, performing potential switching processing on the read-write control unit according to the buffer ending instruction to generate a write potential signal.
Step S43, the update data in the buffer unit is obtained according to the write-in potential signal, and the update data is written into the flash memory module to update the firmware in the flash memory module.
Therefore, in the scheme, when the electronic product cannot be started normally and the memory in the electronic product has the problem of locking, the firmware of the memory is forcedly updated through the independent serial communication protocol, so that the firmware updating efficiency of the memory in the electronic product can be effectively improved, the maintenance cost and period of the electronic product are reduced, and the user experience is improved.
In the description of the present specification, the descriptions of the terms "present embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. An electronic product, comprising:
The data transmission interface is in communication connection with the host end and is used for receiving the firmware update data packet burnt by the host end;
The central controller is in communication connection with the data transmission interface through a serial communication protocol, and is in communication connection with the memory for carrying out power-on processing on the memory;
the memory is in communication connection with the data transmission interface through the serial communication protocol, the memory comprises a main control module and a flash memory module, and the main control module is internally provided with a serial communication interface and an analysis sub-module;
The serial communication interface is used for receiving the firmware update data packet and sending the firmware update data packet to the analysis submodule;
the analysis sub-module is used for processing the firmware update data packet to generate analysis data;
the analysis sub-module is also used for updating the firmware in the flash memory module according to the analysis data.
2. The electronic product of claim 1, wherein the parsing sub-module includes a data decomposition unit that performs the following actions when determining that the firmware update packet is received:
and carrying out logic analysis processing on the firmware updating data packet to generate corresponding analysis data, wherein the analysis data comprises a starting address, a device address, a logic block address, a data length and updating data.
3. The electronic product of claim 2, wherein the parsing sub-module further comprises a registering unit and a buffering unit, and the data decomposing unit is further configured to perform the following actions when determining that the device address is the same as a preset write address:
And storing the logical block address and the data length into the corresponding register units respectively, and writing the updated data into the buffer units.
4. The electronic product of claim 3, wherein the parsing sub-module further comprises a buffer enabling unit, and the data decomposing unit is further configured to determine whether the updated data is completely written into the buffer unit;
If the updated data are all written into the buffer unit, generating a buffer ending instruction and sending the buffer ending instruction to the buffer enabling unit;
and if the updated data are not completely written into the buffer unit, continuing to perform buffer writing processing on the updated data, and repeating judgment until the updated data are completely written into the buffer unit.
5. The electronic product of claim 4, wherein the parsing sub-module further comprises a read-write control unit, and the buffering enabling unit determines that the buffering ending instruction is received, and performs the following actions: and performing potential switching processing on the read-write control unit according to the buffer ending instruction to generate a write-in potential signal.
6. The electronic product according to claim 5, wherein the read-write control unit determines that the write potential signal is generated by performing the actions of: acquiring update data in the buffer unit according to the write-in potential signal;
writing the updated data into a flash memory module, and acquiring writing reply information;
and uploading the write-in reply information to a host end through a serial communication interface.
7. A method for updating memory firmware of an electronic product, comprising:
powering up the memory;
the memory acquires a firmware update data packet;
the memory processes the firmware update data packet to generate analysis data;
and the memory updates the firmware in the flash memory module according to the analysis data.
8. The method for updating memory firmware of an electronic product according to claim 7, wherein the step of processing the firmware update packet to generate the parsed data includes:
Performing logic analysis processing on the firmware update data packet to generate analysis data, wherein the analysis data comprises a starting address, a device address, a logic block address, a data length and update data;
based on the comparison result of the device address and the preset writing address, the logic block address and the data length are respectively stored in the corresponding register units, and the updated data are written into the buffer units.
9. The method for updating memory firmware of an electronic product according to claim 8, wherein the step of storing the logical block address and the data length in respective corresponding register units based on a comparison result of the device address and a preset write address, and writing the update data into a buffer unit comprises:
Judging whether the device address is the same as a preset writing address;
If the device address is the same as the preset writing address, writing the logic block address into a logic block address register unit, writing the data length into a data length register unit, and writing the updated data into a buffer unit;
And if the device address is different from the preset write address, repeatedly acquiring a firmware update data packet, processing the firmware update data packet, acquiring analysis data, and repeatedly judging whether the device address in the analysis data is the same as the preset write address or not until the device address is the same as the preset write address.
10. The method for updating memory firmware of an electronic product according to claim 7, wherein the step of updating firmware in the flash memory module according to the parsing data comprises:
Generating a buffering ending instruction based on a result of writing the update data into the buffer unit;
Performing potential switching processing on the read-write control unit according to the buffer ending instruction to generate a write-in potential signal;
And acquiring the update data in the buffer unit according to the write-in potential signal, and writing the update data into a flash memory module so as to update the firmware in the flash memory module.
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