CN118473390B - A power-on reset circuit and method - Google Patents
A power-on reset circuit and method Download PDFInfo
- Publication number
- CN118473390B CN118473390B CN202410633048.XA CN202410633048A CN118473390B CN 118473390 B CN118473390 B CN 118473390B CN 202410633048 A CN202410633048 A CN 202410633048A CN 118473390 B CN118473390 B CN 118473390B
- Authority
- CN
- China
- Prior art keywords
- voltage
- nmos tube
- electrically connected
- power
- dividing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electronic Switches (AREA)
Abstract
本发明涉及复位电路技术领域，具体公开一种上电复位电路及方法，该电路包括：分压器，包括分压MOS管和分压电阻，设置有分压输出点，用于产生触发分压并调整上电复位电路的功耗；迟滞器，包括迟滞MOS管，与分压输出点电连接，用于避免因电源电压抖动造成的复位电压抖动；比较器，输入端与分压输出点电连接，输出端与迟滞器的输入端电连接，用于将触发分压转换为逻辑信号；缓冲器，输入端与比较器输出端电连接，输出端作为上电复位电路的输出端，用于增加上电复位电路的驱动能力。本发明触发点精准，对工艺角和温度变化不敏感，触发点随工艺角、温度、电源电压变化范围在+/‑100mV之内，且不随电源电压上升而上升，面积小、成本低。
The present invention relates to the field of reset circuit technology, and specifically discloses a power-on reset circuit and method, the circuit comprising: a voltage divider, including a voltage-dividing MOS tube and a voltage-dividing resistor, provided with a voltage-dividing output point, used to generate a trigger voltage division and adjust the power consumption of the power-on reset circuit; a hysteresis device, including a hysteresis MOS tube, electrically connected to the voltage-dividing output point, used to avoid reset voltage jitter caused by power supply voltage jitter; a comparator, the input end of which is electrically connected to the voltage-dividing output point, and the output end of which is electrically connected to the input end of the hysteresis device, used to convert the trigger voltage division into a logic signal; a buffer, the input end of which is electrically connected to the output end of the comparator, and the output end is used as the output end of the power-on reset circuit, used to increase the driving capability of the power-on reset circuit. The present invention has a precise trigger point, is insensitive to process angle and temperature changes, the trigger point changes with process angle, temperature, and power supply voltage within +/-100mV, and does not rise with the increase of power supply voltage, has a small area, and is low in cost.
Description
Technical Field
The invention relates to the technical field of reset circuits, in particular to a power-on reset circuit and a method.
Background
The power-on reset provides an indication to start working after the chip is powered on. The power-on reset circuit generally generates a reset signal by utilizing different node changes in the power-on process. When the memory cell IP is integrated in a high-precision product or on a chip, a relatively accurate power-on reset point is required. Therefore, the minimum power supply voltage requirement of the storage unit IP can be ensured, and the influence on the normal operation of other analog circuits due to the fact that the power supply voltage is too low can be avoided. In addition, portable device applications often have stringent requirements for the overall power consumption of the chip, and designing a power-on reset circuit with very low power consumption will be unavoidable. While very low power circuits tend to mean a larger area, this will greatly increase the cost of the chip, thereby reducing the competitiveness of the chip.
A circuit structure of the existing power-on reset circuit is shown in fig. 1, and the power-on reset circuit has the following defects that 1, a large area, a voltage divider is connected in series by a PMOS tube and an NMOS tube to realize the communication between a power supply and the ground, the PMOS tube and the NMOS tube L/W of the voltage divider are required to be made large for realizing low power consumption, 2, a trigger point is highly dependent on threshold voltages of the PMOS tube and the NMOS tube and is sensitive to temperature and process angles, and 3, the power consumption is highly dependent on power supply voltage. And the power consumption is high under high power supply voltage.
The other circuit structure of the existing power-on reset circuit is shown in fig. 2, and the power-on reset circuit has the advantages of simpler structure, and has the following defects that 1, the power-on reset circuit is large in area, the voltage divider is connected with the ground through a PMOS tube, an NMOS tube and a resistor in series, the L/W of the PMOS tube and the NMOS tube of the voltage divider is large for realizing low power consumption, 2, the trigger point is highly dependent on threshold voltages of the PMOS tube and the NMOS tube and the resistor is sensitive to temperature and process angle, 3, the power consumption is highly dependent on the power supply voltage, and the power consumption is large under the high power supply voltage, and the error is about +/-200mV.
Therefore, there is a particular need for a reset circuit that can achieve low power consumption, small area, and temperature compensation, thereby improving the accuracy of the reset point.
Based on the technical background, the invention researches a power-on reset circuit and a method.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a power-on reset circuit and a method, wherein the circuit has accurate trigger point, is insensitive to process angle and temperature change, has the trigger point within +/-100mV along with the process angle, temperature and power supply voltage, does not rise along with the rise of the power supply voltage, and has small area and low cost.
To achieve the above object, a first aspect of the present invention provides a power-on reset circuit, including:
The voltage divider comprises a voltage division MOS tube and a voltage division resistor, and is provided with a voltage division output point for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
the hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point and is used for avoiding reset voltage jitter caused by power voltage jitter;
the input end of the comparator is electrically connected with the voltage division output point, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the trigger voltage division into logic signals;
And the input end of the buffer is electrically connected with the output end of the comparator, and the output end of the buffer is used as the output end of the power-on reset circuit to output reset voltage for increasing the driving capability of the power-on reset circuit.
The first aspect of the present invention provides a power-on reset method performed in the power-on reset circuit, including:
Generating the trigger voltage division through the voltage division MOS tube and the voltage division resistor and adjusting the power consumption of the power-on reset circuit;
The trigger voltage division is transmitted to the input ends of the hysteresis and the comparator at the same time;
The hysteresis device performs signal hysteresis through the trigger voltage division and the output signal of the comparator, so that reset voltage jitter caused by power voltage jitter is avoided;
the comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer;
the buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit.
The beneficial effects of the invention include:
(1) The power-on reset circuit provided by the invention has the advantages that the trigger point is accurate, insensitive to process angle and temperature change, the trigger point is within +/-100mV along with the process angle, temperature and power supply voltage, and does not rise along with the rise of the power supply voltage, and the power-on reset circuit is small in area and low in cost.
(2) The power-on reset circuit provided by the invention has the advantages that the power consumption is controlled by the electric leakage of the intrinsic NMOS tube, the power consumption does not rise along with the rising of the power supply voltage, and the current of a voltage divider channel can be flexibly changed through the resistance value of the voltage dividing resistor, so that the extremely low power consumption target of the whole design is realized.
(3) According to the power-on reset circuit, the current is controlled by controlling the gate-source voltage of the intrinsic NMOS tube, so that the design of extremely low power consumption is realized, and meanwhile, the use of a large-size MOS tube is avoided, so that the cost is saved.
(4) The power-on reset circuit provided by the invention has the advantages that the trigger voltage division is controlled by the intrinsic NMOS tube, the first voltage division NMOS tube and the second voltage division NMOS tube, and the three are NMOS transistors, so that better process and temperature following can be realized, and the trigger voltage division is smaller in different processes and temperatures.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.
Fig. 1 is a schematic circuit structure diagram of a conventional power-on reset circuit.
Fig. 2 is a schematic diagram of another circuit structure of a conventional power-on reset circuit.
Fig. 3 is a schematic structural diagram of a power-on reset circuit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of voltage waveforms of each node in an embodiment of the power-on reset circuit according to the present invention.
Reference numerals illustrate:
M0-second voltage-dividing NMOS tube, M1-first voltage-dividing NMOS tube, M2-intrinsic NMOS tube, M3-second hysteresis NMOS tube, M4-first hysteresis NMOS tube, M5-comparison NMOS tube, M6-comparison PMOS tube, M7-first buffer NMOS tube, M8-first buffer PMOS tube, M9-second buffer NMOS tube, M10-second buffer PMOS tube, R0-voltage-dividing resistor;
VDD-power, GND-ground, A-divided output point, B-comparator output, PORB-power-on reset circuit output.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the preferred embodiments of the present invention are described below, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein.
In the present invention, unless otherwise indicated, terms of orientation such as "upper and lower" are used to generally refer to the upper and lower portions of the device in normal use, and "inner and outer" are used with respect to the profile of the device. Furthermore, the terms "first, second, third and the like" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first, second, third" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The present invention provides a power-on reset circuit, as shown in fig. 3, comprising:
The voltage divider comprises a voltage division MOS tube and a voltage division resistor R0, and is provided with a voltage division output point A for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
the hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point A and is used for avoiding reset voltage jitter caused by power supply VDD voltage jitter;
The input end of the comparator is electrically connected with the voltage division output point A, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the triggering voltage division into logic signals;
And the input end of the buffer is electrically connected with the output end B of the comparator, and the output end is used as the output end PORB of the power-on reset circuit to output reset voltage for increasing the driving capability of the power-on reset circuit.
In the invention, the trigger point is accurate, insensitive to process angle and temperature change, the trigger point is within +/-100mV along with the process angle, temperature and power supply VDD voltage change range, and does not rise along with the power supply VDD voltage rise, and the invention has small area and low cost.
According to the invention, the voltage division MOS tube comprises an intrinsic NMOS tube M2, a first voltage division NMOS tube M1 and a second voltage division NMOS tube M0;
the drain electrode of the intrinsic NMOS tube M2 is electrically connected with a power supply VDD, and the source electrode is electrically connected with one end of a divider resistor R0;
the other end of the divider resistor R0 is electrically connected with the grid electrode of the intrinsic NMOS tube M2 and the drain electrode of the first divider NMOS tube M1 at the same time and is used as a divider output point A;
the source electrode of the first voltage division NMOS tube M1 is electrically connected with the drain electrode of the second voltage division NMOS tube M0, and the grid electrode is electrically connected with the power supply VDD;
The source electrode of the second voltage division NMOS tube M0 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second voltage division NMOS tube M0.
In the invention, the power consumption is controlled by the electric leakage of the intrinsic NMOS tube M2, does not rise along with the rising of the voltage of the power supply VDD, and can flexibly change the current of a voltage divider passage through the resistance value of the voltage dividing resistor R0, thereby realizing the aim of extremely low power consumption of the whole design.
In the invention, the gate-source voltage of the intrinsic NMOS tube M2 is controlled to control the current, so that the design of extremely low power consumption is realized, and meanwhile, the use of a large-size MOS tube is avoided, thereby saving the cost.
In the invention, the trigger voltage division is controlled by the intrinsic NMOS tube M2, the first voltage division NMOS tube M1 and the second voltage division NMOS tube M0, and the three are NMOS transistors, so that better process and temperature following can be realized, and the voltage of the trigger point is less changed under different processes and temperatures.
In the invention, the trigger point voltage refers to the voltage of the corresponding power supply at the moment when the reset voltage suddenly changes from the logic low level to the logic high level or from the logic high level to the logic low level along with the rising or falling of the power supply, and the trigger voltage division is the voltage generated by the trigger point voltage at the voltage division output point A of the voltage divider, as shown in figure 3.
According to the invention, the hysteresis NMOS tube comprises a first hysteresis NMOS tube M4 and a second hysteresis NMOS tube M3;
the drain electrode of the first hysteresis NMOS tube M4 is electrically connected with the voltage division output point A, and the source electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M3;
The source electrode of the second hysteresis NMOS tube M3 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M.
According to the invention, the comparator comprises a comparison PMOS tube M6 and a comparison NMOS tube M5;
the source electrode of the comparison PMOS tube M6 is electrically connected with the power supply VDD, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the drain electrode;
the source electrode of the comparison NMOS tube M5 is electrically connected with the ground GND, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the grid electrode of the first hysteresis NMOS tube M4;
The gates of the comparison PMOS tube M6 and the comparison NMOS tube M5 are electrically connected with the voltage division output point A at the same time.
Preferably, the buffer comprises at least two stages of buffer units connected in series;
the input end of the first-stage buffer unit is electrically connected with the drain electrode of the comparison NMOS tube M5;
The output end of the final buffer unit is used as the output end PORB of the power-on reset circuit;
the input end of each stage of buffer unit is electrically connected with the output end of the previous stage of buffer unit except the final stage;
The number of the buffer units connected in series in at least two stages is even.
Preferably, each stage of buffer unit comprises a buffer PMOS tube and a buffer NMOS tube;
the source electrode of the buffer PMOS tube is electrically connected with the power supply VDD, and the drain electrode of the buffer PMOS tube is electrically connected with the drain electrode of the buffer NMOS tube;
The source electrode of the buffer NMOS tube is electrically connected with the ground GND;
the grid electrodes of the buffer PMOS tube and the buffer NMOS tube are electrically connected with each other and serve as the input end of the buffer unit;
the drain electrode of the buffer NMOS tube is used as the output end of the buffer unit.
The invention also provides a power-on reset method performed in the power-on reset circuit, which comprises the following steps:
Triggering voltage division is generated through a voltage division MOS tube and a voltage division resistor R0, and the power consumption of a power-on reset circuit is adjusted;
The trigger voltage division is transmitted to the input ends of the hysteresis and the comparator at the same time;
the hysteresis device performs signal hysteresis by triggering the voltage division and the output signal of the comparator, so that reset voltage jitter caused by power supply VDD voltage jitter is avoided;
the comparator converts the trigger voltage division into a logic signal and outputs the logic signal to the buffer;
the buffer converts the logic signal output by the comparator into a driving signal to drive an external circuit.
According to the invention, the generation of the trigger voltage division and the adjustment of the power consumption of the power-on reset circuit through the voltage division MOS tube and the voltage division resistor R0 comprises the following steps:
When the voltage of the power supply VDD is lower than the sum of threshold voltages of the first voltage dividing NMOS tube M1 and the second voltage dividing NMOS tube M0, the first voltage dividing NMOS tube M1 and the second voltage dividing NMOS tube M0 are not conducted, the intrinsic NMOS tube M2 is conducted without current, and the voltage division is triggered to be high level;
When the voltage of the power supply VDD is not less than the sum of the threshold voltages of the first voltage dividing NMOS transistor M1 and the second voltage dividing NMOS transistor M0 and gradually increases, the voltage between the source and the drain of the intrinsic NMOS transistor M2 gradually increases, the current flowing through the voltage gradually increases, the voltage between the gate and the source gradually decreases, and the value of the voltage is equal to the negative value of the product of the current flowing through the intrinsic NMOS transistor M2 and the voltage dividing resistor R0, in this process, the intrinsic NMOS transistor M2 works in a linear region and triggers the voltage dividing to gradually decrease;
when the power supply VDD voltage increases to the trigger point voltage, the trigger voltage division is low enough to cause the reset voltage to jump from a logic low level to a logic high level;
When the voltage of the power supply VDD continues to increase, so that the decrease of the voltage between the gate and the source of the intrinsic NMOS transistor M2 causes the decrease of the current flowing through the intrinsic NMOS transistor M2 to exceed the increase of the voltage between the source and the drain, so that the current flowing through the intrinsic NMOS transistor M2 works in a saturation region, the current flowing through the intrinsic NMOS transistor M2 remains unchanged, and the value of the trigger voltage division is close to the voltage of the gate and the source of the second voltage division NMOS transistor M0 and remains unchanged;
The current flowing through the voltage divider channel is regulated by regulating the size of the voltage regulating resistor, so that the power consumption of the power-on reset circuit is regulated.
Preferably, the hysteresis device performs signal hysteresis by triggering the voltage division and the output signal of the comparator, and avoiding reset voltage jitter caused by power supply VDD voltage jitter includes:
When the trigger voltage division is at a high level, the output voltage of the comparator is at a low level, and the hysteresis is turned off;
When the trigger voltage is gradually reduced to the threshold voltage of the comparator, the output voltage of the comparator is high level, the first hysteresis NMOS tube M4 is turned on due to the rising of the grid voltage, the second hysteresis NMOS tube M3 is turned on accordingly to continuously pull down the trigger voltage, and if the power supply VDD voltage in the power-down process is reduced to the trigger point voltage in the rising of the power supply VDD, the trigger voltage prevents the reset voltage from changing from the logic high level to the logic low level unless the power supply VDD voltage is continuously reduced, so that reset voltage jitter caused by the shaking of the power supply VDD voltage is avoided.
According to the present invention, a buffer for converting a logic signal output from a comparator into a driving signal to drive an external circuit includes:
The logic signals output by the comparator are converted into driving signals in a grading way through at least two stages of buffer units connected in series to drive an external circuit.
The present invention will be described in more detail with reference to the following examples.
Example 1
As shown in fig. 3, the present embodiment provides a power-on reset circuit, including:
The voltage divider comprises a voltage division MOS tube and a voltage division resistor R0, and is provided with a voltage division output point A for generating trigger voltage division and adjusting the power consumption of the power-on reset circuit;
the hysteresis device comprises a hysteresis MOS tube which is electrically connected with the voltage division output point A and is used for avoiding reset voltage jitter caused by power supply VDD voltage jitter;
The input end of the comparator is electrically connected with the voltage division output point A, and the output end of the comparator is electrically connected with the input end of the hysteresis device and is used for converting the triggering voltage division into logic signals;
The input end of the buffer is electrically connected with the output end B of the comparator, and the output end is used as the output end PORB of the power-on reset circuit to output reset voltage for increasing the driving capability of the power-on reset circuit;
The voltage division MOS tube comprises an intrinsic NMOS tube M2, a first voltage division NMOS tube M1 and a second voltage division NMOS tube M0;
the drain electrode of the intrinsic NMOS tube M2 is electrically connected with a power supply VDD, and the source electrode is electrically connected with one end of a divider resistor R0;
the other end of the divider resistor R0 is electrically connected with the grid electrode of the intrinsic NMOS tube M2 and the drain electrode of the first divider NMOS tube M1 at the same time and is used as a divider output point A;
the source electrode of the first voltage division NMOS tube M1 is electrically connected with the drain electrode of the second voltage division NMOS tube M0, and the grid electrode is electrically connected with the power supply VDD;
the source electrode of the second voltage division NMOS tube M0 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second voltage division NMOS tube M0;
the hysteresis NMOS tube comprises a first hysteresis NMOS tube M4 and a second hysteresis NMOS tube M3;
the drain electrode of the first hysteresis NMOS tube M4 is electrically connected with the voltage division output point A, and the source electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M3;
the source electrode of the second hysteresis NMOS tube M3 is electrically connected with the ground GND, and the grid electrode is electrically connected with the drain electrode of the second hysteresis NMOS tube M3;
the comparator comprises a comparison PMOS tube M6 and a comparison NMOS tube M5;
the source electrode of the comparison PMOS tube M6 is electrically connected with the power supply VDD, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the drain electrode;
the source electrode of the comparison NMOS tube M5 is electrically connected with the ground GND, and the drain electrode of the comparison NMOS tube M5 is electrically connected with the grid electrode of the first hysteresis NMOS tube M4;
The grid electrodes of the comparison PMOS tube M6 and the comparison NMOS tube M5 are electrically connected with the voltage division output point A at the same time;
in this embodiment, the buffer includes two stages of buffer units connected in series;
the input end of the first-stage buffer unit is electrically connected with the drain electrode of the comparison NMOS tube M5;
the output end of the second-stage buffer unit is used as the output end PORB of the power-on reset circuit;
the input end of the second-stage buffer unit is electrically connected with the output end of the first-stage buffer unit;
In the embodiment, the first-stage buffer unit comprises a first buffer PMOS tube M8 and a second buffer NMOS tube M7, and the second-stage buffer unit comprises a second buffer PMOS tube M10 and a second buffer NMOS tube M9;
the source electrode of each stage of buffer PMOS tube is electrically connected with the power supply VDD, and the drain electrode is electrically connected with the drain electrode of the buffer NMOS tube;
The source electrode of each stage of buffer NMOS tube is electrically connected with the ground GND;
The grid electrodes of each stage of buffer PMOS tube and buffer NMOS tube are mutually and electrically connected and serve as the input end of the buffer unit;
the drain electrode of each stage of buffer NMOS tube is used as the output end of the buffer unit.
The embodiment provides a power-on reset method, which includes:
When the voltage of the power supply VDD is lower, the second voltage division NMOS tube M0 or the first voltage division NMOS tube M1 is not conducted, and the voltage divider channel is closed, the intrinsic NMOS tube M2 can be conducted but no current flows, vgs=0 and Vds=0;
When the voltage of the power supply VDD gradually exceeds the sum of the threshold voltages of the second voltage division NMOS tube M0 and the first voltage division NMOS tube M1, the second voltage division NMOS tube M0 and the first voltage division NMOS tube M1 are gradually conducted to rapidly pull down a voltage division output point A, at the moment, the intrinsic NMOS tube M2 is in a linear region, vds of the intrinsic NMOS tube M2 gradually increases, so that the current gradually rises, vgs of the intrinsic NMOS tube M2 also gradually decreases, vgs_M2= -I.R0, when the voltage of the voltage division output point A is reduced to the threshold voltage of the comparator, the voltage of an output end B of the comparator is rapidly raised, and an output end PORB signal of a power-on reset circuit jumps from 0 to 1;
When the voltage of the power supply VDD reaches a certain value, the Vgs of the intrinsic NMOS tube M2 is reduced to cause the current of the intrinsic NMOS tube M2 to be reduced, the current of the intrinsic NMOS tube M2 is increased to cause the current of the intrinsic NMOS tube M2 to be increased beyond the increase of Vds, and the current of the intrinsic NMOS tube M2 is kept constant after that, the intrinsic NMOS tube M2 enters a saturation region with enough Vds, the voltage of the power supply VDD continuously rises, and the current of the intrinsic NMOS tube M2 is kept unchanged;
The gate voltage of the first hysteresis NMOS tube M4 is changed to be high to conduct the hysteresis passage, and the voltage division output point A is pulled down to be lower by the currents generated by the second hysteresis NMOS tube M3 and the first hysteresis NMOS tube M4, so that when the power supply VDD is powered down, the trigger point is lower than the trigger point when the power supply VDD is raised, and the jitter of the output end PORB of the power-on reset circuit caused by the jitter of the power supply VDD can be avoided;
The current of the voltage divider channel can be flexibly changed by adjusting the resistance value of the voltage dividing resistor R0, so that the aim of extremely low power consumption of the whole design is fulfilled;
the circuit controls the current by controlling the Vgs of the intrinsic NMOS tube M2 of the intrinsic NMOS tube, so that the design with extremely low power consumption is realized, and meanwhile, the use of a large-size MOS tube is avoided, thereby saving the cost;
The triggering voltage division of the voltage division output point A is limited by the intrinsic NMOS tube M2, the first voltage division NMOS tube M1 and the second voltage division NMOS tube M0, and the three are NMOS transistors, so that better process and temperature following can be realized, and the triggering point is smaller in change under different processes and temperatures.
Fig. 4 shows a schematic diagram of voltage waveforms of each node in the power-on reset circuit, from which it can be seen that the power-on reset method provided by the invention realizes accurate triggering of the trigger point.
The power-on reset circuit provided by the embodiment of the invention has the advantages of accurate trigger point, insensitivity to process angle and temperature change, small area and low cost, and the trigger point is within +/-100mV along with the process angle, temperature and power supply voltage, and does not rise along with the rising of the power supply voltage.
The foregoing description of embodiments of the invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410633048.XA CN118473390B (en) | 2024-05-21 | 2024-05-21 | A power-on reset circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410633048.XA CN118473390B (en) | 2024-05-21 | 2024-05-21 | A power-on reset circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118473390A CN118473390A (en) | 2024-08-09 |
| CN118473390B true CN118473390B (en) | 2025-03-21 |
Family
ID=92151148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410633048.XA Active CN118473390B (en) | 2024-05-21 | 2024-05-21 | A power-on reset circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118473390B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066971A (en) * | 2012-12-31 | 2013-04-24 | 成都锐成芯微科技有限责任公司 | Ultra-low power consumption high-precision power-on reset circuit |
| CN112994671A (en) * | 2021-02-08 | 2021-06-18 | 苏州领慧立芯科技有限公司 | Low-power-consumption small-area high-precision power-on reset circuit |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369310A (en) * | 1992-06-01 | 1994-11-29 | Hewlett-Packard Corporation | CMOS power-on reset circuit |
| US5847586A (en) * | 1995-11-08 | 1998-12-08 | Burstein; Steven | Enhanced power-on-reset/low voltage detection circuit |
| US7876135B2 (en) * | 2008-02-29 | 2011-01-25 | Spectra Linear, Inc. | Power-on reset circuit |
| JP2010141552A (en) * | 2008-12-11 | 2010-06-24 | Toppan Printing Co Ltd | Power-on reset circuit and generating method of power-on reset signal |
| CN101588167B (en) * | 2009-06-18 | 2011-06-15 | 广州润芯信息技术有限公司 | Electrifying reset and undervoltage turnoff circuit |
| CN201541247U (en) * | 2009-11-20 | 2010-08-04 | 中兴通讯股份有限公司 | A power-on reset device for an integrated circuit chip |
| CN106411300B (en) * | 2016-09-26 | 2019-05-31 | 上海华力微电子有限公司 | A kind of electrification reset circuit |
| CN114598306A (en) * | 2022-03-11 | 2022-06-07 | 珠海普林芯驰科技有限公司 | Low-power-consumption power-on reset circuit and power-on reset method |
| CN116633333A (en) * | 2023-05-30 | 2023-08-22 | 灵动微电子(苏州)有限公司 | Power-on reset circuit and integrated circuit |
-
2024
- 2024-05-21 CN CN202410633048.XA patent/CN118473390B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066971A (en) * | 2012-12-31 | 2013-04-24 | 成都锐成芯微科技有限责任公司 | Ultra-low power consumption high-precision power-on reset circuit |
| CN112994671A (en) * | 2021-02-08 | 2021-06-18 | 苏州领慧立芯科技有限公司 | Low-power-consumption small-area high-precision power-on reset circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118473390A (en) | 2024-08-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10481625B2 (en) | Voltage regulator | |
| JP3782726B2 (en) | Overcurrent protection circuit | |
| US10503189B1 (en) | Voltage regulator and dynamic bleeder current circuit | |
| US9454164B2 (en) | Method and apparatus for limiting startup inrush current for low dropout regulator | |
| JP5516320B2 (en) | Semiconductor integrated circuit for regulator | |
| JP5353548B2 (en) | Band gap reference circuit | |
| JP2004280923A (en) | Internal power supply circuit | |
| US8314649B1 (en) | Semiconductor apparatus | |
| TWI514104B (en) | Current source for voltage regulator and voltage regulator thereof | |
| US20140300408A1 (en) | Semiconductor device having a complementary field effect transistor | |
| US6545530B1 (en) | Circuit and method for reducing quiescent current in a voltage reference circuit | |
| CN118473390B (en) | A power-on reset circuit and method | |
| JP4848959B2 (en) | Power circuit | |
| US20240272665A1 (en) | Low-dropout regulator and operation method | |
| JP2019200579A (en) | Voltage regulator | |
| CN118642558A (en) | Low voltage drop linear regulator, DC-DC power supply and control method | |
| CN113031694B (en) | Low-power-consumption low-dropout linear regulator and control circuit thereof | |
| CN115528787B (en) | Control loop accelerating circuit | |
| CN109387768B (en) | Test system and test method of reference voltage circuit | |
| CN114356017B (en) | LDO module and voltage generation circuit thereof | |
| CN111580593A (en) | Multistage amplifier circuit with current limiting circuit | |
| US11068004B2 (en) | Regulator with reduced power consumption using clamp circuit | |
| CN111488026B (en) | Power supply voltage stabilizing circuit | |
| KR100967029B1 (en) | Regulator with Soft Start | |
| CN114995564B (en) | Starting circuit, starting method and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |