CN118409921B - Storage test unit, test method thereof and electronic equipment - Google Patents
Storage test unit, test method thereof and electronic equipment Download PDFInfo
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Abstract
The invention provides a storage test unit, a test method thereof and electronic equipment, wherein the test method of the storage test unit comprises the following steps: writing first-class data into the storage device, and fully writing the storage device; writing second-class data into the storage device, wherein the second-class data covers the first-class data, and powering off or hard resetting the storage device in the process of writing the second-class data; and after the storage device is powered on again, the storage data of the storage device is read, when the second type of data written before the power failure is reserved in the storage data, after the reserved second type of data is covered by the first type of data, the storage data are all the first type of data in the whole-disk reading and checking process, and then the test of the storage device is passed. The invention provides a storage test unit, a test method thereof and electronic equipment, which can test the retention capacity of the storage equipment on the data integrity and have higher test accuracy.
Description
Technical Field
The present invention relates to the field of storage testing technologies, and in particular, to a storage testing unit, a testing method thereof, and an electronic device.
Background
The most basic requirement of the storage device is to ensure the correctness of the stored data. In the storage field, a Non-Volatile Memory (NVM) can ensure that data stored therein is not lost when static, but if a Memory chip is powered down while data is being written to the Memory chip, the stored data is highly likely to be lost. In the event of a power failure, the data integrity of the storage device is difficult to guarantee, which may result in loss of operating system data or user file data stored within the storage device, and thus the retention of data integrity by the memory chip is unknown.
Disclosure of Invention
The invention aims to provide a storage test unit, a test method thereof and electronic equipment, which can test the data integrity maintaining capability of the storage equipment and have higher test accuracy.
In order to solve the technical problems, the invention is realized by the following technical scheme:
The invention provides a test method of a storage test unit, which comprises the following steps:
Writing first-class data into a storage device, and fully writing the storage device;
writing second-class data into the storage device, wherein the second-class data covers the first-class data, and the storage device is powered off or hard reset in the process of writing the second-class data; and
And after the second type of data written before power failure is reserved in the stored data, the reserved second type of data is covered by the first type of data, and the stored data are all the first type of data when the whole disk is read and checked, so that the test of the storage device is passed.
In one embodiment of the present invention, the step of writing the second type of data to the storage device includes:
Setting a plurality of test segments, wherein the second type of data is stored in the test segments, the plurality of test segments are provided with numbers, the test segments comprise at least one logic block, the addresses of the plurality of logic blocks are distributed continuously in the test segments, the number of the logic blocks and the addresses of the plurality of test segments are set randomly, and the addresses of the plurality of test segments are not overlapped;
And writing the test sections into the storage equipment in sequence according to the serial number sequence.
In an embodiment of the present invention, in the step of writing the test segment to the storage device, the test segment is randomly written to the storage device, and the second type data overwrites the first type data at the writing location.
In one embodiment of the present invention, the step of powering off or hard resetting the storage device comprises: starting from writing the second test segment, powering off or hard resetting the storage device during writing of any one of the test segments.
In one embodiment of the present invention, the step of re-reading the stored data of the storage device includes obtaining a power-off segment, the power-off segment being the test segment being written when a power-off or hard reset occurs.
In an embodiment of the present invention, the judging conditions for passing the test of the storage device include: the second type of data is stored in the test segment written before the power-off segment, and the first type of data is stored in the test segment written after the power-off segment.
In an embodiment of the present invention, the judging conditions for passing the test of the storage device include: in the power-off section, the first type of data is allowed to be stored in part of logic blocks, wherein the logic blocks storing the first type of data are positioned at the tail of the power-off section.
In an embodiment of the invention, the test method comprises preparing a plurality of the test segments before writing the second type of data.
The invention provides a storage test unit, comprising:
The test section preparation module is used for preparing a plurality of test sections and recording addresses and data block numbers of the test sections, wherein the addresses of the plurality of test sections are not overlapped;
the first data writing module is used for writing first-class data into the storage equipment and filling the storage equipment;
the second data writing module writes second type data into the storage device according to the address of the test section, wherein the second type data covers the first type data;
the power-off execution module is used for powering off or hard resetting the storage device in the process of writing the second type of data; and
And the verification recovery module is used for reading the storage data of the storage device after the power is turned on again, when the second type data written before the power failure is reserved in the storage data, and after the reserved second type data is covered by the first type data, the storage data are all the first type data in the whole-disk reading verification process, and the test of the storage device is passed and the test passing of the storage device is judged.
The invention provides an electronic device comprising a storage device, a processor and a computer program stored in a storage medium and executable on said processor, characterized in that the processor implements a method of testing a storage test unit according to any one of the preceding claims when executing said computer program.
As described above, the invention provides a storage test unit, a test method thereof and electronic equipment, which can test whether the storage equipment still has good data integrity maintaining capability under the condition of abnormal power failure. According to the technical scheme provided by the invention, the self-test capability of the storage equipment is achieved, the test efficiency is high, the test error caused by the hardware problems such as bad blocks can be eliminated, and the test accuracy is high.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory test unit according to an embodiment of the invention.
Fig. 2 is a schematic functional structure of a controller according to an embodiment of the invention.
FIG. 3 is a schematic diagram illustrating a functional structure of a processor according to an embodiment of the invention.
FIG. 4 is a flowchart of a method for testing a memory device according to an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating writing of test segments and first type data according to an embodiment of the present invention.
FIG. 6 is a power-down timing diagram of a test segment during writing according to an embodiment of the present invention.
Fig. 7 is a schematic block diagram of an electronic device according to an embodiment of the present invention.
Fig. 8 is a schematic block diagram illustrating the structure of a computer-readable storage medium according to an embodiment of the present invention.
In the figure: 100. a storage device; 110. a controller; 111. a power-down early warning module; 112. a data management module; 120. caching by a controller; 130. a flash memory chip; 200. a power management module; 300. storing the test unit; 310. a storage host; 320. a power supply controller; 330. an input/output interface; 400. a processor; 411. a test section preparation module; 412. a first data writing module; 413. a second data writing module; 414. a power-off execution module; 415. checking a recovery module; 500. computer instructions; 501. a computer-readable storage medium; RST, reset port; dataChunk, a test section.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The test object of the storage test unit provided by the invention is a storage device, and particularly a nonvolatile storage device, and the storage test unit can be used for testing the data integrity maintaining capability of the nonvolatile storage device. In the present invention, the nonvolatile memory device is a flash memory or a memory device including a flash memory, such as an SM flash memory card, a CF card, a multimedia card (Multi MEDIA CARD, MMC), a Secure digital card (Secure DIGITAL CARD, SD card), a memory stick, a micro hard disk, and the like. Referring to fig. 1, an object to be measured is a storage device 100. In the present invention, the memory device 100 includes a controller 110 and a flash memory chip 130. Wherein the controller 110 includes a controller cache 120. The controller 110 is electrically connected to the memory test unit 300 to receive control commands and host data. The controller cache 120 is electrically connected to the controller 110 and the flash memory chip 130. In writing data to the memory device 100, the data is first written to the controller cache 120 and then transferred from the controller cache 120 to the flash memory chip 130. In this embodiment, the storage device 100 is electrically connected to the power management module 200, and the power management module 200 supplies power to the storage device 100. In the present invention, when power failure occurs, the stored data in the flash memory chip 130 is not lost, and the data in the controller cache 120 is lost.
Referring to fig. 1, in an embodiment of the invention, a storage test unit 300 includes a storage host 310, a power controller 320, and an input-output interface 330. The storage host 310 is electrically connected to the controller 110 to send clock signals, control commands and host data to the controller 110. Wherein the host data is not limited to user data or process file data, etc. And the controller 110 may also feed back data of the control result to the storage host 310. The power controller 320 is electrically connected to the power management module 200 to control the power-off time and the power-on time of the power management module 200. The power controller 320 is electrically connected to the power management module 200 through an integrated circuit bus (Inter-INTEGRATED CIRCUIT, I2C). In the present embodiment, the input/output interface 330 is a General-purpose input/output bus (GPIO). The input/output interface 330 is electrically connected to the reset terminal RST of the memory device 100, so as to input a signal for controlling the reset to the memory device 100, so as to control the reset process of the memory device 100. In one embodiment of the invention, a logical schematic of a memory device 100 is shown in Table 1. The logic block is the minimum read-write unit of the memory device 100, and in this embodiment, sequential read-write or random read-write can be performed on the logic block.
Referring to fig. 2, in one embodiment of the present invention, when writing data to the memory device 100, the data is preferentially written into the controller cache 120 and then transferred to the flash memory chip 130. When data is written into the memory device 100, the address used is a logical address of a logical block, and after the controller 110 and its firmware are arranged, the address of the data is a physical address of the logical block when the data is finally written into the flash memory chip 130. And when the data is written, an address mapping relation is established between the logical address and the physical address of the written data, so that the physical address of the written data can be found according to the address mapping relation when the written data is called. The address mapping relationship of the write data may be stored in the controller cache 120 in the form of a linked list, thereby forming an address mapping table of the write data. When a power failure occurs, the address mapping table stored in the controller cache 120 is also lost, so that the data corresponding to the lost part of the address mapping table becomes invalid data. The valid data is data that can be found by the address mapping table.
Referring to fig. 2, in an embodiment of the present invention, the controller 110 includes a power-down warning module 111 and a data management module 112. The power failure early warning module 111 is electrically connected to the storage host 310, and receives a power failure indication instruction of the storage host 310. When a power down action in the plan is to occur, the storage host 310 sends a power down indication instruction to the controller 110 before the power down time. The time of sending the power-down instruction and the interval time of the power-down time are data backup time. When the power-down early warning module 111 receives the power-down instruction, the data management module 112 transfers the data in the controller cache 120 to the flash memory chip 130. It should be noted that, during the data backup time, the data buffered by the transfer controller 120 is the first priority of the storage device 100, and the data transfer is completed at the fastest transmission speed of the device, so as to avoid data loss. In this embodiment, after power is turned off and turned on again, the data of the flash memory chip 130 is read again, and whether the data is lost is checked. Data may be recovered when the data is lost. The present invention is not limited to the operation of data recovery to the storage device 100. In the invention, when the power failure occurs unplanned, the abnormal power failure is obtained. In the event of an abnormal power failure, the storage host 310 may not issue a power failure instruction, or the data backup time is too short in spite of the power failure instruction, all or part of the data in the controller cache 120 is lost, and part of the data in the flash memory chip 130 may become invalid data. Wherein the lost data of the controller cache 120 includes an address mapping table and user data.
Referring to fig. 1 and 3, in one embodiment of the present invention, a storage host 310 includes a processor 400. Wherein the processor 400 comprises a test section preparation module 411, a first data write module 412, a second data write module 413, a power down execution module 414, and a verification restoration module 415. Wherein the first data writing module 412 and the second data writing module 413 are used to write data to the storage device 100. The test segment preparation module 411 is configured to select a logic block from the storage device 100 to form a plurality of test segments. Wherein the address selection of the plurality of test segments is random and the addresses of the plurality of test segments do not overlap each other. In this embodiment, the test section includes a plurality of logic blocks. In the same test segment, a plurality of logical block addresses are distributed continuously. The first data write module 412 writes the first type of data to the storage device 100 until the storage device 100 is full. If the second type of data is stored in the address to be written, the first type of data is used to overwrite the original second type of data when the first data writing module 412 writes the data. The second data writing module 413 writes the second type of data to the test segment of the storage device 100, and the second type of data covers the original first type of data. In this embodiment, the first type of data is preset data, and the tester can determine the content of the first type of data. The second type of data is randomly generated data and is different from the first type of data. For the convenience of description of the scheme of this embodiment, in the following embodiments, the first type of data is, for example, 0xA5, and the second type of data is, for example, 0x5A. The power-off execution module 414 is electrically connected to the power controller 320 and the input/output interface 330. The power-off execution module 414 sends a power-off instruction or a power-on instruction to the power controller 320 to adjust the power supply condition of the storage device 100 through the power controller 320 and the power management module 200. Wherein the power down execution module 414 may also output a hard reset signal to the input-output interface 330. The input/output interface 330 is electrically connected to the reset port RST of the memory device 100. For example, the hard reset signal is a low level signal, and the power-down execution module 414 outputs the low level signal to the reset port RST, thereby resetting the memory device 100 to achieve the effect of simulating abnormal power down. In another embodiment of the present invention, the processor 400 may also be provided in the controller 110, thereby providing the memory device 100 with self-test capability.
Referring to fig. 1 and 3, in an embodiment of the present invention, after the power is turned on again, the verification restoration module 415 reads the data of the flash memory chip 130 and the controller cache 120, and compares and determines whether the type of the data stored in the test segment which is written before the power is turned off and the type of the data stored in the test segment which is not written before the power is turned off meets the expectations. Specifically, the second type of data should be stored in the test section written before power failure, the first type of data should be stored in the test section not written before power failure, and the first type of data and the second type of data may be partially used in the power failure test section. And after restoring all of the test segment written before the power-off, the power-off test segment, and the test segment not written before the power-off to the first type of data, the check restoration module 415 checks whether the whole disk of the storage device 100 is the first type of data.
Referring to fig. 1, 3 and 4, the present invention provides a testing method of a memory test unit, which includes steps S10 to S50.
And step S10, writing the first type of data into the storage device and filling the storage device.
And S20, setting a test section, wherein the second type of data is stored in the test section, and randomly writing the test section into the storage device.
Step S30, powering off the storage device or hard resetting the storage device when writing the test segment.
And S40, reading the data of the test section, and detecting whether the second type of data written before power failure is completely reserved.
And S50, covering the second type data by the first type data, restoring the storage device, and if all the data in the storage device are the first type data, passing the test.
Referring to fig. 1 and fig. 3-5, in an embodiment of the present invention, in step S10, the first data writing module 412 writes the first type of data to the storage device 100 until the entire disk of the storage device 100 is written with the first type of data. As shown in fig. 5, the first type of data is, for example, 0xA5. In step S20, a plurality of test segments DataChunk are first generated. Wherein the test segment DataChunk stores a second type of data. The second type data is different from the first type data. As shown in fig. 5, the second type of data is, for example, 0x5A. In step S20, the test segments DataChunk have respective numbers to distinguish between the different test segments DataChunk. As shown in fig. 5, the present embodiment provides, for example, 5 test segments DataChunk, and test segments DataChunk _1, dataChunk _2, dataChunk _3, dataChunk _4, and DataChunk _5, respectively. It should be noted that, the test segment DataChunk is to package consecutive logic blocks. In this embodiment, in step S20, when the test segment DataChunk is written to the storage device 100, the data content of the test segment DataChunk is first written to the controller cache 120. And then transferred into flash memory chip 130.
In step S20, the prepared test piece is shown in the following table, for example. Table 1 shows the address distribution, size, and type of data stored in the test segment before and after power down, and the distribution of logic blocks in the memory device 100. It should be noted that the test segment refers to an address selected from the storage device for writing as the second type of data. Addresses outside the test segment are not involved in the test steps of the present invention in the storage device. For example, logical block_0, logical block_1, logical block_5, and so on, as shown in the following table. It should be further noted that, although the addresses outside the test section do not participate in the test procedure of the present invention, the execution method of the instructions by different storage devices is different, and the storage devices may have errors, so that it is not excluded that the addresses outside the test section participate in the test procedure of the present invention during the test, thereby causing errors in data. The testing method provided by the invention can eliminate the errors and more comprehensively test the retention of the data integrity of the storage device. As shown in the following table, the test segments include one or more logic blocks, the following table shows only 5 test segments, and does not limit the test segments to 5. In the preparation phase, consecutive logical blocks are randomly selected from the memory device 100 as test segments. Wherein the selected logical block address is the address of the test segment. For example, the address of test segment_2 is the addresses of logical blocks_2 to logical block_4. In the test segment, addresses of a plurality of logical blocks are distributed consecutively. In the present invention, the test segment may have only one logic block. Addresses of the plurality of test segments are randomly distributed in the storage device, and addresses between the plurality of test segments do not overlap. In this embodiment, when preparing test segments, logic blocks are randomly selected to form a plurality of test segments. And numbering the test segments, wherein the number of the test segments is irrelevant to the address sequence of the test segments. It should be noted that, addresses of a plurality of test segments are randomly selected, and the selected logical blocks of the test segments are recorded and written. As shown in fig. 5 and the following table, the logical block addresses of the test segments written to the storage device 100 are random, and the process of writing the test segments is written according to the serial number sequence of the test segments, i.e., the test segment_1, the test segment_2, the test segment_3, the test segment_4, and the test segment_5 are written in sequence. After the test section is prepared, the address of the test section is recorded.
Table 1 is as follows.
Referring to fig. 1 and 3-6, in step S20, test segments DataChunk are written to the storage device 100 according to the serial number sequence of the test segments in an embodiment of the present invention. And in other embodiments of the invention, the test segments may be written with data out of the numbered order. In step S30, starting from the second test segment DataChunk _2, a power-down indication or a reset indication may occur during the write process of either test segment DataChunk. As shown in fig. 6, in the present embodiment, after writing the test segment DataChunk _1 and the test segment DataChunk _2, and while writing the test segment DataChunk _3, the power-off execution module 414 sends a power-off instruction to the power controller 320, and the power controller 320 controls the power management module 200, so that the storage device 100 is powered off. In another embodiment of the present invention, the power-down execution module 414 inputs a hard reset signal to the reset port RST through the input-output interface 330 to reset the memory device 100 and empty the memory data in the controller cache 120. As shown in fig. 6, the power supply VCC/VCCQ is a power supply for the memory device 100. It should be noted that the present invention does not limit the number of the test segment in which data writing is being performed when power-off occurs.
Referring to fig. 1, 3-6, in step S40, the power is turned on again after the power is turned off. Wherein the time interval between power-off and power-on again is not limited by the present invention. Specifically, the interval between power down and power up again is greater than the general recovery time of the storage device 100. It should be noted that, according to different parameters of the type of the storage device 100, the data recovery time of the storage device 100 has a mean value, and the general recovery time in this embodiment refers to the average data recovery time of the storage device 100. In step S40, after being powered up again, the data of the plurality of test segments DataChunk are sequentially read. In this embodiment, under the control of the power management module 200, the power VCC/VCCQ is powered off, wherein the power VCC/VCCQ is powered off at a power-down time node. Wherein the test segment being written cannot be completely saved and is difficult to recover at the time of power failure of the time node. The test segment before the power down time node, although not saved, can be restored in the event that the storage device 100 has an abnormal power down data restoration capability. While at the time of power down, the test segment of the memory device 100 has not been written, which is not limited by the present invention.
Referring to fig. 1, 3-6, in step S40, a test segment in which data is being written at the time of powering down the time node is used as a power-off segment, for example, test segment DataChunk _3 is used as a power-off segment. The verification restoration module 415 reads a test section where data is written before the power-off section, and a test section where data is scheduled to be written after the power-off section. It should be noted that the time sequence of writing data is based on the previous and next steps in this embodiment, and is independent of the address sequence of the test segment. As shown in fig. 5, the power-off section is a test section DataChunk _3. In this embodiment, in step S40, if the second type of data is stored in the test section in which the data is written before the power-off section and the first type of data is stored in the test section in which the data is scheduled to be written after the power-off section, the storage device 100 passes the data recovery capability test.
As shown in the above table, the power-off section is a test section_3, after the power-on is restarted, the second type data is stored in the test section_1 and the test section_2, and the first type data is stored in the test section_4 and the test section_5. In the power-off section, the first type of data may be stored in a part of the logic blocks, and the second type of data may be stored in a part of the logic blocks, as shown in the test section_3 of the table above. The logical block in which the first type of data is stored is located at the end of the power-down segment. It should be noted that, the tail of the power-off segment refers to the last 1 or more logic blocks of the address sequence in the power-off segment. In the power-off section, all logic blocks may store the first type data or the second type data. It should be noted that the types of stored data in the same logic block are the same.
Referring to fig. 1, 3-6, in step S50, the check and restoration module 415 writes the first type of data into the storage device 100 until the first type of data covers the test segment and the first type of data fills the storage device 100. In step S50, the stored data in the storage device 100 is read out to determine that the first type of data fills the storage device 100, so that the storage device 100 can ensure that the storage device 100 can realize power-off data protection, and meanwhile, the storage device 100 cannot have other storage problems due to the power-off data protection capability, thereby ensuring the comprehensiveness and accuracy of the test result.
Referring to fig. 1 and fig. 7, the present invention further provides an electronic device, where the electronic device includes a processor 400 and a storage device 100, the storage device 100 stores program instructions, and the processor 400 executes the program instructions to implement the method for testing a storage device. The processor 400 may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU for short), a network processor (Network Processor, NP for short), etc.; but also digital signal processors (DIGITAL SIGNAL Processing, DSP for short), application SPECIFIC INTEGRATED circuits (ASIC for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The storage device 100 is a mNAND-type product including, but not limited to eMMC, UFS, SSD, etc. May be one or more independent Circuit hardware, such as an Application SPECIFIC INTEGRATED Circuit (ASIC), or may be a module or system product consisting of independent Circuit hardware. It should be noted that the computer program stored in the test unit 300 may be implemented in the form of a software functional unit and may be stored in a computer readable storage medium when sold or used as a separate product. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present invention. It should be noted that, the storage testing method provided by the present invention may also be burned into the storage device 100 in a firmware manner, so as to form a complete electronic device. The processor 400 may be provided in the memory test unit 300 or in the controller 110. In another embodiment of the present invention, the test firmware storing the test method is burned into the memory device 100, and the memory test unit 300 is only used to send power-off instructions, hard reset instructions and power-on instructions required for the test, so as to control the test process. In other embodiments of the present invention, the controller 110 may actively generate power-down instructions, hard-reset instructions, and power-up instructions required for testing, while the first type of data store is mapped directly into the flash memory chip 130 by the controller firmware through a mapping table. In other embodiments of the present invention, the storage device 100 may perform self-test. Wherein the test results may be stored in predetermined locations of flash memory chip 130 and exported after the test is completed.
Referring to fig. 4 and 8, the present invention further provides a computer readable storage medium 501, where the computer readable storage medium 501 stores computer instructions 500, and the computer instructions 500 are used to make a computer execute the above-mentioned testing method of the storage device. The computer readable storage medium 501 may be an electronic medium, a magnetic medium, an optical medium, an electromagnetic medium, an infrared medium, or a semiconductor system or propagation medium. The computer-readable storage medium 501 may also include semiconductor or solid state memory, magnetic tape, removable computer diskette, random Access Memory (RAM), read-only memory (ROM), rigid magnetic disk and optical disk. Optical discs may include compact disc-read only memory (CD-ROM), compact disc-read/write (CD-RW), and DVD.
The invention provides a storage test unit, a test method thereof and electronic equipment, wherein the test method of the storage test unit comprises the following steps: and writing the first type of data into the storage device and filling the flash memory chip of the storage device. And writing the second type of data into the storage device, and powering off or hard resetting the storage device in the process of writing the second type of data. And after the power is turned on again, the storage data of the storage device is read, and when the second type of data written before the power failure is reserved in the storage data, the test of the storage device is passed. Through the scheme, whether the storage device still has good data integrity maintaining capability under the condition of abnormal power failure can be tested, and the data retention capability of different storage devices under the condition of abnormal power failure can be accurately and efficiently tested through the second class data retention condition. According to the technical scheme provided by the invention, the storage test unit can be integrated into the storage equipment, so that the storage equipment has the capability of completing self-test, the test efficiency is high, the test error caused by the hardware problems such as bad blocks can be eliminated, and the test accuracy is high.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (7)
1. A method of testing a memory test unit, comprising the steps of:
writing first-class data into a storage device, and fully writing the storage device, wherein the first-class data is preset data;
writing second-class data into the storage device, wherein the second-class data covers the first-class data, and the storage device is powered off or hard reset in the process of writing the second-class data, and the second-class data is randomly generated data and is different from the first-class data; and
After the storage device is powered on again, the storage data of the storage device are read, when the second type of data written before the power failure is reserved in the storage data, after the reserved second type of data is covered by the first type of data, the storage data are all the first type of data when the whole disk is read and checked, and then the test of the storage device is passed;
wherein writing the second type of data to the storage device comprises:
Setting a plurality of test segments, wherein the second type of data is stored in the test segments, the plurality of test segments are provided with numbers, the test segments comprise at least one logic block, the addresses of the plurality of logic blocks are distributed continuously in the test segments, the number of the logic blocks and the addresses of the plurality of test segments are set randomly, and the addresses of the plurality of test segments are not overlapped; and
Writing the test sections into the storage equipment in sequence according to the serial number sequence;
The step of re-reading the storage data of the storage device comprises the steps of acquiring a power-off section, wherein the power-off section is the test section which is being written when power-off or hard reset occurs;
The judging conditions for the passing of the test of the storage device comprise: the second type of data is stored in the test segment written before the power-off segment, and the first type of data is stored in the test segment written after the power-off segment.
2. The method according to claim 1, wherein in the step of writing the test segment to the storage device, the test segment is randomly written to the storage device, and the second-type data overwrites the first-type data of the writing location.
3. The method of claim 1, wherein powering down or hard resetting the memory device comprises: starting from writing the second test segment, powering off or hard resetting the storage device during writing of any one of the test segments.
4. The method for testing a memory test unit according to claim 1, wherein the judgment condition for passing the test of the memory device includes: in the power-off section, the first type of data is allowed to be stored in part of logic blocks, wherein the logic blocks storing the first type of data are positioned at the tail of the power-off section.
5. The method of claim 1, comprising preparing a plurality of the test segments prior to writing the second type of data.
6. A memory test unit, comprising:
The test section preparation module is used for preparing a plurality of test sections and recording addresses and data block numbers of the test sections, wherein the addresses of the plurality of test sections are not overlapped;
The first data writing module is used for writing first type data into the storage equipment and filling the storage equipment, wherein the first type data is preset data;
And a second data writing module for writing second class data to the storage device according to the address of the test segment, wherein the second class data covers the first class data, the second class data is randomly generated data and is different from the first class data, and the step of writing the second class data to the storage device comprises the following steps: setting a plurality of test segments, wherein the second type of data is stored in the test segments, the plurality of test segments are provided with numbers, the test segments comprise at least one logic block, the addresses of the plurality of logic blocks are continuously distributed in the test segments, the number of the logic blocks and the addresses of the plurality of test segments are randomly set, the addresses of the plurality of test segments are not overlapped, and the test segments are sequentially written into the storage device according to the number sequence;
the power-off execution module is used for powering off or hard resetting the storage device in the process of writing the second type of data; and
The verification recovery module is used for reading the storage data of the storage device after the storage device is powered on again, when the second type data written before the power failure is reserved in the storage data, after the reserved second type data is covered by the first type data, the storage data are all the first type data when the whole disk is read out and verified, and then the test of the storage device is passed, and the test of the storage device is judged to be passed;
The step of re-reading the storage data of the storage device comprises the steps of acquiring a power-off section, wherein the power-off section is the test section which is being written when power-off or hard reset occurs;
The judging conditions for the passing of the test of the storage device comprise: the second type of data is stored in the test segment written before the power-off segment, and the first type of data is stored in the test segment written after the power-off segment.
7. An electronic device comprising a storage device, a processor and a computer program stored in a storage medium and executable on said processor, characterized in that the processor implements a method of testing a storage test unit according to any one of claims 1 to 5 when executing said computer program.
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| US11416144B2 (en) * | 2019-12-12 | 2022-08-16 | Pure Storage, Inc. | Dynamic use of segment or zone power loss protection in a flash device |
| CN114328281B (en) * | 2021-11-30 | 2023-11-14 | 苏州浪潮智能科技有限公司 | Solid state disk abnormal power failure processing method and device, electronic equipment and medium |
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| CN110739025A (en) * | 2019-09-30 | 2020-01-31 | 广州妙存科技有限公司 | storage equipment power failure test method, device and system |
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