CN102135927B

CN102135927B - Method and device for system booting based on NAND FLASH

Info

Publication number: CN102135927B
Application number: CN 201110111751
Authority: CN
Inventors: 段琳; 赵志宇; 张颖; 钱嘉林; 李星爽
Original assignee: Hangzhou H3C Technologies Co Ltd
Current assignee: New H3C Information Technologies Co Ltd
Priority date: 2011-04-29
Filing date: 2011-04-29
Publication date: 2013-02-13
Anticipated expiration: 2031-04-29
Also published as: CN102135927A

Abstract

The invention provides a method and a device for system booting based on NAND FLASH. The method comprises the steps of: storing a plurality of boost programs in NAND FLASH in advance, carrying out offset operation on an original address sent to the NAND FLASH by a CPU (Central Processing Unit) by using a logic chip in the process of system booting in order to obtain an unread boot program address; and reading and executing the unread boot program in the NAND FLASH by the CPU, judging that the system booting is successful if the execution is successful, otherwise, restarting the CPU for trying the system booting again until the system booting is successful, or judging that the system booting fails in the event that all the boot programs are failed to execute. According to the invention, backup starting of the boot programs can be realized by replacing the read boot program address.

Description

System guiding method and device based on NAND FLASH

Technical Field

The present invention relates to a booting method of a computer system, and more particularly, to a booting method and apparatus based on a nand flash memory (NANDFLASH).

Background

At the beginning of system startup, the memory of the system is not directly readable and writable, and there is no kernel code in the memory that can be executed, which needs to perform system boot. The system boot refers to a boot program which runs before the kernel of the operating system runs, initializes hardware equipment and establishes a mapping map of a memory space through the boot program, and prepares a correct environment for finally calling the kernel of the operating system. The boot program is typically stored on a non-volatile memory device.

Current non-volatile memory devices include mainly NOR FLASH (NOR FLASH) and nand FLASH (NAND FLASH). The interface of NOR FLASH is composed of address bus, data bus and control signal lines for reading, writing, chip selection, etc., the read-write control time sequence of the interface is the same as that of RAM chip, and the on-chip execution (XIP) operation of code can be realized, so that it becomes the leading storage chip of mainstream system. As shown in fig. 1, the NANDFLASH interface has no distinction between an address bus and a data bus, and data read/write operations are performed through serial I/O buses. When NAND FLASH data is read, a read operation command needs to be sent first, an address of the data to be read is input through an I/O bus, and then the data is read through the I/O bus, and the read-write operation is different from the read-write operation of the RAM chip, so that the XIP operation cannot be realized.

NAND FLASH has the advantages of higher memory density and longer life than NOR FLASH, and therefore there is also an increasing CPU support NAND FLASH as system boot memory chips. NAND FLASH as a boot memory chip, however, has several problems during the boot process:

(1) bad block problem: due to the process characteristics of NAND FLASH, the problem of bad blocks is inevitable. The erase operation at NAND FLASH is to restore all memory cells to a logic "1" level, when there are unrecoverable pages in the data block NAND FLASH, the block is a bad block. Bad blocks are no longer available and are identified by their own oob (out of band) area.

(2) And (3) bit overturning: when data is kept and read, due to the charge releasing process of the memory cell, the problem of bit inversion can occur, and data abnormity is caused. The method for solving the problem of bit flipping is to record the ECC of the page data in the oob area of each page for the correction action during reading, so as to ensure the reliability of the data.

(3) Backup execution of boot code cannot be implemented: NAND FLASH do not support random access of data, and the purpose of replacing the starting code position and backing up the starting can not be achieved by modifying the connection mode of the address bus like NOR FLASH.

Because of the above problems, NAND FLASH has a great risk in system boot, bit flipping and bad block problems may cause errors in executing code, and random linear access cannot be supported like NOR FLASH, and backup start of code segments cannot be directly realized.

In the prior art, the starting from NAND FLASH can be realized by the connection mode shown in fig. 2, and the starting from NAND FLASH can also be realized by the connection mode shown in fig. 3.

In the connection mode shown in fig. 2, the CPU is directly connected to pins of NAND FLASH, the CPU is directly started by NAND FLASH, and due to the limitation of NAND FLASH interface, data of a specific address cannot be directly read through an address line, and backup starting of a code cannot be realized by replacing a starting code position; obviously, the connection method cannot solve the bit flipping problem of NAND FLASH, cannot ensure the reliability of the starting code, cannot ensure the reliability of the system starting, and therefore, the connection method is not suitable for mass production systems.

In the connection mode shown in fig. 3, a small-capacity NOR FLASH is used to store the initial boot code, complete the initialization of the CPU NAND FLASH controller and read the boot code of the NAND FLASH larger segment, and the read NAND FLASH code in the NOR FLASH needs to have a bad block detection and ECC algorithm code. However, this implementation requires the use of NOR FLASH chips and implements bad block detection and ECC functions, and therefore, the system design is complex.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a system boot apparatus NAND FLASH, which can implement backup start of a boot program and has a simple system design.

In order to achieve the above object, the present invention provides an NAND FLASH-based system boot apparatus, which includes a CPU, NAND FLASH, and a logic chip; wherein, the logic chip switches an input/output (I/O) bus between the CPU and the NAND FLASH; the control pin of the CPU is directly connected with the control pin of the NANDFLASH and is simultaneously accessed to the logic chip;

the NAND FLASH is used for pre-storing a main bootstrap program and one or more backup bootstrap programs;

the CPU is used for sending a read control command and an original address to NAND FLASH when system booting is needed; the original address is an address in NAND FLASH address space range; after sending the read control command and the original address, reading the bootstrap program from NAND FLASH and executing, if the execution is successful, sending a timing signal to the logic chip, otherwise, not sending the timing signal;

the logic chip is used for pre-storing the offset of each backup bootstrap program address relative to the original address; the standby boot program reading device is used for waiting for receiving a timing signal sent by a CPU and judging whether the timing signal sent by the CPU is received within a preset time, if the timing signal is not received, sending a reset signal to the CPU, restarting the CPU to try to conduct system boot again, and when the CPU re-reads the boot program, carrying out offset operation on an original address sent by the CPU to NAND FLASH according to the offset of a pre-stored standby boot program relative to the original address to obtain an unread standby boot program address, and sending the unread standby boot program address to NAND FLASH so that the CPU reads the unread standby boot program; if the unread boot program does not exist, the system boot fails.

The invention also provides a system guide method based on NAND FLASH, which is applied to the device and comprises the following steps:

A. storing a main bootstrap program and one or more auxiliary bootstrap programs in NAND FLASH in advance, and storing the offset of each auxiliary bootstrap program address relative to the original address in a logic chip in advance;

B. when the system is required to be booted, the CPU sends a read control command and an original address to NAND FLASH; after sending the read control command and the original address, reading the bootstrap program from NAND FLASH and executing, if the execution is successful, sending a timing signal to the logic chip, otherwise, not sending the timing signal;

C. the logic chip waits for receiving a timing signal sent by the CPU, judges whether the timing signal sent by the CPU is received within a preset time, if the timing signal is not received, if an unread boot program exists, sends a reset signal to the CPU, restarts the CPU to try system boot again, and when the CPU reads the boot program again, carries out offset operation on an original address sent by the CPU to NAND FLASH according to the offset of a prestored backup boot program relative to the original address to obtain an unread backup boot program address, and sends the unread backup boot program address to NANDFLASH so that the CPU reads the unread backup boot program; if the unread boot program does not exist, the system boot fails.

According to the technical scheme, the offset operation is carried out on the original address sent to NAND FLASH by the CPU in the process of carrying out system boot by using the logic chip to obtain the offset address, and the CPU reads and executes the boot program starting from the offset address in NAND FLASH to carry out system boot. The invention replaces the bootstrap program by replacing the address of the bootstrap program, can realize the backup starting of the bootstrap program and simplifies the system design.

Drawings

FIG. 1 is a schematic interface diagram of NAND FLASH;

FIG. 2 is a schematic diagram of a prior art device for performing system boot from NAND FLASH boot;

FIG. 3 is a schematic diagram of another prior art device for performing system boot from NAND FLASH boot;

FIG. 4 is a schematic structural diagram of a system guiding device NAND FLASH according to an embodiment of the present invention;

fig. 5 is a schematic diagram of an internal structure of a CPLD in the device of fig. 4;

FIG. 6 is a schematic illustration of a storage mode for the boot program in NAND FLASH of the device of FIG. 4;

FIG. 7 is a flow chart of a system booting method based on NAND FLASH according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail below with reference to the accompanying drawings and examples.

The present invention provides higher capacity characteristics within a given mold size by utilizing the high storage density of NAND FLASH, storing multiple spare boot programs in NAND FLASH, and recording the offset of each spare boot program relative to the original address; when the system is required to boot, the offset operation is carried out on the original address sent to NAND FLASH by the CPU through the logic chip, and then the address of the boot program to be read is changed, so that the purpose of reading the backup boot program to start is achieved.

The backup boot program, i.e., the backup boot program of the primary boot program, is hereinafter collectively referred to as the backup boot program.

The present invention is described in detail below by using a Complex Programmable Logic Device (CPLD) as an example, and it can be understood by those skilled in the art that the logic chip is not limited to the CPLD, and may be other logic chips, such as an FPGA.

Referring to fig. 4, fig. 4 is a structural diagram of a system boot device based on NAND FLASH according to an embodiment of the present invention; the CPLD is respectively connected with an I/O pin of the CPU NAND FLASH controller and an I/O pin of the NANDFLASH and is used for switching an I/O bus between the CPU and NAND FLASH; the control pin of the CPU is directly connected with the control pin of NAND FLASH and is connected to the CPLD.

In the apparatus of FIG. 4, NAND FLASH, for pre-storing a master boot program and one or more backup boot programs;

the CPU is used for sending a read control command and an original address to NAND FLASH when system boot is needed; after sending the read control signal and the original address, reading the bootstrap program from NAND FLASH and executing, if the execution is successful, sending a timing signal to the CPLD, otherwise, not sending the timing signal; the original address is an address in NAND FLASH address space range;

the CPLD is used for pre-storing the offset of each boot program address relative to the original address; the standby boot program address offset calculation method comprises the steps that a timing signal sent by a CPU is waited to be received, whether the timing signal sent by the CPU is received within preset time is judged, if the timing signal is not received, if a boot program which is not read exists, a reset signal is sent to the CPU, the CPU is restarted to try system boot again, when the CPU reads the boot program again, offset operation is carried out on an original address sent to NANDFLASH by the CPU according to the offset of the pre-stored standby boot program relative to the original address to obtain an unread standby boot program address, and the unread standby boot program address is sent to NAND FLASH to enable the CPU to read the unread standby boot program; if the unread boot program does not exist, the system boot fails.

Referring to fig. 5, fig. 5 is a schematic diagram of an internal structure of the CPLD in the device shown in fig. 4, which includes: the device comprises an addition unit, an address offset unit, a timing unit and a reset unit; wherein,

the adding unit is used for pre-storing the offset of each spare bootstrap program address relative to the original address;

the address offset unit is used for carrying out offset operation on the original address sent by the CPU to NAND FLASH according to the offset of the spare boot program stored in the adding unit relative to the original address to obtain an unread spare boot program address when the CPU re-reads the boot program, and sending the unread spare boot program address to NAND FLASH so that the CPU reads the unread spare boot program;

the timing unit is used for waiting for receiving the timing signal sent by the CPU and judging whether the timing signal sent by the CPU is received within the preset time, if so, the system is successfully guided, otherwise, an overtime signal is sent to the reset unit;

and the reset unit is used for judging whether a boot program which is not read exists after receiving the overtime signal sent by the timing unit, if so, sending a reset signal to the CPU, restarting the CPU to try to perform system boot again, and otherwise, failing to perform the system boot.

In addition, the CPLD also comprises a command analysis unit, which is used for detecting the state of a control pin accessed to the CPLD by the CPU, judging whether the current address cycle is the address cycle according to the state of the control pin and a read control command sent to NAND FLASH by the CPU, and if so, sending an address cycle instruction to an address offset unit;

before performing address offset operation on the original address sent by the CPU to NAND FLASH, the address offset unit is further configured to: judging whether a received address cycle instruction sent by the command analysis unit is received or not, if so, carrying out address offset operation on an original address sent to NAND FLASH by the CPU, and otherwise, setting an I/O bus between the switched CPU and NAND FLASH as a through mode; the pass-through mode is a state in which no intervention is made in data transmission between the CPU and the NAND FLASH;

the CPU reads the boot code from NAND FLASH when the I/O bus between the CPU and NAND FLASH is in pass-through mode.

Here, since NAND FLASH only has an I/O bus, when data in NAND FLASH needs to be read, it is necessary to send a read control command and a read address to NAND FLASH first, and then read data at the read address from NAND FLASH, where sending the read address is sent to NAND FLASH in an address cycle, and reading data from NAND FLASH is performed in a data cycle, which belongs to the prior art and is not described again.

In the present invention, the CPU also needs to read the boot program according to the above process, so the command parsing unit needs to determine whether the current address cycle is based on the state of the control pin and the read control command sent to NAND FLASH by the CPU, where the method for determining whether the current address cycle is the same as the prior art. If the current address cycle is the address cycle, an address cycle indication is sent to an address offset unit, the address offset unit needs to perform address offset operation according to the address cycle indication sent by the command analysis unit when the address cycle and the original address need to perform address offset operation, and in a non-address cycle, the CPLD does not need to modify any transmission data or command between the CPUs NAND FLASH, so that the I/O bus between the CPU and NAND FLASH which is switched is set to be in a through mode. The pass-through mode refers to the state of the I/O bus between the CPU and NAND FLASH where the CPLD is transitioning without any modification or interference to the data being transferred on the I/O bus.

Here, since the CPU has been processed by the CPLD before reading the boot program from NAND FLASH in accordance with whether or not system boot is first performed, the original address sent by the CPU to NAND FLASH is processed accordingly, and the processed boot program address is sent to NAND FLASH, the CPU can directly read the boot program at the boot program address in NAND FLASH after the I/O bus of the CPLD relay is set to the pass-through mode.

In addition, the timing unit also has a timing function, and the CPLD needs to start the timing function before waiting for receiving a timing signal sent by the CPU every time the system is guided; after receiving the timing signal sent by the CPU, the system is determined to be successfully guided, and the timing function is closed. The timing function can be started at any time in the system booting process, as long as the preset time is longer than the time required from the timing time to the completion of the booting program executed by the CPU. For example, the timer may be started after receiving the address of the master boot program from the CPU, or may be started when the CPU starts reading and executing the boot program.

Referring to fig. 6, fig. 6 is a schematic diagram of a storage manner of the boot program in NAND FLASH of the device shown in fig. 4. The multiple boot programs stored in NAND FLASH are stored as follows: the number of data blocks occupied by each boot program is calculated in advance according to the data block size of NAND FLASH, and each boot program is stored from the start position of the data block at the position of integral multiple of the number of NAND FLASH data blocks occupied by the boot program. For example, assuming that NAND FLASH has a data block size of 128kbytes and the boot program has a size of 550kbytes, it takes NAND FLASH total of 5 data blocks, if the boot program 1 is stored as the master boot program from the beginning of NAND FLASH at the 1 st data block, and takes NAND FLASH total of 5 data blocks from 0 to 4; the bootstrap program 2 is stored from the starting position of the 5 th data block as a first backup bootstrap program and occupies 5 blocks starting from 5 data block blocks from 5 th to 9 th; the bootstrap program 3 is stored from the start position of the 10 th data block as a second standby bootstrap program and occupies 5 data blocks from 10 th to 14 th; and so on. In practical applications, the main boot program and the backup boot program may be sequentially stored in NAND FLASH, for example, the boot program 2 may be stored from the end of the boot program 1, the boot program 3 may be stored from the end of the boot program 2, and so on. The master boot program and the standby boot program may be stored out of order.

In the invention, because the CPU performs system boot after reset and restart, the sent address is the original address when the system boot is performed each time retry. In order to start from the standby boot program, the adding unit needs to record the number of times of system boot retry so as to acquire the next unread boot program address when the execution of the boot program read this time fails.

For this purpose, the adding unit is further used for presetting and initializing the system boot retry number to be 0; further for: after receiving a timing signal sent by a CPU, resetting the system guide retry times; the system is used for waiting for receiving the retry notice sent by the reset unit and adding 1 to the number of system boot retries after receiving the retry notice sent by the reset unit;

the reset unit is further configured to: pre-storing the number of the spare boot programs; after receiving a timeout signal sent by a timing unit, judging whether the number of times of the current system boot retry is less than the pre-stored number of spare boot programs, if so, determining that the spare boot program which is not read exists, otherwise, determining that the spare boot program which is not read does not exist; when sending the reset signal to the CPU, the CPU is further used for: sending a retry notification to the addition unit;

when the address offset unit performs offset operation on the original address sent to NAND FLASH by the CPU to obtain an unread spare boot program address, the specific steps are as follows: if the current system boot retry number is n, the value obtained by adding the offset of the nth spare boot program address relative to the original address recorded in the adding unit and the original address is used as an unread spare boot program address. Where n is a natural number greater than 0.

In addition, in order to prevent unlimited retries from booting the system, the reset unit is further configured to: pre-storing the number of the spare boot programs; after receiving the time-out signal sent by the timing unit, before adding 1 to the number of system boot retries, the method is further configured to: and judging whether the number of times of the current system boot retry is less than the pre-stored number of the backup boot programs, if so, determining that the backup boot programs which are not read exist, and otherwise, determining that the backup boot programs which are not read do not exist.

The number of spare boot programs is NAND FLASH.

Here, the CPLD may determine whether the CPU is the first read boot program or the re-read boot program based on the number of times of the system boot retry, determine that the CPU is the first read boot program if the number of times of the system boot retry is 0, determine that the CPU is the re-read boot program if the number of times of the system boot retry is not 0, and perform an address offset operation on an address sent to NAND FLASH by the CPU if the number of times of the system boot retry is the re-read boot program, which has been described in detail above.

In addition, in order to further verify the correctness of the bootstrap program, a CRC record of the bootstrap program is stored in a fixed position of the bootstrap program;

after the CPU reads and executes the boot program in NAND FLASH, before sending a timing signal to the timing unit, the CPU is further configured to: and performing CRC operation on the read bootstrap program, comparing the operation result with the CRC record in the bootstrap program, and if the operation result is the same as the CRC record in the bootstrap program, sending a timing signal to the timing unit, otherwise, not sending the timing signal.

Fig. 4 shows an embodiment of the present invention, where the original address may be a master boot program address or a non-boot program address; if the address is the main bootstrap program address, when the system bootstrap is carried out for the first time, the CPLD is not needed to carry out address offset operation on the original address; if the original address is not the address of the master boot program, the CPLD needs to further perform address offset operation on the original address to obtain the address of the master boot program when the system boot is performed for the first time.

Therefore, when the original address is a non-boot address, the adding unit is further configured to: pre-storing the offset of the address of the main bootstrap program relative to the original address; the address offset unit is further configured to: when the system boot is first performed, the sum of the offset of the master boot address from the original address stored in advance in the addition unit and the original address is used as the master boot address, and the master boot address is sent to NAND FLASH.

The NAND FLASH-based system guiding device is described in detail above, and the NAND FLASH-based system guiding method is further provided by the invention.

Referring to fig. 7, fig. 7 is a flowchart of a system booting method based on NANDFLASH implemented on the apparatus shown in fig. 4, where the method includes the following steps:

step 701, storing a main bootstrap program and one or more backup bootstrap programs in NAND FLASH in advance, and storing the offset of each backup bootstrap program address relative to the original address in the CPLD in advance;

step 702, when the system boot is needed, the CPU sends a read control command and an original address to NAND FLASH, reads a boot program from NAND FLASH and executes the boot program after sending the read control command and the original address, if the boot program is executed successfully, a timing signal is sent to the CPLD, otherwise, the timing signal is not sent;

step 703, the CPLD waits for receiving a timing signal sent by the CPU, and determines whether the timing signal sent by the CPU is received within a preset time, and if the timing signal is not received, if an unread boot program exists, sends a reset signal to the CPU, restarts the CPU to try system boot again, and when the CPU re-reads the boot program, performs offset operation on an original address sent by the CPU to NAND FLASH according to an offset of a pre-stored spare boot program relative to the original address to obtain an unread spare boot program address, and sends the unread spare boot program address to the NANDFLASH, so that the CPU reads the unread spare boot program; if the unread boot program does not exist, the system boot fails.

The original address here is an address in the address space range of NAND FLASH.

In the embodiment shown in fig. 7, the CPLD also continuously monitors the state of the control pin of the CPLD to which the CPU is connected;

before the CPLD performs the address offset operation on the original address sent by the CPU to NAND FLASH, the method further includes: judging whether the current address cycle is the address cycle according to the monitored state of the control pin and a read control command sent to NAND FLASH by the CPU, if so, performing address offset operation on an original address sent to NANDFLASH by the CPU, and otherwise, setting an I/O bus between the CPU and NAND FLASH transferred by the CPLD as a through mode; the through mode is the state of the I/O bus when the CPLD does not intervene on the data information transmitted on the I/O bus between the CPU and NAND FLASH which are switched by the CPLD;

the CPU reads the boot code from NAND FLASH when the I/O bus between NAND FLASH is in pass-through mode.

In addition, the CPLD has a timing function, and the CPLD needs to start the timing function before waiting for receiving a timing signal sent by the CPU every time the system is guided; after receiving the timing signal sent by the CPU, the system is determined to be successfully guided, and the timing function is closed. The timing function can be started at any time in the system booting process, as long as the preset time is longer than the time required from the timing time to the completion of the booting program executed by the CPU. For example, the timer may be started after receiving the address of the master boot program from the CPU, or may be started when the CPU starts reading and executing the boot program.

In the embodiment of the present invention shown in fig. 7, the number of system boot retries is set and initialized in advance in the CPLD to be 0; storing the number of the boot program copies in the CPLD in advance;

after determining that the CPLD receives the timing signal sent by the CPU within the preset time, the step 703 further includes: resetting the system guide retry times; after the timing signal sent by the CPU is judged and determined not to be received within the preset time, the method further comprises the following steps: adding 1 to the system guide retry number, judging whether the current system guide retry number is smaller than the number of the backup boot programs before adding 1 to the system guide retry number, if so, judging that the backup boot programs which are not read exist, otherwise, judging that the backup boot programs which are not read do not exist;

the method for the CPLD to obtain an unread spare boot program address by performing offset operation on the original address sent by the CPU to NAND FLASH according to the offset between the spare boot program address and the original address stored in advance in step 703 is as follows: if the system boot retry number is n, the original address and the offset of the nth spare boot program address relative to the original address are added, and the sum obtained by adding is used as an unread spare boot program address.

Here, before the CPLD performs the offset operation on the original address sent by the CPU to NAND FLASH according to the offset between the pre-stored spare boot program address and the original address, it may determine whether the CPU reads the boot program for the first time or re-reads the boot program according to the current system boot retry number, if the current system boot retry number is 0, it may determine that the CPU reads the boot program for the first time, and if the current system boot retry number is not 0, it may determine that the CPU reads the boot program for the re-read. Therefore, based on the number of system boot retries, it can be determined whether an address offset operation is required for the original address.

In addition, in order to further verify the read boot program, the CRC record of the piece of boot program is stored at the fixed position of the boot program stored in NAND FLASH; step 702, after the CPU executes the boot program and before sending the timing signal to the CPLD, further includes: and performing CRC operation on the received bootstrap program, comparing the operation result with a CRC record stored at a fixed position in the bootstrap program, if the operation result is the same as the CRC record, sending a timing signal to the sending CPLD, and otherwise, not sending the timing signal.

Fig. 7 shows that, in the embodiment of the present invention, the original address may be a master boot program address or a non-boot program address; if the address of the main bootstrap program is the address of the main bootstrap program, when the bootstrap program is read for the first time, the CPLD is not required to carry out address offset operation on the original address; if the address is not the primary boot program address, then an address offset operation is also required for the original address when the boot program is read for the first time.

Therefore, when the original address is a non-boot program address, the CPLD also prestores the offset of the main boot program address relative to the original address; when the CPU first reads the boot program, the sum of the offset of the master boot program address from the original address and the original address is taken as the master boot program address, and the master boot program address is sent to NAND FLASH.

According to the technical scheme of the invention, the invention provides a system booting method and device based on NAND FLASH aiming at the problems of unreliability and impracticality existing in the system booting from NAND FLASH at present. The system boot is monitored and the address of the bootstrap program is changed by using a logic chip, and the initial process of changing the bootstrap program is transparent to the CPU and NAND FLASH, so the method is suitable for all systems using NAND FLASH; the NAND FLASH is used for multi-backup starting operation due to the characteristics of high storage density and large storage capacity, logic implementation of bad block detection and ECC (error correction code) verification is omitted on the premise of ensuring reliable starting of the system, inherent defects of a NAND FLASH chip are avoided, and the reliability of a NAND FLASH guide system is improved; in addition, the invention also simplifies the realization of interface logic and improves the realizability.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A nand flash NAND FLASH-based system boot apparatus comprising a CPU and a nand flash, the apparatus further comprising: a logic chip; wherein, the logic chip switches an input/output (I/O) bus between the CPU and the NAND FLASH; the control pin of the CPU is directly connected with the control pin of NAND FLASH and is connected to the logic chip;

2. The apparatus of claim 1, wherein the logic chip comprises: the device comprises an addition unit, an address offset unit, a timing unit and a reset unit;

the timing unit is used for waiting for receiving the timing signal sent by the CPU, judging whether the timing signal sent by the CPU is received within the preset time, and if the timing signal is not received, sending an overtime signal to the reset unit;

the reset unit is used for judging whether a boot program which is not read exists after receiving the overtime signal sent by the timing unit, if so, sending a reset signal to the CPU, restarting the CPU to try to perform system boot again, and otherwise, the system boot fails.

3. The apparatus of claim 2, wherein the logic chip further comprises a command parsing unit;

the command analysis unit is used for monitoring the state of the control pin accessed to the logic chip by the CPU, judging whether the current address cycle is the address cycle or not according to the monitored state of the control pin and a read control command sent to NAND FLASH by the CPU, and if the current address cycle is the address cycle, sending an address cycle instruction to the address offset unit;

the address offset unit, before performing the address offset operation on the original address sent by the CPU to NAND FLASH, is further configured to: judging whether an address cycle instruction sent by a command analysis unit is received or not, if so, carrying out address offset operation on an original address sent to NAND FLASH by the CPU, and otherwise, setting an I/O bus between the switched CPU and NAND FLASH to be in a through mode; the through mode is the state of the I/O bus when the logic chip does not intervene on the data information transmitted on the I/O bus between the CPU and the NAND FLASH which are switched;

the CPU reads boot code from the NANDFLASH when the I/O bus between the CPU and NAND FLASH is in the pass-through mode.

4. The apparatus of claim 3, wherein the timing unit, before waiting to receive the timing signal from the CPU, is further configured to: starting a timing function; after receiving the timing signal sent by the CPU, the CPU is further configured to turn off the timing function.

5. The apparatus of claim 4, wherein the adding unit is further configured to preset and initialize a number of system boot retries to 0; the system is used for waiting for receiving the timing signal sent by the CPU and clearing the system guide retry times after receiving the timing signal sent by the CPU; the system is used for waiting for receiving the retry notice sent by the reset unit and adding 1 to the number of system boot retries after receiving the retry notice sent by the reset unit;

the reset unit is further configured to: pre-storing the number of spare boot programs, wherein the number of spare boot programs is NAND FLASH; after receiving a timeout signal sent by a timing unit, judging whether the number of times of the current system boot retry is less than the pre-stored number of spare boot programs, if so, determining that the spare boot program which is not read exists, otherwise, determining that the spare boot program which is not read does not exist; when sending the reset signal to the CPU, the CPU is further used for: sending a retry notification to the addition unit;

when the address offset unit performs offset operation on the original address sent by the CPU to NAND FLASH according to the offset of the spare boot program address stored in the addition unit relative to the original address to obtain an unread spare boot program address, specifically: if the system boot retry number is n, the original address and the offset of the nth spare boot program address relative to the original address are added, and the sum obtained by adding is used as an unread spare boot program address.

6. The apparatus of claim 5, wherein the address offset unit determines that the CPU re-reads the boot program when the number of system boot retries in the addition unit is not 0.

7. The apparatus of claim 6, wherein a CRC record of the piece of the boot program is stored in a fixed location of the boot program in advance;

8. The apparatus of any of claims 2 to 7,

the original address is the master boot address stored in NAND FLASH;

or,

the original address is any address in NAND FLASH address space range;

the addition unit is further to: pre-storing the offset of the address of the main bootstrap program relative to the original address;

the address offset unit is further to: when the CPU first reads the boot program, the sum of the offset of the master boot program address from the original address and the original address is taken as the master boot program address, and the master boot program address is sent to NAND FLASH.

9. A system boot method based on NAND FLASH is characterized in that a logic chip switches an I/O bus between a CPU and NAND FLASH; the control pin of the CPU is directly connected with the control pin of NAND FLASH and is connected to the logic chip; the method comprises the following steps:

10. The method of claim 9, wherein a logic chip continuously monitors the state of a CPU accessing a control pin of the logic chip;

before performing the address offset operation on the original address sent by the CPU to NAND FLASH in step C, the method further includes: judging whether the current address period is the address period or not according to the monitored state of the control pin and a read control command sent to NAND FLASH by the CPU, if so, carrying out address offset operation on an original address sent to the NANDFLASH by the CPU, and otherwise, setting an I/O bus between the switched CPU and the NANDFLASH to be a through mode; the through mode is the state of the I/O bus when the logic chip does not intervene on the data information transmitted on the I/O bus between the CPU and the NAND FLASH which are switched;

step B the CPU reads the boot code from NAND FLASH when the I/O bus between it and NAND FLASH is in pass-through mode.

11. The method of claim 10, wherein the logic chip of step C further comprises, before waiting for receiving the timing signal from the CPU: starting a timing function; after receiving the timing signal sent by the CPU, the method further comprises: the timing function is turned off.

12. The method of claim 11, wherein the number of system boot retries is preset and initialized to 0; pre-storing the number of spare boot programs, wherein the number of spare boot programs is NAND FLASH;

step C, after the logic chip judges and determines that the timing signal sent by the CPU is received in the preset time, the logic chip further comprises: resetting the system guide retry times; after the timing signal sent by the CPU is judged and determined not to be received within the preset time, the method further comprises the following steps: adding 1 to the system guide retry number, judging whether the current system guide retry number is smaller than the number of the backup boot programs before adding 1 to the system guide retry number, if so, judging that the backup boot programs which are not read exist, otherwise, judging that the backup boot programs which are not read do not exist;

step C, the method for obtaining an unread spare boot program address by performing offset operation on the original address sent by the CPU to NAND FLASH according to the offset between the spare boot program address and the original address stored in advance comprises: if the system boot retry number is n, the original address and the offset of the nth spare boot program address relative to the original address are added, and the sum obtained by adding is used as an unread spare boot program address.

13. The method of claim 12, wherein the logic chip determines that the CPU re-reads the boot program when the current number of system boot retries is not 0.

14. The method of claim 13, wherein a CRC record of the piece of the boot program is previously stored at a fixed location of the boot program;

after the CPU finishes executing the boot program and before sending the timing signal to the logic chip, the method further includes: and performing CRC operation on the section of the bootstrap program, comparing the operation result with the CRC record in the section of the bootstrap program, if the operation result is the same as the CRC record in the section of the bootstrap program, sending a timing signal to the logic chip, and otherwise, not sending the timing signal.

15. A method as claimed in any one of claims 9 to 13, wherein said original address is a master boot address stored at NAND FLASH;

or,

the original address is any address in NAND FLASH address space range;

the logic chip also prestores the offset of the main bootstrap program address relative to the original address; when the CPU first reads the boot program, the sum of the offset of the master boot program address from the original address and the original address is further set as the master boot program address, and the master boot program address is sent to NAND FLASH.