CN118366920B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN118366920B CN118366920B CN202410726760.4A CN202410726760A CN118366920B CN 118366920 B CN118366920 B CN 118366920B CN 202410726760 A CN202410726760 A CN 202410726760A CN 118366920 B CN118366920 B CN 118366920B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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Abstract
The invention discloses a semiconductor structure and a manufacturing method thereof, which belong to the technical field of semiconductors, wherein the semiconductor structure at least comprises: a substrate comprising a first region and a second region; the first shallow trench isolation structure is arranged in the first region; the second shallow trench isolation structure is arranged in the second region, the width of the second shallow trench isolation structure is smaller than that of the first shallow trench isolation structure, and the depth of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure; a first active region which is the substrate between the adjacent second shallow trench isolation structures; the second active region is an epitaxial layer between adjacent second shallow trench isolation structures; and the isolation region is arranged at the bottom of the second active region. The semiconductor structure and the manufacturing method thereof provided by the invention can inhibit electric leakage caused by parasitic effect and reduce the production cost.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a semiconductor structure and a manufacturing method thereof.
Background
Shallow trench isolation (Shallow Trench Isolation, STI) is one of the important structures in integrated circuits, and is disposed between semiconductor devices to prevent current leakage between adjacent semiconductor devices and reduce the area of the isolation region. Some semiconductor devices include different functional regions, and the requirements on the width and depth of the shallow trench isolation structure are different, for example, in a dense region in an integrated circuit, parasitic effects between adjacent semiconductor devices may form a leakage channel, and in order to reduce the leakage current, STI with a small width and a large depth is required. However, in the actual manufacturing process, due to the etching load effect (Loading Effect) in the shallow trench etching process, the trench etching depth with small width is smaller, and the trench etching depth with large width is larger, so that parasitic leakage is increased in the trench with small width, and meanwhile, a gap (Viod) is easily formed in the trench with small width when the isolation medium is filled, so that the isolation performance is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, by which a second shallow trench isolation structure with high aspect ratio can be formed, electric leakage caused by parasitic effect can be restrained, cost in the production process can be reduced, and production time can be shortened.
In order to solve the above technical problems, the present invention provides a semiconductor structure, at least comprising:
A substrate comprising a first region and a second region;
the first shallow trench isolation structure is arranged in the first region;
The second shallow trench isolation structure is arranged in the second region, the width of the second shallow trench isolation structure is smaller than that of the first shallow trench isolation structure, and the depth of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure;
a first active region which is the substrate between the adjacent second shallow trench isolation structures;
The second active region is an epitaxial layer between adjacent second shallow trench isolation structures; and
And the isolation region is arranged at the bottom of the second active region. In an embodiment of the present invention, the widths of the first active region and the second active region are equal.
In an embodiment of the present invention, two sides of the isolation region extend to bottoms of the second shallow trench isolation structures at two sides of the second active region.
In an embodiment of the present invention, a width of the first shallow trench isolation structure is 1.4 times to 1.8 times that of the second shallow trench isolation structure.
In an embodiment of the present invention, an aspect ratio of the first shallow trench isolation structure is 5:1 to 7:1, and an aspect ratio of the second shallow trench isolation structure is 10:1 to 14:1.
The invention also provides a manufacturing method of the semiconductor structure, which at least comprises the following steps:
Providing a substrate, wherein the substrate comprises a first area and a second area;
Forming a first shallow trench isolation structure in the first region;
Forming a second shallow trench isolation structure in the second region, wherein the width of the second shallow trench isolation structure is smaller than that of the first shallow trench isolation structure, the depth of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure, and etching and depositing isolation media of the second shallow trench isolation structure and the first shallow trench isolation structure are obtained synchronously;
The substrate between the adjacent second shallow trench isolation structures is a first active region; and
And the epitaxial layer between the adjacent second shallow trench isolation structures is a second active region.
In an embodiment of the present invention, the method for manufacturing the first shallow trench isolation structure and the second shallow trench isolation structure includes:
forming a hard mask layer on the substrate;
Forming a patterned photoresist layer on the hard mask layer;
Etching the hard mask layer and the substrate by taking the patterned photoresist layer as a mask, forming a first shallow trench in the first region, and forming a second shallow trench in the second region, wherein the width and the depth of the second shallow trench are respectively larger than those of the first shallow trench;
depositing an isolation medium to completely fill the first shallow trench, forming a first shallow trench isolation structure, wherein the isolation medium is formed on the side wall and the bottom of the second shallow trench, and a concave part is formed between the isolation medium in the second shallow trench; and
Etching the isolation medium, removing the isolation medium at the bottom of the concave part, and forming the second shallow trench isolation structure by the isolation medium on the side wall of the second shallow trench.
In an embodiment of the present invention, the manufacturing method further includes: and after removing the isolation medium at the bottom of the concave part, performing inclined ion implantation on the substrate at the bottom of the concave part to form an isolation region.
In an embodiment of the present invention, the implantation angle of the inclined ion implantation is 5 ° to 10 °, the implanted ions include oxygen ions, and the implantation angle is an included angle between an ion implantation direction and a normal line of the substrate.
In an embodiment of the present invention, the manufacturing method further includes: after forming the isolation region, an epitaxial layer is formed in the recess, and the surface of the epitaxial layer is flush with the surface of the substrate.
In summary, the present application provides a semiconductor structure and a method for fabricating the same, which have the unexpected technical effect of forming a second shallow trench isolation structure with small width and large depth in a dense region, and completely isolating adjacent active regions, thereby suppressing leakage caused by parasitic effects. The etching step is reduced, the filling quality of the isolation medium is improved, and gaps are not formed in the isolation medium. The second shallow trench isolation structure with high depth-to-width ratio can be formed, and the size of the second shallow trench isolation structure is smaller than that of the photoetching mask plate, so that the cost for developing the small-size mask plate is reduced. In the manufacturing process, the photoresist process is only needed to be carried out once, so that the cost for developing various masks is reduced, the raw material cost in the production process is reduced, and the production time is shortened. The widths of the first active region and the second active region on the second region are equal, the performance consistency of the semiconductor device can be improved, and the isolation effect can be further improved by the isolation region at the bottom of the second active region, so that the yield of the semiconductor structure is improved.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of forming a pad oxide layer, a pad nitride layer and a patterned photoresist layer on a substrate in one embodiment.
Fig. 2 is a schematic diagram of a first shallow trench and a second shallow trench formed in an embodiment.
FIG. 3 is a schematic illustration of an isolation medium and recesses deposited in an embodiment.
FIG. 4 is a schematic diagram of an embodiment after etching the isolation medium.
FIG. 5 is a schematic diagram illustrating the formation of isolation regions in one embodiment.
Fig. 6 is a schematic diagram of an epitaxial layer deposited in one embodiment.
Fig. 7 is a schematic diagram of a semiconductor structure in an embodiment.
Description of the reference numerals:
10. A substrate; 11. a pad oxide layer; 12. pad nitriding layer; 13. patterning the photoresist layer; 131. a first opening; 132. a second opening; 141. a first shallow trench; 142. a second shallow trench; 15. an isolation medium; 16. a concave portion; 17. a first shallow trench isolation structure; 18. an isolation region; 19. an epitaxial layer; 20. a second shallow trench isolation structure; 21. a first active region; 22. a second active region; 100. a first region; 200. a second region.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Referring to fig. 7, in an embodiment of the present application, the semiconductor structure includes a substrate 10, the substrate 10 includes a first region 100 and a second region 200, a first shallow trench isolation structure 17 is formed in the first region 100, and a second shallow trench isolation structure 20 is formed in the second region 200. The width of the second shallow trench isolation structure 20 is smaller than the width of the first shallow trench isolation structure 17, the depth of the second shallow trench isolation structure 20 is larger than the depth of the first shallow trench isolation structure 17, and etching and depositing isolation media of the second shallow trench isolation structure 20 and the first shallow trench isolation structure 17 are obtained synchronously, so that the manufacturing process is simplified, and electric leakage caused by parasitic effects can be restrained. The substrate 10 between the adjacent second shallow trench isolation structures 20 is a first active region 21, the epitaxial layer between the adjacent second shallow trench isolation structures 20 is a second active region 22, and the widths of the first active region 21 and the second active region 22 are equal to form the same type of semiconductor device, so that the performance consistency of the semiconductor device is improved. Specifically, a specific structure of the semiconductor structure and a method for manufacturing the semiconductor structure of the present application are shown in fig. 1 to 7.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 is made of any suitable semiconductor material, such as a substrate of sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or silicon germanium (GeSi), and the like, and further includes a stacked structure made of these semiconductor materials, or is made of silicon on insulator, silicon germanium on insulator, and the like, which can be specifically selected according to the manufacturing requirements of the semiconductor device. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, and the substrate 10 may be an undoped substrate, a doped substrate, or an N-type substrate or a P-type substrate, and the thickness of the substrate 10 is not particularly limited and is selected according to the manufacturing requirements.
Referring to fig. 1, in an embodiment of the present invention, a substrate 10 includes a first region 100 and a second region 200, for example, to form shallow trench isolation structures with different widths and depths. The first region 100 is, for example, a device sparse region, and the second region 200 is, for example, a device dense region. In the present embodiment, the first region 100 is used to form an edge region of a Nand-flash Memory or a Nor-flash Memory, for example, and the second region 200 is used to form a Memory Cell (Memory Cell) of the Nand-flash Memory or the Nor-flash Memory, for example. In another embodiment of the present invention, the first region 100 and the second region 200 are used to form sparse regions and dense regions, respectively, of other semiconductor devices.
Referring to fig. 1, in an embodiment of the present invention, a hard mask layer is formed on a substrate 10, and the hard mask layer includes, for example, a pad oxide layer 11 and a pad nitride layer 12. The pad oxide layer 11 is, for example, a dense silicon oxide or the like, and the pad oxide layer 11 is prepared by, for example, a thermal oxidation method or an In-situ vapor growth method (In-Situ Steam Generation, ISSG) or the like, to obtain a dense silicon oxide or the like. In this embodiment, for example, the pad oxide layer 11 is prepared by an in-situ vapor growth method, specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900 ℃ to 1150 ℃, oxygen mixed with a small amount of hydrogen is introduced, silicon on the surface of the substrate 10 reacts with oxygen and hydrogen at a high temperature to generate a dense pad oxide layer 11, and the quality of the generated pad oxide layer 11 is better. The thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, 10nm, 40nm, 30nm, 40nm, or the like.
Referring to fig. 1, in an embodiment of the present invention, after forming a pad oxide layer 11, a pad nitride layer 12 is formed on the pad oxide layer 11, and the pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. Wherein the pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the pad nitride layer 12. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and the pad nitride layer 12 may be formed by low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or the like. Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and reacted at a pressure of, for example, 2t to 10t and a temperature of, for example, 700 ℃ to 900 ℃, to deposit the pad nitride layer 12, and the thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. In this embodiment, the thickness of the pad nitride layer 12 is, for example, 50nm to 120nm. By providing the pad nitride layer 12, the substrate 10 can be protected from planarization processes such as Chemical Mechanical Polishing (CMP) involved in the fabrication of the shallow trench isolation structure. And the pad nitride layer 12 can be used as a mask in the shallow trench formation process, and protects the substrate 10 at other positions from damage when the substrate 10 is etched. Since the pad nitride layer 12 has high stress, the pad oxide layer 11 can be used to buffer the stress in the pad nitride layer 12, so as to avoid the defect of the substrate 10 caused by the stress, and the pad oxide layer 11 can also be used as a stop layer when the pad nitride layer 12 is etched and removed.
Referring to fig. 1, in an embodiment of the present application, after forming a pad nitride layer 12, a photoresist layer is formed on the pad nitride layer 12, and a patterned photoresist layer 13 is formed by exposing, developing, etc., wherein the patterned photoresist layer 13 includes a plurality of first openings 131 and a plurality of second openings 132. Wherein the first opening 131 is disposed on the first region 100, the second opening 132 is disposed on the second region 200, and the width of the second opening 132 is greater than the width of the first opening 131. In the present application, the number of the first and second openings 131 and 132 on the first and second regions 100 and 200 is not particularly limited, and is selected according to the kind and performance requirements of the semiconductor device. In the present embodiment, the number of the first openings 131 and the second openings 132 is merely taken as an example, and the semiconductor structure and the manufacturing method are described.
Referring to fig. 1 to 2, in an embodiment of the invention, the first opening 131 and the second opening 132 expose a portion of the pad nitride layer 12 to define a shallow trench location. The first shallow trench 141 and the second shallow trench 142 are formed, for example, rectangular, by etching in the direction of the substrate 10 using the patterned photoresist layer 13 as a mask, for example, using dry etching or wet etching. In this embodiment, for example, a shallow trench is formed by dry etching, and the etching gas includes, for example, one or more of chlorine (Cl 2), trifluoromethane (CHF 3), difluoromethane (CH 2F2), nitrogen trifluoride (NF 3), sulfur hexafluoride (SF 6), hydrogen bromide (HBr), or the like, or a mixture of them with oxygen (O 2). After the shallow trench is formed, the patterned photoresist layer 13 is removed by wet cleaning or ashing process.
Referring to fig. 1 to 2, in an embodiment of the application, the first opening 131 is used for positioning the first shallow trench 141, and the second opening 132 is used for positioning the second shallow trench 142. In forming the first and second shallow trenches 141 and 142, since the width of the second opening 132 is greater than the width of the first opening 131, the depth of the second shallow trench 142 formed is greater than the depth of the first shallow trench 141 due to an etching load effect, and the width of the second shallow trench 142 is greater than the width of the first shallow trench 141. In the application, shallow trenches with different depths are formed by one-step etching, so that the etching steps are reduced.
Referring to fig. 2 to 3, in an embodiment of the invention, after forming the shallow trench, an isolation medium 15 is deposited in the shallow trench until the isolation medium 15 completely fills the first shallow trench 141. Before the isolation medium 15 is deposited, thermal oxidation treatment can be performed on the shallow trench, corners at the bottom of the shallow trench are rounded, and tip leakage phenomenon is reduced. The present invention is not limited to the deposition method of the isolation medium 15, and the isolation medium 15 formed in the shallow trench may be formed by, for example, chemical vapor deposition (Chemical Vapor Deposition, CVD) or high aspect Ratio chemical vapor deposition (HIGH ASPECT Ratio Process CVD, HARP-CVD). In this embodiment, the isolation medium 15 is obtained by depositing tetraethyl orthosilicate (TETRAETHYL ORTHOSILICATE, TEOS), specifically, at a temperature range of 300 ℃ to 500 ℃, for example, 30torr to 760torr, for example, the tetraethyl orthosilicate and an oxygen-containing precursor, for example, one of O 2 or O 3, are introduced, and the deposition time is controlled to obtain the isolation medium 15. The isolation medium 15 deposited by chemical vapor deposition has high speed and can be deposited at low temperature, and the deposited silicon dioxide has good hole filling capability and is not easy to cause the problems of gaps and the like.
Referring to fig. 2 to 3, in an embodiment of the application, when the isolation medium 15 is deposited, the first shallow trench 141 is located in the sparse region, and the width of the first shallow trench 141 is capable of ensuring that the isolation medium 15 is completely deposited, and the isolation medium 15 in the first shallow trench 141 has no void defect. Meanwhile, the width of the second shallow trenches 142 is greater than that of the first shallow trenches 141, the isolation medium 15 is deposited only on the sidewalls and bottom of the second shallow trenches 142, and the recesses 16 are formed between the isolation medium 15 within the second shallow trenches 142. When the isolation medium 15 is deposited, the isolation medium 15 is simultaneously covered on the pad nitride layer 12. In the present application, the width of the recess 16 is equal to the width of the substrate 10 between the adjacent second shallow trenches 142, specifically, in the design process, the time for the isolation medium 15 to completely fill the first shallow trenches 141 is calculated according to the width and depth of the first shallow trenches 141, and the thickness of the isolation medium 15 on the sidewalls of the second shallow trenches 142 is calculated at this time, so that the widths of the first openings and the second openings are reversely deduced, so that the width of the recess 16 is equal to the width of the substrate 10 between the adjacent second shallow trenches 142 after etching and depositing the isolation medium 15.
Referring to fig. 3 to 4, in an embodiment of the invention, after the isolation medium 15 is deposited, a portion of the isolation medium 15 is removed by dry etching, for example, the isolation medium 15 at the bottom of the recess 16 is removed until the isolation medium 15 at the bottom of the recess 16 is completely removed, and at the same time, the isolation medium 15 on the pad nitride layer 12 and in the first shallow trench is also partially removed, so as to form a first shallow trench isolation structure 17 in the first shallow trench, and the isolation medium 15 at two sides of the recess 16 forms a second shallow trench isolation structure in the subsequent manufacturing process. In this embodiment, the gas of the etching isolation medium 15 includes, for example, trifluoromethane, carbon tetrafluoride (CF 4), argon (Ar), etc., wherein the gas flow rate of trifluoromethane is, for example, 30sccm to 40sccm, for example, 35sccm, the gas flow rate of carbon tetrafluoride is, for example, 5sccm to 10sccm, for example, 7sccm, the gas flow rate of argon is, for example, 60sccm to 70sccm, for example, 65sccm. The etching power is 280W to 350W, and the etching pressure is 80Torr to 120Torr. By adopting dry etching and controlling etching conditions, vertical etching can be performed, ensuring that only the isolation medium 15 at the bottom is removed in the second shallow trench 142.
Referring to fig. 4 to 5, in an embodiment of the present invention, after removing the isolation medium 15 at the bottom of the recess 16, ion implantation is performed on the substrate 10 at the bottom of the recess 16 to form the isolation region 18. Specifically, the substrate 10 is placed in an ion implantation apparatus, and ion implantation is performed by means of inclined ion implantation in the recess 16 as shown by the arrow direction in fig. 5, and the implantation angle is, for example, 5 ° to 10 °, wherein the angle between the ion implantation direction and the normal line of the substrate is defined as the implantation angle of the ions. The ions implanted into the isolation region 18 include, for example, oxygen ions, and the implantation energy is, for example, 10kev to 50kev, and the ion concentration in the isolation region 18 is, for example, 1x10 20atoms/cm3~1x1021atoms/cm3. The implantation energy can be adjusted according to the depth of the concave portion 16, and the implantation angle is controlled so that two sides of the formed isolation region 18 are positioned at the bottom of the isolation medium 15 and are continuously arranged, and the active regions of adjacent devices are completely isolated, so that electric leakage caused by parasitic effects can be restrained. During the ion implantation, the remaining area of the substrate 10 is only formed with the isolation region 18 at the bottom of the recess 16 due to the presence of the pad nitride layer 12 and the isolation medium 15.
Referring to fig. 5-6, in one embodiment of the present invention, after forming isolation regions 18, an epitaxial layer 19 is formed on substrate 10 within recess 16. The epitaxial layer 19 is, for example, a monocrystalline silicon layer, and the epitaxial layer 19 is formed, for example, by a selective epitaxial growth method (SELECTIVE EPITAXIAL GROWTH, SEG). Specifically, the epitaxial growth gas source is, for example, one or a mixture of silane (SiH 4), trichlorosilane (SiHCl 3), dichlorosilane (Dichlorodihydrosilane, DCS), or the like. In this embodiment, the epitaxial growth gas source is, for example, a mixture of dichlorosilane and hydrogen chloride, the flow rate of dichlorosilane is, for example, 150sccm to 250sccm, the flow rate of hydrogen chloride is, for example, 30sccm to 60sccm, the epitaxial growth temperature is, for example, 850 ℃ to 950 ℃, and the epitaxial growth time is controlled until the surface of the epitaxial layer 19 is flush with the surface of the substrate 10. During the growth process, dichlorosilane decomposes to form silicon, epitaxial growth of monocrystalline silicon on the exposed silicon substrate and growth of polycrystalline silicon in other areas, while hydrogen chloride consumes polycrystalline silicon at a rate greater than that of monocrystalline silicon, so that monocrystalline silicon can be grown in and out of recess 16 without net accumulation of polycrystalline silicon in other areas.
Referring to fig. 6 to fig. 7, after the epitaxial layer 19 is formed, the pad nitride layer 12, the pad oxide layer 11 and a portion of the isolation medium 15 on the substrate 10 are removed, so that the surfaces of the substrate 10, the epitaxial layer 19 and the isolation medium 15 are located in the same plane. In the present embodiment, the pad nitride layer 12 and the pad oxide layer 11 on the substrate 10, and the isolation medium 15 protruding from the surface of the substrate 10 are removed by a planarization process such as chemical mechanical polishing. In the chemical mechanical polishing process, for example, a polishing process of a non-selective polishing slurry having substantially the same polishing rate for nitride and oxide is selected, so that the pad nitride layer 12, the pad oxide layer 11, and a part of the isolation medium 15 are simultaneously removed, and the polished surface is flattened. In another embodiment of the present application, the pad nitride layer 12, the pad oxide layer 11, and a portion of the isolation medium 15 are etched, for example, by dry etching, wet etching, or a combination of dry etching and wet etching. When dry etching is adopted, etching gas comprises one or a mixture of a plurality of types of trifluoromethane, difluoromethane or sulfur hexafluoride, or the like, or the mixture of the trifluoromethane, difluoromethane or sulfur hexafluoride and oxygen is adopted, when wet etching is adopted, acid solution is adopted to etch the pad nitride layer 12, specifically phosphoric acid with the volume fraction of 85% -88% is adopted, the pad nitride layer 12 is etched under the condition of 150 ℃ -165 ℃ for example, and etching liquid for wet etching the pad oxide layer 11 and the isolation medium 15 is hydrofluoric acid or buffer oxide etching liquid (Buffered Oxide Etch, BOE) for example. By controlling the etching process, the surfaces of the substrate 10, the epitaxial layer 19 and the isolation medium 15 are located in the same plane.
Referring to fig. 6 to 7, in an embodiment of the present application, after removing the pad nitride layer 12, the pad oxide layer 11 and a portion of the isolation medium 15 on the substrate 10, the isolation medium on both sides of the epitaxial layer 19 is defined as a second shallow trench isolation structure 20. The width of the first shallow trench isolation structure 17 is, for example, 1.4 times to 1.8 times that of the second shallow trench isolation structure 20, the aspect ratio of the first shallow trench isolation structure 17 is, for example, 5:1 to 7:1, and the aspect ratio of the second shallow trench isolation structure 20 is, for example, 10:1 to 14:1. In an embodiment of the present application, the width of the first shallow trench isolation structure 17 is, for example, 40nm, the depth is, for example, 250nm, and the width of the second shallow trench isolation structure 20 is, for example, 25nm, and the depth is, for example, 300nm. In other embodiments, the width and depth of the first and second shallow trench isolation structures 17 and 20 are designed according to the device requirements. The second shallow trench with larger width is formed firstly, after the isolation medium is deposited, the second shallow trench isolation structure with small width and large depth is formed in the dense region through etching and epitaxial growth, so that adjacent active regions can be completely isolated, and electric leakage caused by parasitic effects is restrained. The application can form the second shallow trench isolation structure with high depth-to-width ratio, and the size of the second shallow trench isolation structure is smaller than the size on the photoetching mask plate, thereby being beneficial to reducing the cost of developing the mask plate with small size. Meanwhile, in the manufacturing process, the photoresist process is only needed to be carried out once, so that the cost for developing various masks is reduced, the raw material cost in the production process is reduced, and the production time is shortened.
Referring to fig. 6 to 7, in the semiconductor structure, the substrate 10 between the second shallow trench isolation structures 20 is defined as a first active region 21, and the epitaxial layer between the second shallow trench isolation structures 20 is defined as a second active region 22. The widths of the first active area 21 and the second active area 22 are equal, and semiconductor devices of the same type are formed on the first active area 21 and the second active area 22, so that performance consistency of the semiconductor devices is improved. And the isolation region 18 at the bottom of the second active region 22, two sides of the isolation region 18 extend to the bottoms of the second shallow trench isolation structures 20 at two sides of the second active region 22, so that the isolation effect can be further improved, the electric leakage caused by parasitic effect can be suppressed, and the yield of the semiconductor structure can be improved.
Referring to fig. 7, after a semiconductor structure is obtained, the semiconductor structure is used in a Nand-flash memory or a Nor-flash memory, for example, the fabrication of a floating gate, an inter-gate dielectric layer, a control gate, etc. is performed on the second region 200 of the semiconductor structure, and the fabrication of a word line polysilicon, a control gate polysilicon on both sides of the word line polysilicon, etc. is performed on the first region 100, which will not be described in detail herein. In other embodiments, the semiconductor structure may also be used in the fabrication of semiconductor devices where dense and sparse regions exist.
In summary, the present application provides a semiconductor structure and a method for fabricating the same, which are unexpectedly capable of forming a second shallow trench isolation structure with small width and large depth in a dense region, and completely isolating adjacent active regions, thereby suppressing leakage caused by parasitic effects. Shallow trenches with different depths are formed through one-step etching, and etching steps are reduced. The second shallow trench isolation structure with high depth-to-width ratio can be formed, and the size of the second shallow trench isolation structure is smaller than that of the photoetching mask plate, so that the cost for developing the small-size mask plate is reduced. In the manufacturing process of the semiconductor structure, the photoresist process is only needed to be carried out once, so that the cost for developing various masks is reduced, the raw material cost in the production process is reduced, and the production time is shortened. The widths of the first active region and the second active region on the second region are equal, the performance consistency of the semiconductor device can be improved, and the isolation effect can be further improved by the isolation region at the bottom of the second active region, so that the yield of the semiconductor structure is improved.
Reference throughout this specification to "one embodiment," "an embodiment," or "a particular embodiment (A SPECIFIC embodiment)" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment, and not necessarily in all embodiments, of the invention. Thus, the appearances of the phrases "in one embodiment (in one embodiment)", "in an embodiment (in an embodiment)", or "in a specific embodiment (IN A SPECIFIC embodiment)" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics of any specific embodiment of the present invention may be combined in any suitable manner with one or more other embodiments. It will be appreciated that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and are to be considered as part of the spirit and scope of the invention.
It should also be understood that the embodiments of the invention disclosed above are merely intended to aid in the description of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (10)
1. A semiconductor device is provided, which is a semiconductor device, characterized in that it comprises at least:
A substrate comprising a first region and a second region;
the first shallow trench isolation structure is arranged in the first region;
The second shallow trench isolation structure is arranged in the second region, the width of the second shallow trench isolation structure is smaller than that of the first shallow trench isolation structure, and the depth of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure;
a first active region which is the substrate between the adjacent second shallow trench isolation structures;
The second active region is an epitaxial layer between adjacent second shallow trench isolation structures; and
And the isolation region is arranged at the bottom of the second active region.
2. The semiconductor structure of claim 1, wherein the first active region and the second active region are equal in width.
3. The semiconductor structure of claim 1, wherein two sides of the isolation region extend to a bottom of the second shallow trench isolation structure on two sides of the second active region.
4. The semiconductor structure of claim 1, wherein a width of the first shallow trench isolation structure is 1.4 times to 1.8 times a width of the second shallow trench isolation structure.
5. The semiconductor structure of claim 4, wherein the aspect ratio of the first shallow trench isolation structure is 5:1-7:1 and the aspect ratio of the second shallow trench isolation structure is 10:1-14:1.
6. A method for fabricating a semiconductor structure, comprising:
Providing a substrate, wherein the substrate comprises a first area and a second area;
Forming a first shallow trench isolation structure in the first region;
Forming a second shallow trench isolation structure in the second region, wherein the width of the second shallow trench isolation structure is smaller than that of the first shallow trench isolation structure, the depth of the second shallow trench isolation structure is larger than that of the first shallow trench isolation structure, and etching and depositing isolation media of the second shallow trench isolation structure and the first shallow trench isolation structure are obtained synchronously;
The substrate between the adjacent second shallow trench isolation structures is a first active region; and
And the epitaxial layer between the adjacent second shallow trench isolation structures is a second active region.
7. The method of manufacturing a semiconductor structure according to claim 6, wherein the method of manufacturing the first shallow trench isolation structure and the second shallow trench isolation structure comprises:
forming a hard mask layer on the substrate;
Forming a patterned photoresist layer on the hard mask layer;
Etching the hard mask layer and the substrate by taking the patterned photoresist layer as a mask, forming a first shallow trench in the first region, and forming a second shallow trench in the second region, wherein the width and the depth of the second shallow trench are respectively larger than those of the first shallow trench;
depositing an isolation medium to completely fill the first shallow trench, forming a first shallow trench isolation structure, wherein the isolation medium is formed on the side wall and the bottom of the second shallow trench, and a concave part is formed between the isolation medium in the second shallow trench; and
Etching the isolation medium, removing the isolation medium at the bottom of the concave part, and forming the second shallow trench isolation structure by the isolation medium on the side wall of the second shallow trench.
8. The method of fabricating a semiconductor structure of claim 7, further comprising: and after removing the isolation medium at the bottom of the concave part, performing inclined ion implantation on the substrate at the bottom of the concave part to form an isolation region.
9. The method of claim 8, wherein the oblique ion implantation has an implantation angle of 5 ° to 10 °, the implanted ions include oxygen ions, and the implantation angle is an angle between an ion implantation direction and a normal line of the substrate.
10. The method of fabricating a semiconductor structure of claim 8, further comprising: after forming the isolation region, an epitaxial layer is formed in the recess, and the surface of the epitaxial layer is flush with the surface of the substrate.
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