CN118363274B

CN118363274B - Method, system and device for improving uniformity of key dimensions of etched patterns on chips

Info

Publication number: CN118363274B
Application number: CN202410465603.2A
Authority: CN
Inventors: 张生睿; 俞宗强; 施伟杰; 鄢昌莲; 王航宇
Original assignee: Dongfang Jingyuan Electron Ltd
Current assignee: Dongfang Jingyuan Electron Ltd
Priority date: 2024-04-17
Filing date: 2024-04-17
Publication date: 2025-02-21
Anticipated expiration: 2044-04-17
Also published as: CN118363274A

Abstract

The present invention relates to the field of photolithography, and in particular, to a method, system, and apparatus for improving uniformity of critical dimensions of etched patterns on a chip. The method for improving the uniformity of the key size of the etched pattern on the chip comprises the following steps of obtaining an initial etched pattern on the chip, extracting a photoresist pattern corresponding to the initial etched pattern, providing an etching deviation table, performing first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern, obtaining a density distribution map of the initial etched pattern on the chip and obtaining the corresponding etching deviation map, establishing a mapping relation between the density distribution map and the etching deviation map, performing second compensation on the target pattern based on the mapping relation to obtain an optimized pattern, and etching the optimized pattern to obtain a final etched pattern. The problem of poor uniformity of critical dimensions of etched patterns in the etching process is solved.

Description

Method, system and equipment for improving uniformity of critical dimension of etched pattern on chip

[ Field of technology ]

The present invention relates to the field of photolithography, and in particular, to a method, system, and apparatus for improving uniformity of critical dimensions of etched patterns on a chip.

[ Background Art ]

The most central step in semiconductor chip fabrication is to transfer the design pattern of the chip onto a silicon wafer, and among the numerous process steps in chip fabrication, the processes directly related to pattern transfer are mainly photolithography and etching. And (3) a wafer Factory (FAB) obtains photomask data (Mask) corrected by Optical Proximity (OPC) from the original design layout, then forms a photoresist pattern on the photoresist, and forms an etching pattern after the photoresist pattern is developed. However, the etching process causes etching deviation, and the line width of the photoresist before etching is different from the line width of the etching material after photoresist is removed. At present, the common practice in industry is to change the designed layout according to an etching deviation table (EtchingBiasTable) to compensate the etching deviation into the photoresist pattern of the photoetching so as to rewrite and calibrate the photoresist pattern of the photoetching.

If the two photoresist patterns are assumed to have the same local environment, but different environments in a larger range, different etching load effects may result. Even if the etching deviation is considered through the etching deviation table, that is, the sizes of the photoresist patterns are the same, the sizes of the etched patterns obtained after etching are still different, which causes a problem of uniformity of line width (CDU), that is, a problem of poor uniformity of critical dimension, thereby affecting the yield of wafer factory flow.

[ Invention ]

In order to solve the problem of poor uniformity of critical dimensions of etched patterns in the etching process, the invention provides a method, a system and equipment for improving the uniformity of critical dimensions of etched patterns on a chip.

The invention provides a method for improving the uniformity of the critical dimension of an etched pattern on a chip, which comprises the following steps:

Acquiring an initial etching pattern on a chip, and extracting a photoresist pattern corresponding to the initial etching pattern;

providing an etching deviation table, and performing first compensation on the photoresist pattern through the etching deviation table after the photoresist pattern is extracted to obtain a target pattern;

acquiring a density distribution diagram of an initial etching pattern on a chip and acquiring a corresponding etching deviation diagram thereof;

establishing a mapping relation between a density distribution diagram and an etching deviation diagram;

performing second compensation on the target graph based on the mapping relation to obtain an optimized graph;

And etching the optimized pattern to obtain a final etched pattern.

Preferably, the first compensation of the photoresist pattern by the etching deviation table includes:

Parameters of the photoresist patterns comprise spacing and line width, etching deviation values are obtained through an etching deviation table, and the line width of the photoresist patterns and/or the spacing between the photoresist patterns are modified based on the etching deviation values so as to perform first compensation on the photoresist patterns.

Preferably, obtaining the density profile of the initial etch pattern on the chip includes:

dividing a chip into blocks;

acquiring the area of an initial etching pattern in a certain block;

Obtaining the initial etching pattern density of the block based on the area of the initial etching pattern in the block and the area of the block;

and acquiring the positions of the blocks, and acquiring a density distribution diagram of the initial etching pattern on the chip based on the positions of the blocks and the initial etching pattern density in the blocks.

Preferably, the obtaining the density distribution map of the initial etching pattern on the chip further comprises:

A preset first density variation value is set,

Judging whether the density difference value of the adjacent positions on the density distribution diagram of the initial etching pattern meets the requirement of being larger than a preset first density change value or not;

if yes, obtaining etching patterns corresponding to the positions meeting the requirements, and clustering the etching patterns to obtain at least two types of classification patterns;

obtaining the positions of etching patterns in the classified patterns of each category;

and obtaining the density distribution diagram of the classified patterns of the same category based on the positions of the etched patterns in the classified patterns of the same category and the density distribution diagram of the initial etched pattern.

Preferably, the step of obtaining the density distribution map of the classification pattern further comprises:

a preset second density variation value is set,

Judging whether the density difference value of adjacent positions on the density distribution diagram of the classification graph of the same category is larger than a preset second density change value or not;

if yes, setting the position as a local similar point;

Etching the target pattern corresponding to the local similar points to obtain an actual etched pattern;

and obtaining etching deviation values between actual etching patterns.

Preferably, calculating and acquiring the corresponding etching deviation map includes:

And providing an AI model, taking a density distribution diagram of an initial etching pattern on the chip as input, and calculating an etching deviation diagram corresponding to the output density distribution diagram through the AI model.

Preferably, performing the second compensation on the target graph based on the mapping relation includes:

the target pattern comprises a space and a line width;

Etching the target pattern to obtain a corresponding target etching pattern;

acquiring a density distribution diagram of a target etching pattern on a chip, and acquiring etching deviation values based on the density distribution diagram and the mapping relation of the target etching pattern;

And modifying the line width of the target patterns and/or the spacing between the target patterns based on the etching deviation values so as to carry out second compensation on the target patterns.

Preferably, etching the optimized pattern includes:

providing a local etching model, and etching the optimized pattern obtained through the second compensation by adopting the local etching model to obtain a final etching pattern;

judging whether etching deviation exists in the final etching pattern;

If the etching pattern exists, iterating the optimized pattern as a target pattern until the etching pattern finally obtained has no etching deviation, and outputting the etching pattern finally obtained.

The invention provides a system for improving the uniformity of the critical dimension of an etched pattern on a chip, which comprises:

the OPC module is used for performing analog imaging processing to obtain a photoresist pattern;

the etching module is used for carrying out etching treatment on the photoresist pattern to obtain an initial etching pattern;

the identification module is used for acquiring a density distribution diagram of an initial etching pattern on the chip;

the calculation module is used for calculating and acquiring an etching deviation graph corresponding to the initial etching graph;

The AI module is used for establishing a mapping relation between the density distribution diagram and the etching deviation diagram;

The processing module is used for carrying out first compensation on the photoresist pattern through the etching deviation table after the photoresist pattern is extracted to obtain a target pattern, and carrying out second compensation on the target pattern based on the mapping relation to obtain an optimized pattern;

And the output module is used for outputting the final etching pattern.

The invention provides a computer device which is applied to the method for improving the uniformity of the critical dimension of the etched pattern on the chip and comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the method for improving the uniformity of the critical dimension of the etched pattern on the chip.

Compared with the prior art, the method, the system and the equipment for improving the uniformity of the critical dimension of the etched pattern on the chip have the following beneficial effects:

1. The method for improving the uniformity of the critical dimension of the etched pattern on the chip provided by the embodiment of the invention comprises the following steps:

Providing an etching deviation table, and performing first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern;

And etching the optimized pattern to obtain a final etched pattern.

2. The first compensation of the photoresist pattern through the etching deviation table comprises the following steps:

Parameters of the photoresist patterns comprise spacing and line width, etching deviation values are obtained through an etching deviation table, and the line width of the photoresist patterns and/or the spacing between the photoresist patterns are modified based on the etching deviation values so as to perform first compensation on the photoresist patterns, wherein the first compensation can primarily eliminate the etching deviation of the photoresist patterns.

3. The method for obtaining the density distribution map of the initial etching pattern on the chip comprises the following steps:

dividing a chip into blocks;

acquiring the area of an initial etching pattern in a certain block;

and acquiring the positions of the blocks, and acquiring a density distribution diagram of the initial etching pattern on the chip based on the positions of the blocks and the initial etching pattern density in the blocks. The density distribution map of the initial etching pattern on the chip is obtained by obtaining the density of the initial etching pattern in each block, the calculation process is simple, and the processing efficiency is high.

4. The embodiment of the invention further comprises the following steps after obtaining the density distribution diagram of the initial etching pattern on the chip:

A preset first density variation value is set,

And obtaining the density distribution diagram of the classified patterns of the same category based on the positions of the etched patterns in the classified patterns of the same category and the density distribution diagram of the initial etched pattern. After the target patterns with the same shape are clustered, the calculation amount of the subsequent process can be greatly simplified, and the efficiency of obtaining the etching deviation graph can be improved.

5. The embodiment of the invention further comprises the following steps after obtaining the density distribution map of the classification graph:

a preset second density variation value is set,

if yes, setting the position as a local similar point;

The method comprises the steps of obtaining the etching deviation value between actual etching patterns, directly analyzing the density distribution diagram and the number of the etching deviation diagrams of the initial etching patterns to be quite large, indirectly obtaining the density distribution diagram and the etching deviation diagram of the initial etching patterns by analyzing the relationship between the density distribution diagram and the etching deviation diagram of the classification patterns, and reducing the calculated amount.

6. The method for calculating and obtaining the corresponding etching deviation graph comprises the following steps:

And providing an AI model, taking a density distribution diagram of an initial etching pattern on the chip as input, and calculating an etching deviation diagram corresponding to the output density distribution diagram through the AI model. And the AI model is applied to the analysis process of the density distribution diagram and the etching deviation diagram, so that the expressive force of the model is greatly improved, and the residual error of the model is reduced.

7. The second compensation of the target graph based on the mapping relation comprises the following steps:

the target pattern comprises a space and a line width;

Etching the target pattern to obtain a corresponding target etching pattern;

And modifying the line width of the target patterns and/or the spacing between the target patterns based on the etching deviation values so as to carry out second compensation on the target patterns. After the target pattern is subjected to the second compensation and etching process, the influence of the loading effect is considered in the photoetching and etching process, so that the final etching pattern generated by etching is closer to the expected one.

8. The method for etching the optimized graph comprises the following steps:

judging whether etching deviation exists in the final etching pattern;

if the etching pattern exists, iterating the optimized pattern as a target pattern until the etching pattern finally obtained has no etching deviation, and outputting the etching pattern finally obtained. And (3) providing a local etching model, and etching the optimized pattern obtained through the second compensation by using the local etching model to obtain a final etching pattern.

9. The embodiment of the invention also provides a system, which has the same beneficial effects as the method for improving the uniformity of the critical dimension of the etched pattern on the chip, and is not repeated herein.

10. The embodiment of the invention also provides a computer device, which has the same beneficial effects as the method for improving the uniformity of the critical dimension of the etched pattern on the chip, and the description is omitted herein.

[ Description of the drawings ]

FIG. 1a is a flowchart illustrating a method for improving uniformity of critical dimensions of etched patterns on a chip according to a first embodiment of the present invention.

FIG. 1b is a schematic diagram of a method for improving the uniformity of critical dimensions of an etched pattern on a chip for etching an optimized pattern according to a first embodiment of the present invention.

Fig. 2a is a comparison of the first embodiment of the present invention providing the same local environment but a different larger environment.

Fig. 2b is an enlarged view of the area 2c on fig. 2 a.

Fig. 3a is a flowchart illustrating a process for obtaining a density profile according to a first embodiment of the present invention.

Fig. 3b is a schematic diagram of a density profile provided by a first embodiment of the present invention.

Fig. 3c is a schematic diagram of a process for copying a chip into a copy diagram according to the first embodiment of the present invention.

Fig. 4 is a schematic diagram of post-clustering graphic categories according to the first embodiment of the present invention.

Fig. 5 is a density distribution diagram of a classification scheme according to a first embodiment of the present invention.

Fig. 6 is an etching deviation diagram provided by the first embodiment of the present invention.

FIG. 7 is a schematic diagram of a system for improving uniformity of critical dimension of etched patterns on a chip according to a second embodiment of the present invention.

Fig. 8 is a schematic structural diagram of a computer device according to a second embodiment of the present invention.

The attached drawings are used for identifying and describing:

1. A system, 2, a computer device;

11. OPC module, 12, etching module, 13, identification module, 14, calculation module, 15, AI model, 16, processing module, 17, output module, 21, memory, 22, processor, 23, and computer program.

[ Detailed description ] of the invention

For the purpose of making the technical solution and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and examples of implementation. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art will also appreciate that the embodiments described in the specification are alternative embodiments and that the acts and modules referred to are not necessarily required for the present invention.

In various embodiments of the present invention, it should be understood that the sequence numbers of the foregoing processes do not imply that the execution sequences of the processes should be determined by the functions and internal logic of the processes, and should not be construed as limiting the implementation of the embodiments of the present invention.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The most central step in semiconductor chip fabrication is to transfer the design pattern of the chip onto a silicon wafer, and among the numerous process steps in chip fabrication, the processes directly related to pattern transfer are mainly photolithography and etching. In the currently prevailing integrated circuit production process, photolithography (Lithography) technology is to chemically change a photoresist under exposure to light of a specific wavelength, for example, 193nm or 248nm, and then transfer a pattern designed on a mask into a photoresist topography on a silicon wafer by means of a developer. The etching process is based on the selective removal of unwanted material with the aid of photoresist topography, thereby ultimately creating the desired fine pattern on the wafer. That is, the designer can transfer the designed pattern onto the mask plate to form a mask pattern on the mask plate, and the photoresist can be exposed to light to form a photoresist pattern after the light passes through the mask plate, and finally the photoresist pattern is etched to form an etching pattern on the chip or the wafer.

With the continuous evolution of chip technology nodes, the size of the design layout is far smaller than the wavelength (193 nm) of photolithography, which leads to a strong diffraction effect, commonly called optical proximity effect, so that the morphology of the chip design layout and the morphology of photoresist by photolithography are greatly deviated, in order to compensate for the deviation, in the manufacturing process of an integrated circuit, a wafer Factory (FAB) needs to obtain Mask data (Mask) after Optical Proximity Correction (OPC) from the original design layout, and then the Mask data is removed from the wafer. The optical proximity correction is to correct the layout based on the lithography model, and the range of the optical proximity effect is relatively small, generally a few micrometers, so that the range considered by the lithography model is also about a few micrometers.

Further, etching after photolithography may cause etching deviation, for example, the line width of the photoresist pattern before etching is different from the line width of the etched pattern material after photoresist removal. The size of the etching deviation is related to a plurality of factors, such as substrate materials, line widths of patterns on the photoresist, parameters of the etching process and the like, the etching deviation can lead to the change of the overall size after etching, and patterns with the same size after photoetching can also become different in the size after etching. At present, the common practice in industry is to firstly change the designed layout according to an etching deviation table (Etching Bias Table) to compensate the etching deviation into the photoresist pattern of the photoetching. The compensation described above can also be considered as a correction to the etch pattern with the etch bias, and in order to obtain the desired etch pattern, the photoresist pattern is not generally directly modified. Since the formation of the photoresist pattern is determined by the mask pattern on the mask plate, the exposure condition, and the optical proximity effect (Optical Proximity Correction, also called OPC) correction, the compensation refers to the modification of one or more combinations of the mask pattern, the exposure condition, or the OPC.

The post-lithography target, i.e., the photoresist pattern, is commonly referred to as ADITARGET, and the above-described compensation, i.e., the action of modifying ADI TARGET, is commonly referred to as recalibration (recalibration), and after recalibration according to the etching bias table, during exposure, the post-exposure image is considered as the target pattern according to the photoresist pattern after correction of the etching bias, because the mask pattern, the exposure conditions, or OPC are changed. In the subsequent etching process, the corrected photoresist pattern can take etching deviation into account in advance, so that the expected etching pattern can be obtained after etching. It should be noted that, the etching deviation table is usually obtained empirically, that is, an engineer compares the pattern actually etched with the pattern expected to be obtained, and manually measures the errors of the line width (width) and the space (space) of the two patterns, so as to obtain the etching deviation table finally.

However, there is a significant loading effect (loadingeffect) during the actual etching process, for example, when the chip contains both sparse and dense patterns to be etched, the etching rate of the dense region is lower than that of the sparse region, which is also called overload effect (Micro-loadingEffect) because more reactant is consumed in the dense region during etching process and reactant cannot reach the dense etching region in time, and for example, in the etching of the structure with high aspect ratio, such as deep hole or deep groove, the etching rate of the hole or groove with smaller size is smaller than that of the hole or groove with larger size, which is called loading effect related to aspect ratio, also called aperture effect (ApertureEffect) because etching gas is difficult to enter deep part, and at the same time reaction product is difficult to overflow, resulting in the reduction of the etching rate of the bottom.

Specifically, if the local environments of the two photoresist patterns are different, the etched patterns formed after etching are necessarily different, and the photoresist patterns can be recalibrated through an etching deviation table to compensate the photoresist patterns. However, if two photoresist patterns, the local environments thereof are assumed to be the same, but the environments are not the same in a larger range. Even if the photoresist pattern is compensated by the etching deviation table, the photoresist pattern after exposure is the same and the size obtained after lithography is the same when the photoresist pattern is compensated only by the etching deviation table because the local environment is the same. However, photoresist patterns are subjected to a larger range of environmental influences during etching, which can lead to different etching loading effects. The dimensions of the etched pattern obtained immediately after etching will still be different. The photoresist patterns which are the same in local environment but different in larger environment are different in etching pattern obtained by final etching due to loading effect. This is commonly referred to as a problem of non-uniformity of critical dimensions of the etched pattern. I.e., uniformity, CDU, which can severely affect the yield of a wafer mill (FAB).

In order to suppress the load effect, on the one hand, the actual etching parameters, such as power, gas flow, gas pressure and temperature, are adjusted to achieve a more uniform etching effect, but after all, the adjustment has limitations, and if the adjustment is to be performed more finely, it is necessary to seek a method to improve the uniformity of the critical dimension of the etched pattern on the chip, so as to compensate for the negative effect of the load effect.

In order to solve the above-mentioned technical problems, referring to fig. 1a, a first embodiment of the present invention provides a method for improving uniformity of critical dimensions of etched patterns on a chip, comprising the following steps:

S1, acquiring an initial etching pattern on a chip, and extracting a photoresist pattern corresponding to the initial etching pattern;

S2, providing an etching deviation table, and performing first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern;

S3, acquiring a density distribution diagram of an initial etching pattern on the chip and acquiring a corresponding etching deviation diagram thereof;

s4, establishing a mapping relation between a density distribution diagram and an etching deviation diagram;

s5, performing second compensation on the target graph based on the mapping relation to obtain an optimized graph;

and S6, etching the optimized pattern to obtain a final etched pattern.

It will be appreciated that during the photolithography process, a designer may create a designed pattern onto a mask to form a mask pattern, and after passing through the mask pattern, the photoresist may be exposed to light to form a photoresist pattern, and finally the photoresist pattern may be etched to form an etched pattern on a chip or wafer. It should be noted that the above process may be simulated by means of a predetermined algorithm, program or software, i.e. simulating a photolithography process. Therefore, the initial etching pattern on the chip can be obtained first, and the photoresist pattern corresponding to the initial etching pattern can be extracted by means of a preset algorithm, program or software. Because of the two photoresist patterns, if the local environments are the same, but the environments are not the same in a larger range, the problem of load effect is easily caused in the etching process. The present invention can optimize the mask design by the above method to compensate for the negative effects of the loading effect. It should be noted that, since the photoresist pattern is not directly modified in the photolithography process, the method provided by the invention is to modify one or more of the mask pattern, the exposure condition or the OPC corresponding to the photoresist pattern or the target pattern. Namely, the exposure process is optimized, so that the appearance of the photoresist pattern with the same local environment is changed, and the etching pattern obtained after the etching process of the photoresist pattern is close to the expected effect. Specifically, the purpose of the compensation is to modify the morphology of the photoresist pattern or the target pattern so that the etched pattern thereof also changes. Therefore, the compensation only needs to change the appearance of the photoresist pattern or the target pattern. The detailed steps of the compensation are not repeated in the following.

Further, after the photoresist pattern is extracted, the photoresist pattern can be compensated for the first time by means of the etching deviation table to obtain a target pattern, namely, the morphology of the photoresist pattern corresponding to the initial etching pattern can be modified for the first time by means of the etching deviation table. And two conditions can occur when the compensated photoresist pattern, namely the target pattern, is etched. One is that the local environments are different between the two target patterns, so that the two target patterns have no load effect in the etching process, and the problem of OPC is considered when the patterns with different local environments are processed. The other is a target pattern which is the same as the local environment but is different in environment in a larger range, and the existing load effect cannot be eliminated only by means of the etching deviation table. Specifically, the etching deviation table is obtained empirically by engineers and is not described in detail herein.

Further, after the density distribution diagram of the initial etching pattern on the chip is obtained, the etching deviation diagram corresponding to the density distribution diagram can be obtained through calculation and measurement. It should be understood that the density distribution diagram refers to the density distribution state of the initial etching pattern on the chip, which can intuitively reflect the density degree of the etching pattern distributed on the chip. The aspect ratio is considered in the aperture effect, and the depth of the holes (holes formed by etching patterns) is generally the same, that is, the size of the holes is considered. Thus either the overload effect in the loading effect or the aperture effect in the loading effect. The density profile of the etched pattern is directly related thereto. When the local environments are the same and the positions with larger environments are different, firstly, the density distribution diagram of the position is obtained, then the position can be etched to obtain an etching pattern, the outline of the etching pattern is measured through calculation, the etching deviation value can be obtained by comparing the outline, and then the etching deviation diagram corresponding to the density distribution diagram of the initial etching pattern can be obtained through the position and the etching deviation value.

It should be noted that, the density distribution diagram may be established by manual measurement, or may be identified by providing an identification module. The density distribution map is used as an input value, and the calculated carrier can be an AI model or a polynomial algorithm model. The specific calculation carrier is not particularly limited, and the purpose is to output a corresponding etching deviation graph. Wherein the density distribution diagram represents the density distribution of etching patterns at specific positions or in a certain area on the chip, and the etching deviation diagram represents the numerical value of etching deviation corresponding to the specific position or the certain area on the chip under the certain density distribution. It should be understood that, in the process of obtaining the etching deviation map by calculating the input density distribution map, a certain amount of data is accumulated to establish the mapping relationship between the density distribution map and the etching deviation map, and the mapping relationship between the density distribution map and the etching deviation map is more accurate as the amount of data is gradually enriched. I.e. the accumulation process of data can be regarded as an iterative optimization process of the mapping relation.

Further, since the target patterns have the same local environment, the larger environments are different, that is, the shapes of the two target patterns are identical. And performing second compensation on the target graph based on the mapping relation to obtain an optimized graph. Specifically, as the mapping relationship can reflect the correspondence relationship between the density distribution map and the etching deviation map, for example, in the second compensation process, the position of the target pattern with the same local environment but different larger environments on the chip can be obtained, the density value of the position can be obtained based on the density distribution map, the corresponding etching deviation value can be obtained based on the mapping relationship, and the shape of the target pattern can be modified by optimizing the exposure process based on the etching deviation value, so that the optimized pattern can be obtained.

It should be understood that the local environments of the target patterns are the same, but the larger environments are different, so that the shapes of the target patterns are similar in the local environments, and if the target patterns are directly etched, the target patterns are affected by the load effect, so that the obtained etched patterns are different. The engineer expects that the pattern with the same local environment will result in the same etch pattern. Therefore, the optimized patterns are obtained through the second compensation on the target patterns, and the optimized patterns are similar to the target patterns in the same local environment, and are dissimilar in shape, but the optimized patterns are similar to the final etched patterns after being etched. That is, after the target pattern is compensated, the shape of the target pattern has been changed, and after the target pattern is subjected to the second compensation and etching process, the influence of the load effect is considered in the photoetching and etching processes, so that the final etching pattern generated by etching is closer to the expected one. It should be noted that, the etching process in this embodiment is by means of a preset algorithm, program or software, and will not be described in detail later.

In summary, the invention considers the problem that the photoresist patterns with the same local environment but different larger environments have load effect, and eliminates the load effect problem in the etching process by compensating the photoresist patterns twice, thereby improving the uniformity of the critical dimension of the etched pattern on the chip and further improving the yield of wafer factory flow.

Further, in the step S1, providing the initial etching pattern on the chip includes:

Providing an initial mask plate and exposure conditions;

performing simulated imaging processing on the initial mask plate based on exposure conditions to obtain a photoresist pattern;

And carrying out etching treatment on the photoresist pattern to obtain an initial etching pattern.

It should be appreciated that the lithography process of the present invention may be simulated by means of a predetermined algorithm, program or software. Such as an OPC model or an etch model. Specifically, an initial mask plate and exposure conditions are provided first, and a photoresist pattern can be obtained by simulating the process of simulating imaging processing of the initial mask plate based on the exposure conditions by means of an OPC model. Further, the initial etching model can be obtained by etching the photoresist pattern by means of the etching model. In actual photoetching, a photoresist pattern cannot be modified generally, and a final etching pattern can be seen only by adjusting exposure conditions, mask plate parameters or an OPC model.

Further, in the step S2, performing the first compensation on the photoresist pattern through the etching deviation table includes:

It can be understood that the specific step of modifying the photoresist pattern based on the etching deviation value is to input the etching deviation value into the OPC model, and modify the line width of the photoresist pattern and/or the interval between the photoresist patterns obtained after the simulated imaging processing by changing the exposure process, thereby completing the first compensation of the photoresist pattern and completing the modification of the morphology of the photoresist pattern. It should be appreciated that the first compensation may initially eliminate the etch bias of the photoresist pattern.

Specifically, after the step S2, the method further includes:

setting a preset standard, and judging whether a target graph on the chip meets the preset standard or not;

If not, indicating that the target pattern is a target pattern with different local environments, and directly etching the target pattern which does not meet the preset standard to obtain a final etched pattern;

if yes, the target graph is the target graph with the same local environment but different larger environments.

If the target graph does not accord with the preset standard and is the target graph with different local environments, the target graph shows that the load effect does not exist, and the problem of the different local environments is solved through OPC. If the target pattern meets the preset standard, the target pattern cannot be etched directly, and the load effect can be eliminated by performing secondary compensation. It should be appreciated that the target pattern, which is the same local environment and the same larger environment, may cause loading effects for process reasons, which are not considered.

Specifically, when a preset standard is set, a certain position of an initial etching pattern on the chip can be selected, and whether the initial etching pattern exists in a preset range outside the position is judged;

If not, the graph corresponding to the position does not accord with the preset standard, namely the graph corresponding to the position is the graph with the same local environment but different larger environments.

As a variation, referring to fig. 2a, fig. 2a shows a comparison of a pattern with the same local environment but different larger environments. In fig. 2a, the chip is equally divided into n×n grid points, which represent square small blocks. The preset standard is set to 100 grid points. For example, if the initial etching pattern still exists in the range of 100 lattice points in lattice point 2A, the pattern corresponding to lattice point a is the pattern with the same local environment and the same larger environment. For another example, referring to fig. 2B together, if the grid point 2B has no initial etching pattern at the 51 st grid point on the left side, the pattern corresponding to the grid point 2B is the pattern with the same local environment and different larger environment. It should be understood that the lattice points corresponding to the patterns with the same local environment and different larger environments tend to easily appear in the positions with obvious change of the density of the etched patterns on the chip.

The invention has a plurality of possible implementation modes when acquiring the density distribution map of the initial etching pattern:

In one possible implementation manner, in the step S3, obtaining the density profile of the initial etching pattern on the chip includes:

S31, dividing the chip into blocks;

s32, obtaining the area of an initial etching pattern in a certain partition;

S33, obtaining the initial etching pattern density of the block based on the area of the initial etching pattern in the block and the area of the block;

S34, acquiring the positions of the blocks, and acquiring a density distribution diagram of the initial etching pattern on the chip based on the positions of the blocks and the initial etching pattern density in the blocks.

As can be appreciated, referring to fig. 3a, fig. 3a shows a flow chart for acquiring a density profile. After dividing the chip into blocks, identifying and acquiring the area of the initial etching pattern in each block through a preset identification module, and dividing the area of the initial etching pattern in each block by the area of the block to obtain the initial etching pattern density of the block. Further, the position of the block is obtained, and the relation between the position and the density can be obtained based on the position of the block and the density of the initial etching pattern in the block, so that the density distribution diagram of the initial etching pattern on the chip can be obtained. According to the method, the density of the initial etching pattern in each block is obtained, so that the density distribution map of the initial etching pattern on the chip is obtained, the calculation process is simple, and the processing efficiency is high. Fig. 3b is a schematic representation of a density profile. In the above-mentioned process of dividing the chip into the blocks, the divided blocks may be equal-sized blocks, or may be different-sized or partially identical-sized blocks, and the size of the blocks obtained by dividing the chip is not particularly limited.

Further, referring to fig. 3c, the obtaining a density profile of an initial etching pattern on a chip further includes:

copying the chip into a plurality of identical copy graphs;

Dividing each copy graph into equal-sized blocks, wherein the sizes of the blocks on different copy graphs are different;

and obtaining a density distribution diagram of the initial etching pattern on each copy graph.

It should be appreciated that to enrich the data of the density profile, one chip may be replicated as multiple replica maps. Illustratively, as shown in FIG. 3c, the chip may be replicated as replica FIG. 3A and replica FIG. 3B. Whereas the block size on copy fig. 3A is 1000 x 1000, the block size on copy fig. 3B is 500 x 500. In the process of partitioning the duplicate graphs, the partition sizes of different duplicate graphs are different, namely, the duplicate graphs formed by copying one chip can finally correspondingly obtain a plurality of density distribution graphs, and the data of the density distribution graphs are enriched.

In another possible embodiment, in the step S3, obtaining the density profile of the initial etching pattern on the chip includes:

Selecting a certain mark point on the initial etching pattern on the chip;

selecting one or at least two preset distances outside the marking points as marking areas;

acquiring the area of an initial etching pattern in a mark area;

Obtaining the density of the initial etching pattern corresponding to the mark point based on the area of the initial etching pattern in the mark area and the area in the mark area;

and iterating the process of obtaining the density of the initial etching pattern to obtain a density distribution diagram of the initial etching pattern on the chip.

It should be understood that, in the method adopted in this embodiment, the density distribution map of the initial etching pattern on the whole chip is obtained by obtaining the density of the initial etching pattern at each mark point of the chip, so that the density distribution map is more accurate, but the processing flow is relatively longer.

Further, in other than S3, the present invention has a plurality of possible embodiments when obtaining the etching deviation map:

in one possible embodiment, the density profile represents a relationship between a pattern position and a density, and further includes, after obtaining the density profile of the initial etching pattern on the chip:

A preset first density variation value is set,

It can be appreciated that, because the volume of the density distribution map data of the initial etching pattern is too large, if the relationship between the density distribution map of the initial etching pattern and the etching deviation value is directly established, the model itself cannot cover a large amount of measurement data. Therefore, the implementation judges whether the density difference value of the adjacent positions on the density distribution diagram of the initial etching pattern meets the requirement of being larger than a preset first density variation value. If the requirement is met, the position meeting the requirement is a position with obvious density change on a density distribution diagram of the initial etching pattern. I.e. these locations are more prone to loading effect problems. It should be noted that the location is understood to be a region, and the area of the region is defined according to the same local environment but different larger environments, that is, the size of the region is defined according to the above-mentioned preset standard. Thus, a case where one region corresponds to a plurality of etching patterns, that is, one position corresponds to a plurality of etching patterns, may occur. Further, clustering the etching patterns corresponding to the positions meeting the requirements to obtain at least two categories of classified patterns. It should be understood that clustering refers to aggregating identically shaped graphics into one class. Illustratively, FIG. 4 shows a graph of several shapes, such as an "I" shape, an "L" shape, a "T" shape, a "mouth" shape, or a "Z" shape. After the etching patterns with the same shape are clustered, the calculation amount of the subsequent process can be greatly simplified, and the efficiency of obtaining the etching deviation graph can be improved. The shapes of the figures are at least shown as examples, and the specific shapes thereof are not particularly limited. In addition, the graph clustering can be realized by means of an algorithm, a model or a program, so that the purpose of gathering the etching graphs of the same type is achieved, and the purpose of improving the processing efficiency is achieved.

Further, after the etching patterns meeting the requirements are clustered, the positions of the etching patterns in the classification patterns of each category can be obtained. Specifically, the similar etching patterns on the chip can be matched according to the shape of the pattern clusters by a pattern matching method until the positions of the etching patterns in the classified patterns of each category are obtained. For example, it is assumed that there are 10 ten thousand etching patterns on a chip, and finally 1000 positions meet the requirement, that is, 1000 positions are screened, and then the respective etching patterns in the 1000 positions are clustered, and in the clustering process, it is assumed that the clustering forms 5 categories. While a graphic match for one of the categories may match to less than or equal to 1000 locations of the same local environment but different larger environments. Finally, the density distribution diagram of the classified pattern of the category can be obtained based on the matched position in the category and the density distribution diagram of the initial etching pattern. It should be noted that, the pattern matching may be by means of an algorithm, a model or a program, so as to obtain the positions of similar etching patterns, more precisely find the positions of the etching patterns with the same local environment, and the specific process of pattern matching will not be repeated.

As a variation, the pattern matching process is also omitted, and the positions of etched patterns in the classified patterns of the same class in the pattern cluster are directly acquired. For example, a pattern of a certain class is directly matched, and the density distribution diagram of the classified pattern of the class can be obtained based on the obtained position and the density distribution diagram of the initial etching pattern on the assumption that 200 positions with the same local environment but different environments are matched. The process of omitting the pattern matching is simpler.

Further, the step of obtaining the density distribution map of the classification graph further comprises:

setting a preset second density change value;

if yes, setting the position as a local similar point;

and obtaining etching deviation values between actual etching patterns.

It can be understood that the relationship between the density distribution diagram and the etching deviation diagram of the whole initial etching pattern is directly analyzed, so that the problems of large calculation amount and more measurement data can occur. In the embodiment, after the density distribution diagram of the classification pattern is obtained, the relationship between the density distribution diagram of the classification pattern of a certain class and the etching deviation can be analyzed independently, so that the analysis flow is simplified, and the analysis efficiency is improved.

Further, it is determined whether the density difference between adjacent positions on the density distribution diagram of the classification pattern of the same category is greater than a preset second density variation value. If so, the positions are set to local similarity points. It should be appreciated that the local similarity points indicate that the location is a location on the density profile of the classification pattern where the density change is significant. I.e. these locations are more prone to loading effect problems. Further, the local type points should be patterns with similar shapes, and when the local type points are etched, the shapes of actual etched patterns formed after the etching are different due to the influence of a loading effect.

Further, by acquiring the outline of the actual etching pattern, the etching deviation value can be obtained by comparing the outlines of different actual etching patterns. It should be noted that the profile of the etched pattern can be measured by SEM (electron scanning lens). It should be appreciated that engineers expect the shape of the actual etched pattern after etching of the local similarity points to be the same, so that the relationship between the density profile of the classification pattern and the etch bias value can be analyzed by comparing the profiles.

It will be appreciated that fig. 5 shows a density profile of the classification pattern. It can be seen that boxes 5A and 5B represent locations of the same type of classification graph where there is a large change in density, and these locations are local similarity points. It will be appreciated that locations on the density profile of the classification pattern where the density varies significantly tend to be more prone to loading effects. And thus the locations where these densities vary greatly are set as locally similar points. In the embodiment, the local similar points are selected through screening, so that the difficulty of analyzing the relation between the density distribution diagram and the etching deviation diagram is simplified.

In another possible embodiment, the density profile represents a relationship between a pattern position and a density, and after obtaining the density profile of the initial etching pattern on the chip, the method further includes:

selecting a center point on an initial etching pattern on a chip;

Taking the contour line of the initial etching graph as a boundary line, and selecting a deviation point in the boundary line and within a preset distance from the boundary line;

etching the target pattern corresponding to the center point to obtain an etched pattern;

etching the target pattern corresponding to the deviation point to obtain another etching pattern;

And comparing the two etching patterns to obtain etching deviation values.

It should be understood that in this embodiment, the center point of the initial etching pattern is used as a reference. And the etching deviation value is obtained through the etching patterns of the center point and the deviation point. Compared with the above embodiment, the present embodiment has the advantages of simple steps, and the etching deviation value can be obtained by directly comparing the two points. The disadvantage is the complex computation, which requires the computation of the position on the whole chip. In addition, since the selected points have randomness, the accuracy is also poor.

Further, in the step S4, the establishment of the mapping relationship between the density profile and the etching deviation profile includes various embodiments.

In one possible implementation, calculating and acquiring the corresponding etching deviation map includes:

It will be appreciated that the etch bias values, whether calculated by classifying the density profile of the pattern or directly by the density profile of the initial etch pattern, must be subjected to a calculation process. Specifically, the calculation process may be performed manually by means of a human or may be performed by means of an algorithm. The density value and the corresponding etching deviation value of a certain position are accumulated continuously in the calculation process. When a certain amount of data is accumulated, a large amount of measurement data can be generated to support AI modeling. Specifically, the density value and the corresponding etching deviation value can be used for training the AI model, the mapping relation between the density distribution map and the etching deviation map can be established after the AI model is trained, and at the moment, if the density distribution map of the initial etching pattern is used as input, the etching deviation map corresponding to the output density distribution map can be directly calculated by means of the AI model, so that the method is simple and convenient.

The method comprises the steps of copying a chip into a plurality of identical copy graphs, dividing the copy graphs into blocks with the same size as 1um,5um and 10um respectively, obtaining density distribution graphs of the blocks with different sizes, taking the density distribution graphs as input of an AI model, and outputting an etching deviation graph. Fig. 6 shows an etch bias diagram. The blocks on the etching deviation graph represent positions, and the data in the blocks represent etching deviation values corresponding to the positions. It should be understood that, in this embodiment, the mapping relationship between the density distribution diagram and the etching deviation diagram is established through the AI model, and in practical application, the etching deviation diagram may be directly given directly according to the density distribution diagram of the etching pattern, which is simple and convenient. In addition, when an immediate etching deviation table is built, excessive manual intervention is needed to continuously measure the etching pattern, the overall efficiency is low, the acquisition of data by measuring the etching pattern on a silicon wafer in a large amount is not beneficial to further improving the accuracy of the mapping relation between the density distribution diagram and the etching deviation diagram, the AI model adopted in the embodiment is generally input into a plurality of input matrices and output into a single point (point of interest), so that the AI model is creatively applied to the mapping relation for building the density distribution diagram and the etching deviation diagram, the accuracy of the mapping relation can be greatly improved, and meanwhile, the calculation efficiency can be accelerated by utilizing the high calculation capability of AI.

In another possible embodiment, calculating the etch bias value corresponding to the acquired density includes fitting a polynomial relationship of the etch bias value to its corresponding plurality of density values, and building a load bias model (bias loading mode). It should be understood that the load deviation model established in this embodiment is input as a density value at a certain position, and output as an etching deviation at that position. Compared with the embodiment of the AI model, the present embodiment has the advantages of fast calculation speed, and the disadvantage of limited fitting capability by using the polynomial relation, even if the fitting capability of the polynomial is limited, the model itself still has a larger residual even if the load deviation model is subsequently built, and if the target graph is subsequently compensated by using the load deviation model, the accuracy of the compensation process is insufficient. In addition, the framework of the load deviation model itself cannot cover a large amount of measurement data.

Further, in the step S5, performing the second compensation on the target graph based on the mapping relationship includes:

the target pattern comprises a space and a line width;

Etching the target pattern to obtain a corresponding target etching pattern;

acquiring a density distribution diagram of a target etching pattern on a chip, and acquiring an etching deviation diagram based on the density distribution diagram and the mapping relation of the target etching pattern;

Optimizing the exposure process based on the etching deviation graph to modify the line width of the target patterns and/or the spacing between the target patterns, and completing the second compensation of the target patterns.

It should be understood that, by using the mapping relationship, an etching deviation map corresponding to the density distribution map at the current target pattern can be obtained. And by etching the bias pattern, the exposure process can be optimized. In particular, the purpose of the second compensation is also to modify the topography of the target pattern. I.e., modifying the line width of the target pattern and/or the pitch between the target patterns. Further, when the target pattern is compensated for the second time to form an optimized pattern, the optimized pattern takes the existing load effect into consideration in the etching process. The principle is that the shape of the same target pattern is changed into an optimized pattern with different shapes, and then the optimized pattern is etched, and the final etching pattern generated by etching is closer to the expected pattern because the optimized pattern takes the load effect into consideration.

Further, please refer to fig. 1a and fig. 1b, in the step S6, the etching of the optimized pattern includes:

S61, providing a local etching model, and etching the optimized pattern obtained through the second compensation by adopting the local etching model to obtain a final etching pattern;

s62, judging whether etching deviation exists in the final etching pattern;

s63, if the optimized graph exists, iterating by taking the optimized graph as a target graph;

s64, outputting the finally obtained etching pattern until the finally obtained etching pattern has no etching deviation.

It can be understood that even if the target pattern is compensated according to the etching deviation map in the actual etching process to obtain the optimized pattern, the final etching pattern obtained after the optimized pattern is etched cannot be completely ensured to achieve the effect expected by the engineer. Since the loading effect is only a part of the effects in etching. The premise of being able to fully reach the expected condition is that other effects occurring during etching have been completely eliminated by the first compensation and the second compensation. In this way, at least in an ideal state, the two compensation processes can only eliminate the load effect in practice, but the CDU problem cannot be completely eliminated, so that the present solution can only slow down the CDU problem caused by the load effect in principle. It should be understood that the present invention obtains a final etching pattern by providing a local etching model and etching the optimized pattern obtained through the second compensation using the local etching model. It should be noted that, the local etching model can well eliminate other effects, and avoid the influence of other effects on the etching process, so that the finally obtained etching pattern can well eliminate the CDU problem.

And if so, iterating the optimized pattern as a target pattern until the final etching pattern does not have etching deviation, and outputting the final etching pattern. It should be appreciated that the present invention also introduces a mechanism to load the proximity correction (Loading Proximity Correction, also known as LPC) mechanism. The method is applied to actual photoetching and comprises the following steps of designing a layout, obtaining a photoresist pattern through exposure, obtaining an initial etching pattern through etching, performing first compensation on the photoresist pattern corresponding to the initial etching pattern according to an etching deviation table, calculating a density distribution diagram of the initial etching pattern, obtaining an etching deviation diagram based on the density distribution diagram, performing second compensation based on the etching deviation diagram, applying a local etching model and obtaining a final etching pattern. It should be appreciated that CDU problems may still exist in the final phase of the final etch pattern obtained, at which time a density profile of the final etch pattern may be obtained, and the step of performing the second compensation based on the etch bias pattern iterated to be continuously optimized until the final etch pattern that meets the expectations is output after the CDU problems are eliminated. I.e. the density distribution diagram of the final etching pattern is re-substituted into the AI model to obtain an etching deviation diagram, and the result can be continuously optimized based on the process of iterative second compensation of the etching deviation diagram.

For example, assuming that the photoresist pattern is pattern P1, the first compensated pattern is pattern P2, the second compensated pattern is pattern P3, after P3 is etched, it is found that the etching pattern corresponding to pattern P3 still has a CDU problem, the second compensation is performed on pattern P3 to obtain pattern P4, and if the etching pattern corresponding to pattern P4 does not have a CDU problem, pattern P4 is output.

It should be noted that, the embodiments provided in each step in the method for improving the uniformity of the critical dimension of the etched pattern on the chip provided by the present invention can be freely combined, and the specific combination manner is not limited.

By way of example, the method can acquire the etching deviation graph in a mode of combining a density distribution graph, a graph clustering and a graph matching, and generate an AI model by matching the acquired data of the density distribution graph and the etching deviation graph with an AI modeling mode, so that the expressive force of the AI model is remarkably improved, and the residual error of the model is reduced. Furthermore, the invention can add a local etching model on the basis of carrying out the second compensation through the etching deviation graph, and constructs an iterative optimization LPC mechanism similar to an OPC iterative optimization mask on the basis of obtaining a final etching graph so as to carry out iterative optimization on the CDU problem of the final etching graph, thereby directly and thoroughly solving the CDU problem.

Referring to fig. 7, a system 1 for improving uniformity of critical dimensions of an etched pattern on a chip is further provided in a second embodiment of the present invention, where the system 1 includes:

an OPC module 11 for performing analog imaging processing to obtain a photoresist pattern;

an etching module 12 for performing etching treatment on the photoresist pattern to obtain an initial etching pattern;

The identification module 13 is used for acquiring a density distribution diagram of an initial etching pattern on the chip;

the calculation module 14 is used for calculating and acquiring an etching deviation graph corresponding to the initial etching graph;

The AI module 15 is used for establishing a mapping relation between the density distribution diagram and the etching deviation diagram;

The processing module 16 is used for performing first compensation on the photoresist pattern through the etching deviation table to obtain a target pattern, and performing second compensation on the target pattern based on the mapping relation to obtain an optimized pattern;

and the output module 17 is used for outputting the final etching pattern.

The embodiment of the invention also provides a system 1, which can be applied to the method for improving the uniformity of the critical dimension of the etched pattern on the chip, and has the same beneficial effects as the method for improving the uniformity of the critical dimension of the etched pattern on the chip, and the details are not repeated here.

The third embodiment of the present invention further provides a computer device 2, which is applied to the method for improving the uniformity of the critical dimension of the etched pattern on the chip, and includes a memory 21, a processor 22 and a computer program 23 stored on the memory 21, wherein the processor 22 executes the computer program 23 to implement the method for improving the uniformity of the critical dimension of the etched pattern on the chip.

The embodiment of the present invention also provides a computer device 2, which has the same advantages as the method for improving the uniformity of the critical dimension of the etched pattern on the chip, and will not be described herein.

In order to solve the above-mentioned technical problem, a fourth embodiment of the present invention further provides a computer readable storage medium, where the computer readable storage medium stores computer instructions, where the computer instructions are configured to cause the computer device to execute the above-mentioned method for improving uniformity of critical dimensions of etched patterns on a chip.

It should be noted that a computer readable storage medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may be a machine readable signal medium or a machine readable storage medium. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a computer-readable storage medium would include one or more wire-based electrical connections, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

While the foregoing describes in detail a method, system and apparatus for improving uniformity of critical dimensions of etched patterns on a chip disclosed in the embodiments of the present invention, specific examples are set forth herein to illustrate the principles and embodiments of the present invention, and the above description is only for aiding in understanding the method and its core concept, and, as for those of ordinary skill in the art, variations in terms of the embodiments and application scope of the present invention will be apparent to those of ordinary skill in the art in light of the foregoing, and in light of the foregoing, the present invention should not be construed as limited to the embodiments described herein.

Claims

1. A method for improving the uniformity of the critical dimension of an etched pattern on a chip is characterized by comprising the following steps:

And etching the optimized pattern to obtain a final etched pattern.

2. The method for improving critical dimension uniformity of an etched pattern on a chip as set forth in claim 1, wherein first compensating the photoresist pattern by an etching bias table comprises:

3. The method for improving critical dimension uniformity of an etched pattern on a chip as set forth in claim 1, wherein obtaining a density profile of an initial etched pattern on the chip comprises:

dividing a chip into blocks;

acquiring the area of an initial etching pattern in a certain block;

4. The method for improving the uniformity of critical dimensions of an etched pattern on a chip as set forth in claim 3, further comprising, after obtaining the density profile of the initial etched pattern on the chip:

A preset first density variation value is set,

5. The method for improving the uniformity of critical dimensions of an etched pattern on a chip as set forth in claim 4, further comprising, after obtaining the density profile of the classification pattern:

a preset second density variation value is set,

if yes, setting the position as a local similar point;

and obtaining etching deviation values between actual etching patterns.

6. The method for improving the uniformity of critical dimensions of an etched pattern on a chip as set forth in claim 1, wherein the computing to obtain a corresponding etch bias pattern comprises:

7. The method for improving critical dimension uniformity of etched patterns on a chip as set forth in claim 1 wherein performing a second compensation on the target pattern based on the mapping relationship comprises:

the target pattern comprises a space and a line width;

Etching the target pattern to obtain a corresponding target etching pattern;

8. The method for improving critical dimension uniformity of etched patterns on a chip as set forth in claim 6, wherein etching the optimized patterns comprises:

judging whether etching deviation exists in the final etching pattern;

9. A system for improving the uniformity of critical dimensions of etched patterns on a chip is characterized by comprising:

And the output module is used for outputting the final etching pattern.

10. A computer device for improving the uniformity of the critical dimension of an etched pattern on a chip according to any one of claims 1 to 8, comprising a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to implement the method for improving the uniformity of the critical dimension of an etched pattern on a chip.