CN118315442B

CN118315442B - PIN diode with quasi-vertical structure and preparation method thereof

Info

Publication number: CN118315442B
Application number: CN202410467806.5A
Authority: CN
Inventors: 霍树栋; 高云云
Original assignee: Suzhou Mo'er Gallium Semiconductor Technology Co ltd
Current assignee: Suzhou Mo'er Gallium Semiconductor Technology Co ltd
Priority date: 2024-04-18
Filing date: 2024-04-18
Publication date: 2024-11-15
Anticipated expiration: 2044-04-18
Also published as: CN118315442A

Abstract

The invention relates to a PIN diode with a quasi-vertical structure and a preparation method thereof. The quasi-vertical structure PIN diode includes: a substrate; the P-type epitaxial layer based on gallium nitride is positioned on one side of the substrate; the intrinsic gallium nitride epitaxial layer is positioned on one side of the P-type epitaxial layer far away from the substrate; the N-type gallium nitride epitaxial layer is positioned on one side of the intrinsic gallium nitride epitaxial layer, which is far away from the substrate; the anode electrode is positioned on one side of the P-type epitaxial layer far away from the substrate; and a cathode electrode positioned on one side of the N-type gallium nitride epitaxial layer away from the substrate. The PIN diode is of an inverted structure, the P-type ohmic contact greatly influenced by the contact area is arranged under the table top, the series resistance can be greatly reduced compared with the traditional upright structure, and the current density is improved; and the hole diffusion and background carrier recombination at the interface of the P-type epitaxial layer and the intrinsic gallium nitride epitaxial layer realize compensation doping, the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, and the breakdown characteristic of the device is improved.

Description

PIN diode with quasi-vertical structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a PIN diode with a quasi-vertical structure and a preparation method thereof.

Background

The third-generation semiconductor has the remarkable characteristics of large forbidden bandwidth, high breakdown field strength and high carrier mobility, so that the LED device, the microwave device and the power electronic device prepared from the third-generation semiconductor material gallium nitride have great advantages. The current PIN diode is made of Si or GaAs, is limited by the material characteristics, has the working frequency, the withstand power and the response time reaching the limits and is difficult to further improve, and the high-power gallium nitride PIN diode is needed to be researched, so that the performance is greatly improved.

The conventional gallium nitride PIN diode adopts a P+ GaN layer heavily doped with Mg to have low carrier concentration and low activation rate, and the area of a mesa of an active area of the device and the area of an anode are extremely small due to the consideration of reducing the influence of the current edge collecting effect of the device, so that the ohmic contact resistance of the anode is large, the resistance of a P-type area is large, the series resistance of the gallium nitride PIN diode is large, and the forward current is reduced. In addition, the intrinsic layer of the traditional gallium nitride PIN diode is above the heavily doped N-type layer, and electrons of the N-type layer are easy to diffuse to the intrinsic layer due to the fact that significant carrier diffusion exists in the high-temperature epitaxial process, so that the carrier concentration of the intrinsic layer is increased, the breakdown voltage of the diode is reduced, meanwhile, the conductivity modulation of the device is significantly deteriorated due to the high-carrier concentration of the intrinsic layer, and the performance of the device is reduced.

Disclosure of Invention

Based on this, it is necessary to provide a PIN diode with a quasi-vertical structure and a method for manufacturing the PIN diode with a quasi-vertical structure aiming at the problem of how to improve the performance of the device.

A quasi-vertical structure PIN diode, the quasi-vertical structure PIN diode comprising:

A substrate;

a P-type epitaxial layer based on gallium nitride and positioned on one side of the substrate;

the intrinsic gallium nitride epitaxial layer is positioned on one side of the P-type epitaxial layer away from the substrate;

the N-type gallium nitride epitaxial layer is positioned on one side of the intrinsic gallium nitride epitaxial layer, which is far away from the substrate;

The anode electrode is positioned on one side of the P-type epitaxial layer away from the substrate; and

And the cathode electrode is positioned on one side of the N-type gallium nitride epitaxial layer, which is far away from the substrate.

According to the technical scheme, the PIN diode with the quasi-vertical structure is of an inverted structure, on one hand, the size of an electrode on a table top is smaller because of avoiding the current edge collecting effect, the table top of the inverted structure is provided with the N-type ohmic contact, the contact resistance is less influenced by the area, the P-type ohmic contact greatly influenced by the contact area is arranged under the table top, and the contact resistance is greatly reduced, so that the series resistance of the PIN diode with the quasi-vertical structure can be greatly reduced compared with that of the conventional upright structure, and the current density is improved; on the other hand, the interface of the P-type epitaxial layer and the intrinsic gallium nitride epitaxial layer is subjected to hole diffusion and background carrier recombination to realize compensation doping, and the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is usually small in thickness, short in high-temperature growth time and weak in electron diffusion, so that the inverted quasi-vertical structure PIN diode structure is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, the breakdown characteristic of a device is improved, better electric conduction modulation is realized, and the performance of the device is improved.

In one possible implementation, the P-type epitaxial layer is a P-type gallium nitride epitaxial layer.

In one possible implementation, the thickness of the P-type gallium nitride epitaxial layer is 10 nm-10 μm; the material of the P-type gallium nitride epitaxial layer is heavily doped gallium nitride, and the doping concentration is 1 multiplied by 10 ¹⁷cm^-3～1×10²¹cm^-3.

In one possible implementation, the P-type epitaxial layer includes a stacked barrier layer and a gallium nitride layer, the barrier layer being disposed proximate to the substrate, the barrier layer having a two-dimensional hole gas at an interface with the gallium nitride layer.

In one possible implementation, the barrier layer is selected from at least one of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer.

In one possible implementation manner, in the P-type epitaxial layer, the thickness of the barrier layer is 10 nm-1 μm, and the doping concentration of the barrier layer is 1×10 ¹⁷cm^-3～1×10²¹cm^-3;

In the P-type epitaxial layer, the thickness of the gallium nitride layer is 10 nm-500 nm, and the doping concentration of the gallium nitride layer is 1 multiplied by 10 ¹⁷cm^-3～1×10²¹cm^-3.

In one possible implementation, the thickness of the N-type gallium nitride epitaxial layer is 10 nm-10 μm; the material of the N-type gallium nitride epitaxial layer is heavily doped gallium nitride, and the doping concentration is 1 multiplied by 10 ¹⁶cm^-3～1×10²⁰cm^-3.

In one possible implementation, the intrinsic gallium nitride epitaxial layer has a thickness of 10nm to 100 μm; the intrinsic gallium nitride epitaxial layer is made of lightly doped gallium nitride, and the doping concentration is 1 multiplied by 10 ¹⁴cm^-3～1×10¹⁷cm^-3.

A preparation method of a PIN diode with a quasi-vertical structure comprises the following steps:

epitaxially growing a gallium nitride-based P-type epitaxial layer on the substrate;

epitaxially growing an intrinsic gallium nitride epitaxial layer on the P-type epitaxial layer;

epitaxially growing an N-type gallium nitride epitaxial layer on the intrinsic gallium nitride epitaxial layer;

etching the N-type gallium nitride epitaxial layer and the intrinsic gallium nitride epitaxial layer to form an electrode region on the P-type epitaxial layer; and

And forming an anode electrode in the electrode region of the P-type epitaxial layer, and forming a cathode electrode on the N-type gallium nitride epitaxial layer to obtain the PIN diode with the quasi-vertical structure.

According to the preparation method of the PIN diode with the quasi-vertical structure, which is disclosed by the technical scheme of the invention, the PIN diode with the quasi-vertical structure of gallium nitride can be prepared, on one hand, the quasi-vertical structure PIN diode is required to avoid the current edge collecting effect, the size of an electrode on a table top is smaller, the table top of the inverted structure is provided with N-type ohmic contact, the contact resistance is less influenced by the area, and the P-type ohmic contact with large influence of the contact area is arranged under the table top, so that the contact resistance is greatly reduced, and the series resistance of the PIN diode with the quasi-vertical structure is greatly reduced compared with that of the conventional upright structure, and the current density is improved; on the other hand, the interface of the P-type epitaxial layer and the intrinsic gallium nitride epitaxial layer is subjected to hole diffusion and background carrier recombination to realize compensation doping, and the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is usually small in thickness, short in high-temperature growth time and weak in electron diffusion, so that the inverted quasi-vertical structure PIN diode structure is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, the breakdown characteristic of a device is improved, better electric conduction modulation is realized, and the performance of the device is improved.

In one possible implementation, the epitaxial growth method is an MOCVD method, the temperature is 600-1300 ℃, and the chamber pressure is 10 Torr-200 Torr;

The epitaxial growth method is an MBE method, and the process conditions are as follows: the temperature is 550-700 ℃, the gallium beam current is 5.0X10 ^-7Torr～7.5×10^-7 Torr, and the nitrogen beam current is 0.5 sccm-2.5 sccm.

Drawings

Fig. 1 is a schematic diagram of a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention;

fig. 2 is a flowchart of a method for manufacturing a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention;

fig. 3 is a schematic diagram of a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention after epitaxially growing a barrier layer in the process of manufacturing the PIN diode;

fig. 4 is a schematic diagram of a process for preparing a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention after epitaxially growing a gallium nitride layer;

fig. 5 is a schematic diagram of a process for preparing a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention after epitaxially growing an intrinsic gallium nitride epitaxial layer;

fig. 6 is a schematic diagram of a process for preparing a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention after epitaxially growing an N-type gallium nitride epitaxial layer;

Fig. 7 is a schematic diagram of a PIN diode with a quasi-vertical structure according to a first embodiment of the present invention after etching an electrode region in the process of manufacturing the PIN diode;

FIG. 8 is a schematic diagram of a PIN diode with a quasi-vertical structure according to a second embodiment of the invention;

Fig. 9 is a flowchart of a method for manufacturing a PIN diode with a quasi-vertical structure according to a second embodiment of the present invention;

Fig. 10 is a schematic diagram of a P-type gallium nitride epitaxial layer epitaxially grown during the fabrication of a PIN diode with a quasi-vertical structure according to a second embodiment of the present invention;

fig. 11 is a schematic diagram of a second embodiment of the present invention after epitaxial growth of an intrinsic gan epitaxial layer during fabrication of a quasi-vertical structure PIN diode;

fig. 12 is a schematic diagram of a second embodiment of the present invention after epitaxially growing an N-type gallium nitride epitaxial layer during the fabrication of a PIN diode with a quasi-vertical structure;

Fig. 13 is a schematic diagram of a PIN diode with a quasi-vertical structure according to a second embodiment of the present invention after etching an electrode region.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.

It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

Conventional gan quasi-vertical PIN diodes are usually in a forward structure, because the intrinsic material of gan is N-type material, and doping to form a P-type layer on gan by a compensation method is of course. However, for a quasi-vertical structure PIN diode with a forward structure, due to significant carrier diffusion during high-temperature epitaxy, N-type layer electrons are easy to diffuse to an intrinsic layer, which leads to an increase in the carrier concentration of the intrinsic layer, a decrease in the breakdown voltage of the diode, and a significant deterioration in the conductivity modulation of the device due to the high carrier concentration of the intrinsic layer, which leads to a decrease in the device performance. Meanwhile, the current edge collecting effect is provided, so that the performance of the device is improved, the table top is required to be small, the area of a contact electrode on the table top is small, the table top of the conventional PIN diode with the gallium nitride quasi-vertical structure is in P-type ohmic contact, and the resistance of a P-type region is relatively large, so that the area of the P-type region is small, and the low resistance is more difficult to be realized.

Therefore, the invention creatively provides a PIN diode with an inverted structure, which comprises a substrate, a P-type epitaxial layer based on gallium nitride, an intrinsic gallium nitride epitaxial layer, an N-type gallium nitride epitaxial layer, an anode electrode and a cathode electrode. The P-type epitaxial layer based on gallium nitride at least comprises a gallium nitride epitaxial layer, and the P-type epitaxial layer is positioned on one side of the substrate; the intrinsic gallium nitride epitaxial layer is positioned on one side of the P-type epitaxial layer far away from the substrate; the N-type gallium nitride epitaxial layer is positioned on one side of the intrinsic gallium nitride epitaxial layer far away from the substrate; the anode electrode is positioned on one side of the P-type epitaxial layer far away from the substrate; the cathode electrode is positioned on one side of the N-type gallium nitride epitaxial layer far away from the substrate.

The principle of realizing compensation doping by hole diffusion and background carrier recombination at the interface of the P-type epitaxial layer and the intrinsic gallium nitride epitaxial layer is as follows: for gallium nitride, the intrinsic gallium nitride epitaxial layer is a light N-type layer, in a positive structure, an N-type gallium nitride epitaxial layer is formed firstly, then an intrinsic gallium nitride epitaxial layer is formed on the N-type gallium nitride epitaxial layer, N doping in the N-type gallium nitride epitaxial layer can permeate into the intrinsic gallium nitride epitaxial layer in the process, and therefore N carrier concentration in the intrinsic gallium nitride epitaxial layer is too high; the PIN diode with the quasi-vertical structure is of an inverted structure, a P-type gallium nitride epitaxial layer is formed firstly, then an intrinsic gallium nitride epitaxial layer is formed on the P-type gallium nitride epitaxial layer, P carriers in the P-type gallium nitride epitaxial layer penetrate into the intrinsic gallium nitride epitaxial layer in the process and are compounded with N carriers in the intrinsic gallium nitride epitaxial layer, N carrier concentration in the intrinsic gallium nitride epitaxial layer is reduced, and therefore compensation doping is achieved.

Referring to fig. 1, a quasi-vertical PIN diode 100 according to a first embodiment of the present invention includes a substrate 110, a P-type epitaxial layer 120 based on gallium nitride, an intrinsic gallium nitride epitaxial layer 130, an N-type gallium nitride epitaxial layer 140, an anode electrode 150 and a cathode electrode 160. The P-type epitaxial layer 120 based on gallium nitride refers to that the P-type epitaxial layer 120 at least includes a gallium nitride epitaxial layer.

The quasi-vertical structure PIN diode 100 of the present embodiment is a gallium nitride inverted quasi-vertical structure PIN diode of a quasi-vertical structure, wherein the P-type epitaxial layer 120 is located on one side of the substrate 110, the P-type epitaxial layer 120 includes a stacked barrier layer 121 and a gallium nitride layer 122, the barrier layer 121 is disposed close to the substrate 110, and a two-dimensional hole gas (2 dhg, two-dimensional hole gas) is provided at a heterojunction interface between the barrier layer 121 and the gallium nitride layer 122. The resistance of the P-type epitaxial layer 120 can be further reduced by the two-dimensional hole gas.

The intrinsic gallium nitride epitaxial layer 130 is located on a side of the P-type epitaxial layer 120 away from the substrate 110, the N-type gallium nitride epitaxial layer 140 is located on a side of the intrinsic gallium nitride epitaxial layer 130 away from the substrate 110, the anode electrode 150 is located on a side of the P-type epitaxial layer 140 away from the substrate 110, and the cathode electrode 160 is located on a side of the N-type gallium nitride epitaxial layer 140 away from the substrate 110.

In addition to the foregoing embodiments, the barrier layer 121 is at least one selected from the group consisting of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer. The barrier layer 121 may be an aluminum nitride barrier layer, an aluminum gallium nitride barrier layer, or a composite layer of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer. When the barrier layer 121 is a composite layer of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer, the positions of the aluminum nitride barrier layer and the aluminum gallium nitride barrier layer are not limited, and for example, the aluminum nitride barrier layer may be located between the aluminum gallium nitride barrier layer and the gallium nitride layer 122, or the aluminum gallium nitride barrier layer may be located between the aluminum nitride barrier layer and the gallium nitride layer 122.

In the P-type epitaxial layer 120 according to the above embodiment, the thickness of the barrier layer 121 is 10nm to 1 μm, and the doping concentration of the barrier layer 121 is 1×10 ¹⁷cm^-3～1×10²¹cm^-3. Wherein, the doping element can be Mg. The thickness of the barrier layer 121 may be, but not limited to, 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, or 1 μm, and the doping concentration may be, but not limited to, 1×10 ¹⁷cm^-3、1×10¹⁸cm^-3、1×10¹⁹cm^-3、1×10²⁰cm^-3 or 1×10 ²¹cm^-3.

In the P-type epitaxial layer 120, the thickness of the gallium nitride layer 122 is 10nm to 500nm, and the doping concentration of the gallium nitride layer 122 is 1×10 ¹⁷cm^-3～1×10²¹cm^-3. Wherein, the doping element can be Mg. The thickness of the gallium nitride layer 122 may be, but is not limited to, 10nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm, and the doping concentration may be, but is not limited to, 1×10 ¹⁷cm^-3、1×10¹⁸cm^-3、1×10¹⁹cm^-3、1×10²⁰cm^-3 or 1×10 ²¹cm^-3. In the present embodiment, the thickness of the gallium nitride layer 122 is 10nm to 500nm, and it is possible to avoid the performance disadvantage caused by the fact that the two-dimensional hole gas at the interface between the gallium nitride layer 122 and the barrier layer 121 is too far from the intrinsic gallium nitride epitaxial layer 130.

In the PIN diode 100 with the quasi-vertical structure in this embodiment, the P-type epitaxial layer 120 is a heterojunction of a barrier layer and a gallium nitride layer, and due to the polarization effect, two-dimensional hole gas with high carrier surface density and high mobility exists at the heterojunction interface, and meanwhile, the P-type epitaxial layer 120 adopts high-concentration doping, so that the hole concentration can be further improved, and the resistance of the P-type epitaxial layer can be further reduced.

On the basis of the foregoing embodiment, the thickness of the N-type gallium nitride epitaxial layer 140 is 10nm to 10 μm; the material of the N-type gan epitaxial layer 140 is heavily doped gan with a doping concentration of 1×10 ¹⁶cm^-3～1×10²⁰cm^-3. Wherein the doping element may be Si. Wherein the thickness of the N-type gallium nitride epitaxial layer 140 may be, but is not limited to, 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1 μm, 2 μm, 3 μm, 4 μm,5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, and the doping concentration may be, but is not limited to, 1×10 ¹⁶cm^-3、1×10¹⁷cm^-3、1×10¹⁸cm^-3、1×10¹⁹cm^-3 or 1×10 ²⁰cm^-3.

Based on the previous embodiments, the intrinsic gallium nitride epitaxial layer 130 has a thickness of 10nm to 100 μm; the intrinsic gallium nitride epitaxial layer 130 is made of lightly doped gallium nitride with a doping concentration of 1×10 ¹⁴cm^-3～1×10¹⁷cm^-3. Wherein the doping element can be Si or Mg. The thickness of the intrinsic gallium nitride epitaxial layer 130 may be, but not limited to 10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1μm、10μm、20μm、30μm、40μm、50μm、60μm、70μm、80μm、90μm or 100 μm, and the doping concentration may be, but not limited to, 1×10 ¹⁴cm^-3、1×10¹⁵cm^-3、1×10¹⁶cm^-3 or 1×10 ¹⁷cm^-3.

In the above embodiment, the substrate 110 is made of at least one material selected from Si, siC, sapphire, and GaN. Further, the thickness of the substrate 110 is 50 μm to 1000 μm.

Based on the foregoing embodiment, the anode electrode 150 is a Ni/Au metal layer, wherein the Ni metal layer is disposed close to the substrate 110 and the Au metal layer is disposed away from the substrate 110. The thickness of the Ni/Au metal layer may be (5 to 200) nm/(5 to 200) nm, with 10nm/15nm being preferred. The anode electrode 150 of such a material enables contact with a lower resistance. Of course, the anode electrode 150 is not limited thereto, and may be other possible electrodes. Further, the area of the anode electrode 150 is not limited, and may be designed according to the need.

The cathode electrode 160 is a Ti/Al/Ni/Au metal layer having a thickness of 20nm/120nm/40nm/50nm based on the foregoing embodiment. The cathode electrode 160 of such a material enables a contact with a lower resistance.

It should be noted that, the anode electrode and the cathode electrode in the gallium nitride inverted quasi-vertical structure PIN diode of the present invention are not limited to this, and may be any feasible materials and thicknesses.

According to the technical scheme, the PIN diode with the quasi-vertical structure is of an inverted structure, and due to the polarization effect, two-dimensional hole gas with high carrier surface density and high mobility exists at the heterojunction interface of the P-type epitaxial layer, so that the resistance of the P-type epitaxial layer is reduced; the PIN diode with the quasi-vertical structure has the advantages that the size of an electrode on the table top is smaller because of avoiding the current edge collecting effect, the table top with the inverted structure is provided with the N-type ohmic contact, the contact resistance is less influenced by the area, and the P-type ohmic contact greatly influenced by the contact area is arranged under the table top, so that the contact resistance is greatly reduced, and compared with the traditional upright structure, the series resistance of the PIN diode with the quasi-vertical structure can be greatly reduced, and the current density is improved; the interface of the P-type epitaxial layer and the intrinsic gallium nitride epitaxial layer is subjected to hole diffusion and background carrier recombination to realize compensation doping, and the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is usually small in thickness, short in high-temperature growth time and weak in electron diffusion, so that the inverted PIN structure is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, the breakdown characteristic of a device is improved, better conductivity modulation is realized, and the performance of the device is improved.

Referring to fig. 2 to 7, the method for manufacturing a PIN diode with a quasi-vertical structure according to the first embodiment of the present invention includes the following steps:

and S10, epitaxially growing a P-type epitaxial layer 120 based on gallium nitride on the substrate 110.

In step S10, the P-type epitaxial layer 120 based on gallium nitride includes a barrier layer 121 and a gallium nitride layer 122 stacked, the barrier layer 121 being disposed close to the substrate 110, and a two-dimensional hole gas being present at a heterojunction interface of the barrier layer 121 and the gallium nitride layer 122.

In step S10, the operation of epitaxially growing the P-type epitaxial layer 120 based on gallium nitride on the substrate 110 is as follows: first epitaxially growing a barrier layer 121 on a substrate 110, as shown in fig. 3; a gallium nitride layer 122 is then epitaxially grown on the barrier layer 121, thereby forming a P-type epitaxial layer 120, as shown in fig. 4.

In one possible implementation, the barrier layer 121 is selected from at least one of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer. The barrier layer 121 may be an aluminum nitride barrier layer, an aluminum gallium nitride barrier layer, or a composite layer of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer. When the barrier layer 121 is a composite layer of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer, the positions of the aluminum nitride barrier layer and the aluminum gallium nitride barrier layer are not limited, and for example, the aluminum nitride barrier layer may be located between the aluminum gallium nitride barrier layer and the gallium nitride layer 122, or the aluminum gallium nitride barrier layer may be located between the aluminum nitride barrier layer and the gallium nitride layer 122.

In one possible implementation, in the P-type epitaxial layer 120, the thickness of the barrier layer 121 is 10nm to 1 μm, and the doping concentration of the barrier layer 121 is 1×10 ¹⁷cm^-3～1×10²¹cm^-3; in the P-type epitaxial layer 120, the thickness of the gallium nitride layer 122 is 10nm to 500nm, and the doping concentration of the gallium nitride layer 122 is 1×10 ¹⁷cm^-3～1×10²¹cm^-3.

In one possible implementation, the epitaxial growth method is an MOCVD method, that is, a layer of barrier layer 121 and a layer of gallium nitride layer 122 are epitaxially grown on the substrate 110 as the P-type epitaxial layer 120 by using the MOCVD method; wherein the epitaxial growth temperature is 600-1300 ℃, and the chamber pressure is 10-200 Torr.

In one possible implementation, the epitaxial growth method is an MBE method, and the process conditions are: the temperature is 550-700 ℃, the gallium beam current is 5.0X10 ^-7Torr～7.5×10^-7 Torr, and the nitrogen beam current is 0.5 sccm-2.5 sccm.

In step S10, the P-type epitaxial layer 120 is epitaxially grown on the substrate 110, so that the thickness and carrier concentration of the P-type epitaxial layer 120 can be designed more flexibly, the growth quality of the P-type epitaxial layer 120 is high, and the activation rate and carrier concentration are higher.

And S20, epitaxially growing an intrinsic gallium nitride epitaxial layer 130 on the P-type epitaxial layer 120 obtained in the step S10.

In one possible implementation, the intrinsic gallium nitride epitaxial layer 130 has a thickness of 10nm to 100 μm; the intrinsic gan epitaxial layer 130 is made of heavily doped gan with a doping concentration of 1 x 10 ¹⁴cm^-3～1×10¹⁷cm^-3.

In one possible implementation, the epitaxial growth method is an MOCVD method, that is, a GaN layer is epitaxially grown on the P-type epitaxial layer 120 obtained in step S10 by using the MOCVD method to serve as the intrinsic GaN epitaxial layer 130, as shown in fig. 5; wherein the epitaxial growth temperature is 600-1300 ℃, and the chamber pressure is 10-200 Torr.

And S30, epitaxially growing an N-type gallium nitride epitaxial layer 140 on the intrinsic gallium nitride epitaxial layer 130 obtained in the step S20.

In one possible implementation, the thickness of the N-type gallium nitride epitaxial layer 140 is 10nm to 10 μm; the material of the N-type gan epitaxial layer 140 is heavily doped gan with a doping concentration of 1×10 ¹⁶cm^-3～1×10²⁰cm^-3.

In one possible implementation, the epitaxial growth method is an MOCVD method, that is, a GaN layer is epitaxially grown on the intrinsic GaN epitaxial layer 130 obtained in step S20 by using the MOCVD method to serve as the N-type GaN epitaxial layer 140, as shown in fig. 6; wherein the epitaxial growth temperature is 600-1300 ℃, and the chamber pressure is 10-200 Torr.

And S40, etching the N-type gallium nitride epitaxial layer 140 and the intrinsic gallium nitride epitaxial layer 130 obtained in the step S30 to form an electrode region on the P-type epitaxial layer 120.

Specifically, the N-type gallium nitride epitaxial layer 140 and the intrinsic gallium nitride epitaxial layer 130 obtained in step S30 are etched by using an etching process, and an electrode region is formed on the P-type epitaxial layer 120 after the etching, as shown in fig. 7.

And S50, forming an anode electrode 150 in the electrode region of the P-type epitaxial layer 120 obtained in the step S40, and forming a cathode electrode 160 on the N-type gallium nitride epitaxial layer 140 to obtain the PIN diode 100 with the quasi-vertical structure.

In step S50, the anode electrode 150 is fabricated by vapor deposition and photolithography in the electrode region of the P-type epitaxial layer 120 obtained in step S40, and the area of the anode electrode 150 is not limited and may be designed according to the requirements.

In step S50, a cathode electrode 160 is fabricated by vapor deposition and photolithography on the N-type gallium nitride epitaxial layer 140.

In step S50, the device fabrication is completed after the anode electrode 150 and the cathode electrode 160 are formed, and the PIN diode 100 with a quasi-vertical structure is obtained, as shown in fig. 1.

By applying the preparation method of the PIN diode with the quasi-vertical structure, which is disclosed by the invention, the PIN diode with the quasi-vertical structure of gallium nitride with an inverted structure can be prepared, and due to the polarization effect, two-dimensional hole gas with high carrier surface density and high mobility exists at the heterojunction interface of the P-type epitaxial layer, so that the resistance of the P-type epitaxial layer is reduced; the PIN diode with the quasi-vertical structure has the advantages that the size of an electrode on the table top is smaller because of avoiding the current edge collecting effect, the table top with the inverted structure is provided with the N-type ohmic contact, the contact resistance is less influenced by the area, and the P-type ohmic contact greatly influenced by the contact area is arranged under the table top, so that the contact resistance is greatly reduced, and compared with the traditional upright structure, the series resistance of the PIN diode with the quasi-vertical structure can be greatly reduced, and the current density is improved; the interface of the P-type epitaxial layer and the intrinsic gallium nitride epitaxial layer is subjected to hole diffusion and background carrier recombination to realize compensation doping, the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is usually small in thickness, short in high-temperature growth time and weak in electron diffusion, so that the inverted PIN structure is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, the breakdown characteristic of a device is improved, and better electric conduction modulation is realized.

Referring to fig. 8, a quasi-vertical PIN diode 100 according to a second embodiment of the present invention includes a substrate 110, a P-type gan epitaxial layer 120, an intrinsic gan epitaxial layer 130, an N-type gan epitaxial layer 140, an anode electrode 150 and a cathode electrode 160.

The quasi-vertical structure PIN diode 100 of the present embodiment is a gallium nitride inverted quasi-vertical structure PIN diode with a quasi-vertical structure, wherein the P-type gallium nitride epitaxial layer 120 is located on one side of the substrate 110, the intrinsic gallium nitride epitaxial layer 130 is located on one side of the P-type gallium nitride epitaxial layer 120 away from the substrate 110, the N-type gallium nitride epitaxial layer 140 is located on one side of the intrinsic gallium nitride epitaxial layer 130 away from the substrate 110, the anode electrode 150 is located on one side of the P-type gallium nitride epitaxial layer 140 away from the substrate 110, and the cathode electrode 160 is located on one side of the N-type gallium nitride epitaxial layer 140 away from the substrate 110.

Based on the previous embodiment, the thickness of the P-type gallium nitride epitaxial layer 120 is 10nm to 10 μm; the P-type gan epitaxial layer 120 is made of heavily doped gan with a doping concentration of 1×10 ¹⁷cm^-3～1×10²¹cm^-3. The doping element may be Mg. The thickness of the P-type gallium nitride epitaxial layer 120 may be, but is not limited to, 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, and the doping concentration may be, but is not limited to, 1×10 ¹⁷cm^-3、1×10¹⁸cm^-3、1×10¹⁹cm^-3、1×10²⁰cm^-3 or 1×10 ²¹cm^-3.

Based on the previous embodiments, the intrinsic gallium nitride epitaxial layer 130 has a thickness of 10nm to 100 μm; the intrinsic gallium nitride epitaxial layer 130 is made of lightly doped gallium nitride with a doping concentration of 1×10 ¹⁴cm^-3～1×10¹⁷cm^-3. The doping element may be Si or Mg. The thickness of the intrinsic gallium nitride epitaxial layer 130 may be, but not limited to 10nm、100nm、200nm、300nm、400nm、500nm、600nm、700nm、800nm、900nm、1μm、10μm、20μm、30μm、40μm、50μm、60μm、70μm、80μm、90μm or 100 μm, and the doping concentration may be, but not limited to, 1×10 ¹⁴cm^-3、1×10¹⁵cm^-3、1×10¹⁶cm^-3 or 1×10 ¹⁷cm^-3.

On the basis of the foregoing embodiment, the thickness of the N-type gallium nitride epitaxial layer 140 is 10nm to 10 μm; the material of the N-type gan epitaxial layer 140 is heavily doped gan with a doping concentration of 1×10 ¹⁶cm^-3～1×10²⁰cm^-3. The doping element may be Si. Wherein the thickness of the N-type gallium nitride epitaxial layer 140 may be, but is not limited to, 10nm, 100nm, 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, and the doping concentration may be, but is not limited to, 1×10 ¹⁶cm^-3、1×10¹⁷cm^-3、1×10¹⁸cm^-3、1×10¹⁹cm^-3 or 1×10 ²⁰cm^-3.

In addition to the above embodiments, the thickness of the P-type gallium nitride epitaxial layer 120 is 500nm to 10 μm, and the thickness of the N-type gallium nitride epitaxial layer 140 is 10nm to 1 μm. In the conventional PIN diode with the positive gallium nitride quasi-vertical structure, the thickness of the P-type gallium nitride epitaxial layer is smaller, the contact resistance is larger, and meanwhile, the resistance of the P-type gallium nitride epitaxial layer is larger, so that the resistance of the whole device is larger. In this embodiment, the P-type gan epitaxial layer 120 is under the intrinsic gan epitaxial layer 130, and can grow thicker during epitaxial growth, specifically, the thickness is 500 nm-10 μm, the doping concentration can be higher, and the contact area can be larger, so that the contact resistance and the self resistance of the P-type gan epitaxial layer 120 can be reduced; meanwhile, the N-type gan epitaxial layer 140 is more easily grown on the intrinsic gan epitaxial layer 130, so that the thickness of the N-type gan epitaxial layer 140 in this embodiment is 10 nm-1 μm, which can avoid performance degradation caused by relatively large resistance of the P-type gan epitaxial layer 120.

Based on the foregoing embodiment, the anode electrode 150 is a Ni/Au metal layer, wherein the Ni metal layer is disposed close to the substrate 110 and the Au metal layer is disposed away from the substrate 110. The thickness of the Ni/Au metal layer may be (5 to 200) nm/(5 to 200) nm, with 10nm/15nm being preferred. The anode electrode 150 of such a material enables contact with a lower resistance. Further, the area of the anode electrode 150 is not limited, and may be designed according to the need.

According to the gallium nitride inverted quasi-vertical structure PIN diode, on one hand, the quasi-vertical structure PIN diode is smaller in size of an electrode on a table top due to the fact that current edge collecting effect is avoided, on the other hand, the table top of the inverted structure is provided with N-type ohmic contact, the contact resistance is less influenced by the area, the P-type ohmic contact greatly influenced by the contact area is arranged below the table top, and the contact resistance is greatly reduced, so that the series resistance of the quasi-vertical structure PIN diode is greatly reduced compared with that of a traditional upright structure, and the current density is improved; on the other hand, the interface of the P-type gallium nitride epitaxial layer and the intrinsic gallium nitride epitaxial layer is subjected to hole diffusion and background carrier recombination to realize compensation doping, and the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is usually small in thickness, short in high-temperature growth time and weak in electron diffusion, so that the inverted quasi-vertical structure PIN diode structure is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, the breakdown characteristic of a device is improved, better electric conduction modulation is realized, and the performance of the device is improved.

Referring to fig. 9 to 13, a method for manufacturing a PIN diode with a quasi-vertical structure according to a second embodiment of the present invention includes the following steps:

and S10, epitaxially growing a P-type gallium nitride epitaxial layer 120 on the substrate 110.

In one possible implementation, the thickness of the P-type gallium nitride epitaxial layer 120 is 10nm to 10 μm; the P-type gan epitaxial layer 120 is made of heavily doped gan with a doping concentration of 1×10 ¹⁷cm^-3～1×10²¹cm^-3.

In addition to the above embodiments, the thickness of the P-type gallium nitride epitaxial layer 120 is 500nm to 10 μm. In the conventional PIN diode with the positive gallium nitride quasi-vertical structure, the thickness of the P-type gallium nitride epitaxial layer is smaller, the contact resistance is larger, and meanwhile, the resistance of the P-type gallium nitride epitaxial layer is larger, so that the resistance of the whole device is larger. In this embodiment, the P-type gan epitaxial layer 120 is under the intrinsic gan epitaxial layer 130, and may be grown thicker during epitaxial growth, specifically, the thickness is 500 nm-10 μm, the doping concentration may be higher, and the contact area may be larger, so that the contact resistance and the self resistance of the P-type gan epitaxial layer 120 may be reduced.

In one possible implementation, the epitaxial growth method is an MOCVD method, that is, a GaN layer is epitaxially grown on the substrate 110 by using the MOCVD method as the P-type gallium nitride epitaxial layer 120, as shown in fig. 10; wherein the epitaxial growth temperature is 600-1300 ℃, and the chamber pressure is 10-200 Torr.

In step S10, the P-type gallium nitride epitaxial layer 120 is epitaxially grown on the substrate 110, so that the thickness and carrier concentration of the P-type gallium nitride epitaxial layer 120 can be designed more flexibly, and the growth quality of the P-type gallium nitride epitaxial layer 120 is high, and the activation rate and carrier concentration are higher.

And S20, epitaxially growing an intrinsic gallium nitride epitaxial layer 130 on the P-type gallium nitride epitaxial layer 120 obtained in the step S10.

In one possible implementation, the epitaxial growth method is an MOCVD method, that is, a GaN layer is epitaxially grown on the P-type GaN epitaxial layer 120 obtained in step S10 by using the MOCVD method to serve as the intrinsic GaN epitaxial layer 130, as shown in fig. 11; wherein the epitaxial growth temperature is 600-1300 ℃, and the chamber pressure is 10-200 Torr.

In addition to the above embodiments, the thickness of the N-type gallium nitride epitaxial layer 140 is 10nm to 1 μm. The N-type gan epitaxial layer 140 is more easily grown on the intrinsic gan epitaxial layer 130, so that the thickness of the N-type gan epitaxial layer 140 in the present embodiment is 10 nm-1 μm, which can avoid performance degradation caused by relatively large resistance of the P-type gan epitaxial layer 120.

In one possible implementation, the epitaxial growth method is an MOCVD method, that is, a GaN layer is epitaxially grown on the intrinsic GaN epitaxial layer 130 obtained in step S20 by using the MOCVD method to serve as the N-type GaN epitaxial layer 140, as shown in fig. 12; wherein the epitaxial growth temperature is 600-1300 ℃, and the chamber pressure is 10-200 Torr.

And S40, etching the N-type gallium nitride epitaxial layer 140 and the intrinsic gallium nitride epitaxial layer 130 obtained in the step S30 to form an electrode region on the P-type gallium nitride epitaxial layer 120.

Specifically, the N-type gallium nitride epitaxial layer 140 and the intrinsic gallium nitride epitaxial layer 130 obtained in step S30 are etched by using an etching process, and an electrode region is formed on the P-type gallium nitride epitaxial layer 120 after etching, as shown in fig. 13.

And S50, forming an anode electrode 150 in the electrode region of the P-type gallium nitride epitaxial layer 120 obtained in the step S40, and forming a cathode electrode 160 on the N-type gallium nitride epitaxial layer 140 to obtain the PIN diode 100 with the quasi-vertical structure.

In step S50, the anode electrode 150 is fabricated by vapor deposition and photolithography in the electrode region of the P-type gallium nitride epitaxial layer 120 obtained in step S40, and the area of the anode electrode 150 is not limited and may be designed according to the requirements.

In step S50, the device fabrication is completed after the anode electrode 150 and the cathode electrode 160 are formed, and the PIN diode 100 with a quasi-vertical structure is obtained, as shown in fig. 8.

By applying the preparation method of the PIN diode with the quasi-vertical structure, on one hand, the size of an electrode on a table top is smaller because of avoiding the current edge collecting effect, and the N-type ohmic contact is arranged on the table top with the inverted structure, the contact resistance is less influenced by the area, the P-type ohmic contact with the large influence of the contact area is arranged under the table top, and the contact resistance is greatly reduced, so that the series resistance of the PIN diode with the quasi-vertical structure can be greatly reduced compared with the traditional upright structure, and the current density is improved; on the other hand, the intrinsic gallium nitride epitaxial layer grows on the P-type gallium nitride epitaxial layer, compensation doping can be realized by compounding hole diffusion and background carriers at the interface of the P-type gallium nitride epitaxial layer and the intrinsic gallium nitride epitaxial layer, and the N-type gallium nitride epitaxial layer grown on the intrinsic gallium nitride epitaxial layer is smaller in thickness, short in high-temperature growth time and weak in electron diffusion, so that the inverted quasi-vertical structure PIN diode structure is easier to grow the intrinsic gallium nitride epitaxial layer with low doping concentration, the breakdown characteristic of a device is improved, and better electric conduction modulation is realized.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims

1. A quasi-vertical PIN diode, characterized in that the quasi-vertical PIN diode comprises:

substrate;

A P-type epitaxial layer based on gallium nitride, located on one side of the substrate;

An intrinsic gallium nitride epitaxial layer, located on a side of the P-type epitaxial layer away from the substrate;

An N-type gallium nitride epitaxial layer, located on a side of the intrinsic gallium nitride epitaxial layer away from the substrate;

an anode electrode, located on a side of the P-type epitaxial layer away from the substrate; and

A cathode electrode, located on a side of the N-type gallium nitride epitaxial layer away from the substrate;

The P-type epitaxial layer includes a stacked barrier layer and a gallium nitride layer, the barrier layer is arranged close to the substrate, and a two-dimensional hole gas is present at the interface between the barrier layer and the gallium nitride layer.

2 . The quasi-vertical structure PIN diode according to claim 1 , wherein the barrier layer is selected from at least one of an aluminum nitride barrier layer and an aluminum gallium nitride barrier layer. 3 .

3 . The quasi-vertical PIN diode according to claim 1 , wherein in the P-type epitaxial layer, the barrier layer has a thickness of 10 nm to 1 μm, and a doping concentration of the barrier layer is 1×10 ¹⁷ cm ⁻³ to 1×10 ²¹ cm ⁻³ .

4 . The quasi-vertical PIN diode according to claim 1 , wherein in the P-type epitaxial layer, the gallium nitride layer has a thickness of 10 nm to 500 nm, and a doping concentration of the gallium nitride layer is 1×10 ¹⁷ cm ⁻³ to 1×10 ²¹ cm ⁻³ .

5 . The quasi-vertical PIN diode according to claim 1 , wherein the thickness of the N-type GaN epitaxial layer is 10 nm to 10 μm; the material of the N-type GaN epitaxial layer is heavily doped GaN with a doping concentration of 1×10 ¹⁶ cm ⁻³ to 1×10 ²⁰ cm ⁻³ .

6 . The quasi-vertical PIN diode according to claim 1 , wherein the thickness of the intrinsic gallium nitride epitaxial layer is 10 nm to 100 μm; the material of the intrinsic gallium nitride epitaxial layer is lightly doped gallium nitride with a doping concentration of 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁷ cm ⁻³ .

7. A method for preparing a quasi-vertical PIN diode according to any one of claims 1 to 6, characterized in that it comprises the following steps:

Epitaxially growing a P-type epitaxial layer based on gallium nitride on a substrate, wherein the P-type epitaxial layer comprises a stacked barrier layer and a gallium nitride layer, wherein the barrier layer is arranged close to the substrate, and a two-dimensional hole gas is present at an interface between the barrier layer and the gallium nitride layer;

An anode electrode is formed in the electrode region of the P-type epitaxial layer, and a cathode electrode is formed on the N-type gallium nitride epitaxial layer to obtain a quasi-vertical structure PIN diode.

8. The method for preparing a quasi-vertical PIN diode according to claim 7, characterized in that the epitaxial growth method is a MOCVD method, the temperature is 600 degrees to 1300 degrees, and the chamber pressure is 10 Torr to 200 Torr; or

The epitaxial growth method is an MBE method, and the process conditions are: a temperature of 550 degrees to 700 degrees, a gallium beam current of 5.0×10 ^-7 Torr to 7.5×10 ^-7 Torr, and a nitrogen beam current of 0.5 sccm to 2.5 sccm.