CN118249806B - Low-jitter injection locking phase-locked loop based on multiphase injection and correction - Google Patents
Low-jitter injection locking phase-locked loop based on multiphase injection and correction Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
本发明属于数模混合集成电路设计技术领域，具体公开了一种基于多相位注入及校正的低抖动注入锁定锁相环，包括：多相信号发生器、多相自校正电路、注入锁定振荡器、鉴频鉴相器、电荷泵、低通滤波器和第一分频器。本发明采用多相信号发生器产生多相注入信号，经多相自校正电路校正后注入注入锁定振荡器中，与传统只有单相注入的注入锁定锁相环相比提升了注入信号强度，从而极大地降低了时钟抖动。
The present invention belongs to the technical field of digital-analog hybrid integrated circuit design, and specifically discloses a low-jitter injection-locked phase-locked loop based on multi-phase injection and correction, comprising: a multi-phase signal generator, a multi-phase self-correction circuit, an injection-locked oscillator, a frequency detector, a charge pump, a low-pass filter, and a first frequency divider. The present invention adopts a multi-phase signal generator to generate a multi-phase injection signal, which is injected into an injection-locked oscillator after correction by a multi-phase self-correction circuit, thereby improving the injection signal strength compared to a traditional injection-locked phase-locked loop with only single-phase injection, thereby greatly reducing clock jitter.
Description
Technical Field
The invention belongs to the technical field of digital-analog hybrid integrated circuit design, and particularly relates to a low-jitter injection locking phase-locked loop based on multiphase injection and correction.
Background
Phase-locked loop circuits play a vital role in integrated circuits as clock generation circuits. Conventional phase locked loops typically employ reduced loop bandwidth to suppress in-band noise from the phase frequency detector and charge pump, but this increases out-of-band phase noise and leads to problems of extended lock time and increased chip area. In contrast, injection locked phase locked loops can suppress both in-band and out-of-band phase noise by injecting a low jitter signal into the oscillator with little additional cost.
The conventional injection locking phase-locked loop often adopts a single-phase injection signal, so that the intensity of the injection signal is limited, and further improvement of jitter performance is limited, so that the injection locking phase-locked loop has a large limitation in application.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a low-jitter injection locking phase-locked loop based on multiphase injection and correction, which comprises an injection circuit, an injection locking oscillator, a first frequency divider, a phase frequency detector, a charge pump and a low-pass filter;
The injection circuit comprises a multiphase signal generator and a multiphase self-correction circuit;
the multiphase signal generator is used for processing the reference signal to generate multiphase injection signals;
The input end of the multiphase signal generator is connected with a reference signal and the output end of the multiphase self-correction circuit, and the output end of the multiphase signal generator is connected with the injection end of the injection locking oscillator;
The multiphase self-correction circuit is used for adjusting the position and the width of the input injection signal of the multiphase signal generator and comprises a first correction circuit, a second correction circuit and a third correction circuit;
The input end of the multiphase self-correction circuit is connected with the reference signal and the output end of the injection locking oscillator.
Further, the multiphase signal generator comprises a pulse generator, a first delay chain circuit and a second delay chain circuit;
The input end of the pulse generator is connected with a reference signal and the first output end and the second output end of the multiphase self-correction circuit, and the output end of the pulse generator is connected with the first input end of the first delay chain circuit and the first injection end of the injection locking oscillator;
The second input end of the first delay chain circuit is connected with the third output end of the multiphase self-correction circuit, and the output end of the first delay chain circuit is connected with the first input end of the second delay chain circuit and the second injection end of the injection locking oscillator;
The second input end of the second delay chain circuit is connected with the fourth output end of the multiphase self-correction circuit, and the output end of the second delay chain circuit is connected with the third injection end of the injection locking oscillator.
Further, the pulse generator comprises a first unit delay circuit, a second unit delay circuit and a logic gate;
The first input end of the first unit delay circuit is connected with a reference signal, the second input end of the first unit delay circuit is connected with the first output end of the multiphase self-correction circuit, and the output end of the first unit delay circuit is connected with the first input end of the logic gate and the first input end of the second unit delay circuit;
the second input end of the second unit delay circuit is connected with the second output end of the multiphase self-correction circuit, and the output end of the second unit delay circuit is connected with the second input end of the logic gate;
the output end of the logic gate is the output end of the pulse generator.
Further, a first input end and a second input end of the first correction circuit are connected with a reference signal, a third input end of the first correction circuit is connected with a first output end of the injection locking oscillator, a first output end of the first correction circuit is a first output end of the multiphase self-correction circuit, a second output end of the first correction circuit is a second output end of the multiphase self-correction circuit, and a third output end of the first correction circuit is connected with a first input end of the second correction circuit and a first input end of the third correction circuit;
The second input end of the second correction circuit is connected with a reference signal, the third input end of the second correction circuit is connected with the second output end of the injection locking oscillator, and the output end of the second correction circuit is the third output end of the multiphase self-correction circuit;
the second input end of the third correction circuit is connected with a reference signal, the third input end of the third correction circuit is connected with the third output end of the injection locking oscillator, and the output end of the third correction circuit is the fourth output end of the multiphase self-correction circuit.
Further, the first correction circuit comprises a second frequency divider, a first successive approximation controller, a second successive approximation controller and a first sub-sampling phase detector;
The input end of the second frequency divider is a first input end of the first correction circuit, the output end of the second frequency divider is connected with the first input end of the first successive approximation controller and the first input end of the second successive approximation controller, and the output end of the second frequency divider is a third output end of the first correction circuit; the output end of the first sub-sampling phase discriminator is connected with the second input end of the first successive approximation type controller and the second input end of the second successive approximation type controller; the first input end of the first sub-sampling phase discriminator is the second input end of the first correction circuit, the second input end of the first sub-sampling phase discriminator is the third input end of the first correction circuit, the output end of the first successive approximation controller is the first output end of the first correction circuit, and the output end of the second successive approximation controller is the second output end of the first correction circuit;
the second correction circuit comprises a third successive approximation controller and a second sub-sampling phase detector;
The first input end of the third successive approximation type controller is the first input end of the second correction circuit, and the second input end of the third successive approximation type controller is connected with the output end of the second sub-sampling phase discriminator; the first input end of the second sub-sampling phase discriminator is a second input end of the second correction circuit, the second input end of the second sub-sampling phase discriminator is a third input end of the second correction circuit, and the output end of the third successive approximation controller is an output end of the second correction circuit;
the third correction circuit comprises a fourth successive approximation controller and a third subsampled phase detector;
the first input end of the fourth successive approximation type controller is the first input end of the third correction circuit, and the second input end of the fourth successive approximation type controller is connected with the output end of the third subsampled phase detector; the first input end of the third subsampled phase detector is the second input end of the third correction circuit, the second input end of the third subsampled phase detector is the third input end of the third correction circuit, and the output end of the fourth successive approximation controller is the output end of the third correction circuit.
Further, the injection locked oscillator comprises a first injector, a second injector, a third injector, a first differential delay inverter, a second differential delay inverter, a third differential delay inverter, a first buffer, a second buffer and a third buffer;
The first injector, the second injector and the third injector are all N-type MOS tubes, and grid electrodes are respectively connected with a first injection end, a second injection end and a third injection end of the injection locking oscillator; the sources of the first injector, the second injector and the third injector are respectively connected with the anodes of the input signals of the first differential delay inverter, the second differential delay inverter and the third differential delay inverter, and the drains of the first injector, the second injector and the third injector are respectively connected with the cathodes of the input signals of the first differential delay inverter, the second differential delay inverter and the third differential delay inverter;
The first input end of the first differential delay inverter is connected with the output end of the low-pass filter, the second input end of the first differential delay inverter is connected with the output end of the third differential delay inverter, the first output end of the first differential delay inverter is connected with the input end of the first buffer and the second input end of the second differential delay inverter, and the output end of the first buffer is the first output end of the injection locking oscillator;
The first input end of the second differential delay inverter is connected with the output end of the low-pass filter, the first output end of the second differential delay inverter is connected with the input end of the second buffer and the second input end of the third differential delay inverter, and the output end of the second buffer is the second output end of the injection locking oscillator;
The first input end of the third differential delay inverter is connected with the output end of the low-pass filter, the output end of the third differential delay inverter is connected with the input end of the third buffer, and the output end of the third buffer is the third output end of the injection locking oscillator.
Further, the injection locking oscillator, the first frequency divider, the phase frequency detector, the charge pump and the low-pass filter form a phase-locked loop;
The input end of the first frequency divider is connected with the negative electrode of the output signal of the second buffer, the feedback signal output by the first frequency divider is connected with the second input end of the phase frequency detector, the first input end of the phase frequency detector is connected with the reference signal, the output end of the phase frequency detector is connected with the input end of the charge pump, and the output end of the charge pump is connected with the input end of the low-pass filter.
Further, the first sub-sampling phase detector, the second sub-sampling phase detector and the third sub-sampling phase detector comprise a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and an SR latch;
the first input end of the SR latch is connected with a signal SB, the second input end of the SR latch is connected with a signal RB, and the output end of the SR latch is the output end of the sub-sampling phase discriminator;
The grid electrode of the first PMOS tube, the grid electrode of the fifth PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the sixth PMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are all connected with reference signals; the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are both connected with the output end of the injection locking oscillator; the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are all connected with a signal SB; the grid electrode of the second PMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube are all connected with a signal RB; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are all connected with a power supply; the grid electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the source electrode of the sixth PMOS tube is connected with the grid electrode of the first NMOS tube, the drain electrode of the sixth PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are grounded.
Compared with the prior art, the invention has the following beneficial technical effects:
According to the multiphase injection and self-correction method provided by the invention, the traditional single-phase injection signal is converted into the multiphase self-correction injection signal, so that the intensity of the injection signal is effectively improved, and the clock jitter of the injection locking phase-locked loop is further reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:
FIG. 1 is a schematic diagram of an injection locked phase locked loop structure according to the present invention;
FIG. 2 is a schematic diagram of an injection circuit according to the present invention;
fig. 3 is a block diagram of a sub-sampling phase detector provided by the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that, directions or positional relationships indicated by terms such as "upper", "lower", "left", "right", "inner", "outer", etc., are based on directions or positional relationships shown in the drawings, or directions or positional relationships in which the inventive product is conventionally put in use, are merely for convenience of describing the present invention and simplifying the description, and are not indicative or implying that the apparatus or element to be referred to must have a specific direction, be configured and operated in a specific direction, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
The phase-locked loop circuit is used as a clock generation circuit, is one of the most important modules in an integrated circuit, and is widely applied to the fields of electronic communication, measurement, control, signal processing and the like along with the development of technology; the method can be used for tasks such as frequency synthesis, clock recovery, modulation and demodulation, phase control and the like, and has the advantages of high precision, high stability, quick response, good anti-interference performance and the like.
In conventional charge pump pll structures, the charge pump pll generally requires a low frequency reference signal as an input, and the loop includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. The charge pump phase-locked loop compares the frequency and the phase of the input signal and the frequency-divided signal through the frequency and phase discriminator, and outputs a pulse signal to control the charge pump to charge and discharge the filter, so as to regulate the output frequency of the voltage-controlled oscillator until the output signal can be locked to the frequency multiplication of the reference signal.
The main difference between the traditional injection locking phase-locked loop and the traditional charge pump phase-locked loop is that the injection locking phase-locked loop consists of a phase-locked loop feedback loop and an injection circuit, and the traditional charge pump phase-locked loop does not contain the injection circuit; in addition, conventional injection locked phase locked loops employ a single phase injection signal, resulting in limited injection strength. The locking process of an injection locked phase locked loop is determined by two factors: locking of the feedback loop of the phase locked loop and locking of the injection signal. Assuming that the injection locked phase locked loop is already in a steady state locked state before the injection signal arrives, the phase of the output signal is determined by the reference signal; however, when the injection signal arrives and there is a phase error with the reference signal, the injection signal may pull the output signal of the original phase-locked loop, changing its phase, resulting in a lock failure.
In view of the limitations of the above structure, the embodiment of the invention provides a low-jitter injection locking phase-locked loop structure based on multiphase injection and correction.
A low-jitter injection locking phase-locked loop based on multiphase injection and correction is shown in figure 1, and comprises an injection circuit, an injection locking oscillator, a first frequency divider, a phase frequency detector, a charge pump and a low-pass filter;
the injection circuit comprises a multiphase signal generator and a multiphase self-correction circuit;
the multiphase signal generator is used for processing the reference signal and generating multiphase injection signals;
The input end of the multiphase signal generator is connected with the reference signal and the output end of the multiphase self-correcting circuit, and the output end of the multiphase signal generator is connected with the injection end of the injection locking oscillator;
The multiphase self-correction circuit is used for adjusting the position and the width of the input injection signal of the multiphase signal generator and comprises a first correction circuit, a second correction circuit and a third correction circuit;
The input end of the multiphase self-correcting circuit is connected with the reference signal and the output end of the injection locking oscillator.
In the invention, an injection locking oscillator is used for locking an injection signal to generate an oscillation signal with low jitter; the phase frequency detector is used for comparing the frequency and the phase difference of the reference signal and the feedback signal and outputting a pulse signal to control the charge pump charge-discharge switch to be turned on and off; the charge pump is used for converting the control voltage into charge and discharge current according to the pulse signal output by the phase frequency detector; the low-pass filter is used for adjusting the frequency of the output signal of the injection locking phase-locked loop according to the current output voltage input by the charge pump; the first frequency divider is used for dividing the oscillating signal output by the injection locking oscillator.
As shown in fig. 2, the multiphase signal generator includes a pulse generator, a first delay chain circuit, and a second delay chain circuit;
The input end of the pulse generator is connected with a reference signal and the first output end and the second output end of the multiphase self-correction circuit, and the output end of the pulse generator is connected with the first input end of the first delay chain circuit and the first injection end of the injection locking oscillator;
The second input end of the first delay chain circuit is connected with the third output end of the multiphase self-correction circuit, and the output end of the first delay chain circuit is connected with the first input end of the second delay chain circuit and the second injection end of the injection locking oscillator;
the second input end of the second delay chain circuit is connected with the fourth output end of the multiphase self-correction circuit, and the output end of the second delay chain circuit is connected with the third injection end of the injection locking oscillator.
The pulse generator comprises a first unit delay circuit, a second unit delay circuit and a logic gate;
The first input end of the first unit delay circuit is connected with a reference signal, the second input end of the first unit delay circuit is connected with the first output end of the multiphase self-correcting circuit, and the output end of the first unit delay circuit is connected with the first input end of the logic gate and the first input end of the second unit delay circuit;
The second input end of the second unit delay circuit is connected with the second output end of the multiphase self-correction circuit, and the output end of the second unit delay circuit is connected with the second input end of the logic gate;
the output end of the logic gate is the output end of the pulse generator.
In the invention, the working process of the injection circuit is that the multiphase signal generator processes the reference signal to generate multiphase injection signal, then the multiphase self-correction circuit corrects the pulse width and position of the injection signal, and finally the injection signal is injected into the injection locking oscillator. In the correction process, the multiphase self-correction circuit continuously compares the phase difference of the reference signal and the output signal of the injection locking oscillator, generates a corresponding correction signal to dynamically adjust the multiphase signal generator, so that the signal edges of the multiphase injection signal and the injection locking oscillator are aligned, and the pulse width is optimal.
The first input end and the second input end of the first correction circuit are connected with reference signals, the third input end of the first correction circuit is connected with the first output end of the injection locking oscillator, the first output end of the first correction circuit is the first output end of the multiphase self-correction circuit, the second output end of the first correction circuit is the second output end of the multiphase self-correction circuit, and the third output end of the first correction circuit is connected with the first input end of the second correction circuit and the first input end of the third correction circuit;
A second input end of the second correction circuit is connected with a reference signal, a third input end of the second correction circuit is connected with a second output end of the injection locking oscillator, and an output end of the second correction circuit is a third output end of the multiphase self-correction circuit;
the second input end of the third correction circuit is connected with a reference signal, the third input end of the third correction circuit is connected with the third output end of the injection locking oscillator, and the output end of the third correction circuit is the fourth output end of the multiphase self-correction circuit.
As shown in fig. 2, the first correction circuit includes a second frequency divider, a first successive approximation controller, a second successive approximation controller, and a first sub-sampling phase detector;
The input end of the second frequency divider is a first input end of the first correction circuit, the output end of the second frequency divider is connected with the first input end of the first successive approximation type controller and the first input end of the second successive approximation type controller, and the output end of the second frequency divider is a third output end of the first correction circuit; the first output end of the first sub-sampling phase discriminator is connected with the second input end of the first successive approximation type controller and the second input end of the second successive approximation type controller; the first input end of the first sub-sampling phase discriminator is a second input end of the first correction circuit, the second input end of the first sub-sampling phase discriminator is a third input end of the first correction circuit, the output end of the first successive approximation controller is a first output end of the first correction circuit, and the output end of the second successive approximation controller is a second output end of the first correction circuit;
The second correction circuit comprises a third successive approximation controller and a second sub-sampling phase detector;
The first input end of the third successive approximation type controller is the first input end of the second correction circuit, and the second input end of the third successive approximation type controller is connected with the output end of the second sub-sampling phase discriminator; the first input end of the second sub-sampling phase discriminator is a second input end of the second correction circuit, the second input end of the second sub-sampling phase discriminator is a third input end of the second correction circuit, and the output end of the third successive approximation controller is an output end of the second correction circuit;
The third correction circuit comprises a fourth successive approximation controller and a third subsampled phase detector;
the first input end of the fourth successive approximation controller is the first input end of the third correction circuit, and the second input end of the fourth successive approximation controller is connected with the output end of the third subsampled phase detector; the first input end of the third subsampled phase detector is the second input end of the third correction circuit, the second input end of the third subsampled phase detector is the third input end of the third correction circuit, and the output end of the fourth successive approximation controller is the output end of the third correction circuit.
The injection locking oscillator comprises a first injector, a second injector, a third injector, a first differential delay inverter, a second differential delay inverter, a third differential delay inverter, a first buffer, a second buffer and a third buffer;
the first injector, the second injector and the third injector are all N-type MOS tubes, and grid electrodes are respectively connected with a first injection end, a second injection end and a third injection end of the injection locking oscillator; the sources of the first injector, the second injector and the third injector are respectively connected with the anodes of the input signals of the first differential delay inverter, the second differential delay inverter and the third differential delay inverter, and the drains of the first injector, the second injector and the third injector are respectively connected with the cathodes of the input signals of the first differential delay inverter, the second differential delay inverter and the third differential delay inverter;
A first input end of the first differential delay inverter is connected with an output end of the low-pass filter, a second input end of the first differential delay inverter is connected with an output end of the third differential delay inverter, a first output end of the first differential delay inverter is connected with an input end of the first buffer and a second input end of the second differential delay inverter, and an output end of the first buffer is a first output end of the injection locking oscillator;
The first input end of the second differential delay inverter is connected with the output end of the low-pass filter, the first output end of the second differential delay inverter is connected with the input end of the second buffer and the second input end of the third differential delay inverter, and the output end of the second buffer is the second output end of the injection locking oscillator;
the first input end of the third differential delay inverter is connected with the output end of the low-pass filter, the output end of the third differential delay inverter is connected with the input end of the third buffer, and the output end of the third buffer is the third output end of the injection locking oscillator.
The injection locking oscillator, the first frequency divider, the phase frequency detector, the charge pump and the low-pass filter form a phase-locked loop;
The input end of the first frequency divider is connected with the negative electrode of the output signal of the second buffer, the feedback signal output by the first frequency divider is connected with the second input end of the phase frequency detector, the first input end of the phase frequency detector is connected with the reference signal, the output end of the phase frequency detector is connected with the input end of the charge pump, and the output end of the charge pump is connected with the input end of the low-pass filter.
In the invention, the first sub-sampling phase discriminator, the second sub-sampling phase discriminator and the third sub-sampling phase discriminator adopt the same sub-sampling phase discriminator, and the structure is shown in fig. 3, and the sub-sampling phase discriminator comprises a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6 and an SR latch;
The first input end of the SR latch is connected with the signal SB, the second input end of the SR latch is connected with the signal RB, and the output end of the SR latch is the output end of the sub-sampling phase discriminator;
The grid electrode of the first PMOS tube P1 is connected with a reference signal, the source electrode of the first PMOS tube P1 is connected with a power supply, and the drain electrode of the first PMOS tube P1 is connected with a signal SB;
The grid electrode of the second PMOS tube P2 is connected with the source electrode of the third PMOS tube P3, the source electrode of the second PMOS tube P2 is connected with a power supply, the drain electrode of the second PMOS tube P2 is connected with a signal SB, and the grid electrode of the second PMOS tube P2 is connected with a signal RB;
the grid electrode of the third PMOS tube P3 is connected with a reference signal, and the drain electrode of the third PMOS tube P3 is connected with the grid electrode of the fourth PMOS tube P4;
The source electrode of the fourth PMOS tube P4 is connected with a power supply, the drain electrode of the fourth PMOS tube P4 is connected with a signal RB, and the grid electrode of the fourth PMOS tube P4 is connected with a signal SB;
the grid electrode of the fifth PMOS tube P5 is connected with a reference signal, the source electrode of the fifth PMOS tube P5 is connected with a power supply, and the drain electrode of the fifth PMOS tube P5 is connected with a signal RB;
the grid electrode of the sixth PMOS tube P6 is connected with a reference signal, the source electrode of the sixth PMOS tube P6 is connected with the grid electrode of the first NMOS tube N1, and the drain electrode of the sixth PMOS tube is connected with the grid electrode of the second NMOS tube N2;
The source electrode of the first NMOS tube N1 is connected with the drain electrode of the third NMOS tube N3, the drain electrode of the first NMOS tube N1 is connected with a signal SB, and the gate electrode of the first NMOS tube N1 is connected with a signal RB;
The source electrode of the second NMOS tube N2 is connected with the drain electrode of the fourth NMOS tube N4, the drain electrode of the second NMOS tube N2 is connected with a signal RB, and the gate electrode of the second NMOS tube N2 is connected with a signal SB;
The grid electrode of the third NMOS tube N3 is connected with a reference signal, and the source electrode of the third NMOS tube N3 is connected with the drain electrode of the fifth NMOS tube N5;
The grid electrode of the fourth NMOS tube N4 is connected with a reference signal, and the source electrode of the fourth NMOS tube N4 is connected with the drain electrode of the sixth NMOS tube N6;
the grid electrode of the fifth NMOS tube N5 is connected with the output of a buffer in the injection locking oscillator, and the source electrode of the fifth NMOS tube N5 is grounded;
the gate of the sixth NMOS transistor N6 is connected with the output of the buffer in the injection locking oscillator, and the source of the sixth NMOS transistor N6 is grounded.
The embodiments given above are preferred examples for realizing the present invention, and the present invention is not limited to the above-described embodiments. Any immaterial additions and substitutions made by those skilled in the art according to the technical features of the technical scheme of the invention are all within the protection scope of the invention.
Claims (4)
1. The low-jitter injection locking phase-locked loop based on multiphase injection and correction is characterized by comprising an injection circuit, an injection locking oscillator, a first frequency divider, a phase frequency detector, a charge pump and a low-pass filter;
The injection circuit comprises a multiphase signal generator and a multiphase self-correction circuit;
the multiphase signal generator is used for processing the reference signal to generate multiphase injection signals;
The input end of the multiphase signal generator is connected with a reference signal and the output end of the multiphase self-correction circuit, and the output end of the multiphase signal generator is connected with the injection end of the injection locking oscillator;
The multiphase self-correction circuit is used for adjusting the position and the width of the input injection signal of the multiphase signal generator and comprises a first correction circuit, a second correction circuit and a third correction circuit;
The input end of the multiphase self-correction circuit is connected with a reference signal and the output end of the injection locking oscillator;
The multiphase signal generator comprises a pulse generator, a first delay chain circuit and a second delay chain circuit;
the input end of the pulse generator is connected with a reference signal and the first output end and the second output end of the multiphase self-correction circuit, and the output end of the pulse generator is connected with the first input end of the first delay chain circuit and the first injection end of the injection locking oscillator;
The second input end of the first delay chain circuit is connected with the third output end of the multiphase self-correction circuit, and the output end of the first delay chain circuit is connected with the first input end of the second delay chain circuit and the second injection end of the injection locking oscillator;
The second input end of the second delay chain circuit is connected with the fourth output end of the multiphase self-correction circuit, and the output end of the second delay chain circuit is connected with the third injection end of the injection locking oscillator;
the pulse generator comprises a first unit delay circuit, a second unit delay circuit and a logic gate;
The first input end of the first unit delay circuit is connected with a reference signal, the second input end of the first unit delay circuit is connected with the first output end of the multiphase self-correction circuit, and the output end of the first unit delay circuit is connected with the first input end of the logic gate and the first input end of the second unit delay circuit;
the second input end of the second unit delay circuit is connected with the second output end of the multiphase self-correction circuit, and the output end of the second unit delay circuit is connected with the second input end of the logic gate;
The output end of the logic gate is the output end of the pulse generator;
The logic gate is an AND gate;
the first input end and the second input end of the first correction circuit are connected with reference signals, the third input end of the first correction circuit is connected with the first output end of the injection locking oscillator, the first output end of the first correction circuit is the first output end of the multiphase self-correction circuit, the second output end of the first correction circuit is the second output end of the multiphase self-correction circuit, and the third output end of the first correction circuit is connected with the first input end of the second correction circuit and the first input end of the third correction circuit;
The second input end of the second correction circuit is connected with a reference signal, the third input end of the second correction circuit is connected with the second output end of the injection locking oscillator, and the output end of the second correction circuit is the third output end of the multiphase self-correction circuit;
The second input end of the third correction circuit is connected with a reference signal, the third input end of the third correction circuit is connected with the third output end of the injection locking oscillator, and the output end of the third correction circuit is the fourth output end of the multiphase self-correction circuit;
The first correction circuit comprises a second frequency divider, a first successive approximation controller, a second successive approximation controller and a first sub-sampling phase discriminator;
The input end of the second frequency divider is a first input end of the first correction circuit, the output end of the second frequency divider is connected with the first input end of the first successive approximation controller and the first input end of the second successive approximation controller, and the output end of the second frequency divider is a third output end of the first correction circuit; the output end of the first sub-sampling phase discriminator is connected with the second input end of the first successive approximation type controller and the second input end of the second successive approximation type controller; the first input end of the first sub-sampling phase discriminator is the second input end of the first correction circuit, the second input end of the first sub-sampling phase discriminator is the third input end of the first correction circuit, the output end of the first successive approximation controller is the first output end of the first correction circuit, and the output end of the second successive approximation controller is the second output end of the first correction circuit;
the second correction circuit comprises a third successive approximation controller and a second sub-sampling phase detector;
The first input end of the third successive approximation type controller is the first input end of the second correction circuit, and the second input end of the third successive approximation type controller is connected with the output end of the second sub-sampling phase discriminator; the first input end of the second sub-sampling phase discriminator is a second input end of the second correction circuit, the second input end of the second sub-sampling phase discriminator is a third input end of the second correction circuit, and the output end of the third successive approximation controller is an output end of the second correction circuit;
the third correction circuit comprises a fourth successive approximation controller and a third subsampled phase detector;
the first input end of the fourth successive approximation type controller is the first input end of the third correction circuit, and the second input end of the fourth successive approximation type controller is connected with the output end of the third subsampled phase detector; the first input end of the third subsampled phase detector is the second input end of the third correction circuit, the second input end of the third subsampled phase detector is the third input end of the third correction circuit, and the output end of the fourth successive approximation controller is the output end of the third correction circuit.
2. The low jitter injection locked phase locked loop based on multi-phase injection and correction of claim 1 wherein the injection locked oscillator comprises a first injector, a second injector, a third injector, a first differential delay inverter, a second differential delay inverter, a third differential delay inverter, a first buffer, a second buffer, a third buffer;
the first injector, the second injector and the third injector are all N-type MOS tubes, and grid electrodes are respectively connected with a first injection end, a second injection end and a third injection end of the injection locking oscillator; the sources of the first injector, the second injector and the third injector are respectively connected with the anodes of input signals of the first differential delay inverter, the second differential delay inverter and the third differential delay inverter, and the drains of the first injector, the second injector and the third injector are respectively connected with the cathodes of input signals of the first differential delay inverter, the second differential delay inverter and the third differential delay inverter;
The first input end of the first differential delay inverter is connected with the output end of the low-pass filter, the second input end of the first differential delay inverter is connected with the output end of the third differential delay inverter, the first output end of the first differential delay inverter is connected with the input end of the first buffer and the second input end of the second differential delay inverter, and the output end of the first buffer is the first output end of the injection locking oscillator;
The first input end of the second differential delay inverter is connected with the output end of the low-pass filter, the first output end of the second differential delay inverter is connected with the input end of the second buffer and the second input end of the third differential delay inverter, and the output end of the second buffer is the second output end of the injection locking oscillator;
The first input end of the third differential delay inverter is connected with the output end of the low-pass filter, the output end of the third differential delay inverter is connected with the input end of the third buffer, and the output end of the third buffer is the third output end of the injection locking oscillator.
3. The low-jitter injection locked phase-locked loop based on multi-phase injection and correction of claim 2 wherein said injection locked oscillator, said first frequency divider, said phase frequency detector, said charge pump, said low-pass filter form a phase-locked loop;
The input end of the first frequency divider is connected with the negative electrode of the output signal of the second buffer, the feedback signal output by the first frequency divider is connected with the second input end of the phase frequency detector, the first input end of the phase frequency detector is connected with the reference signal, the output end of the phase frequency detector is connected with the input end of the charge pump, and the output end of the charge pump is connected with the input end of the low-pass filter.
4. The low jitter injection locked phase locked loop based on multi-phase injection and correction of claim 1 wherein the first sub-sampling phase detector, the second sub-sampling phase detector, and the third sub-sampling phase detector each comprise a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, and an SR latch;
the first input end of the SR latch is connected with a signal SB, the second input end of the SR latch is connected with a signal RB, and the output end of the SR latch is the output end of the sub-sampling phase discriminator;
The grid electrode of the first PMOS tube, the grid electrode of the fifth PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the sixth PMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are all connected with reference signals; the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are both connected with the output end of the injection locking oscillator; the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second NMOS tube are all connected with a signal SB; the grid electrode of the second PMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the second NMOS tube are all connected with a signal RB; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are all connected with a power supply; the grid electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the source electrode of the sixth PMOS tube is connected with the grid electrode of the first NMOS tube, the drain electrode of the sixth PMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the third NMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fourth NMOS tube is connected with the drain electrode of the sixth NMOS tube, and the source electrode of the fifth NMOS tube and the source electrode of the sixth NMOS tube are grounded.
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| KR101013920B1 (en) * | 2008-07-30 | 2011-02-14 | 고려대학교 산학협력단 | Frequency multiplication system and its control method |
| CN106549664B (en) * | 2015-09-22 | 2019-11-22 | 澜起科技股份有限公司 | A kind of digital delay phase-locked loop and its locking means |
| CN110113047B (en) * | 2019-05-06 | 2022-12-09 | 东南大学 | An ultra-low jitter coupled multiplier delay phase-locked loop circuit |
| CN111953303A (en) * | 2020-07-27 | 2020-11-17 | 电子科技大学 | A Phase Self-correcting I/Q Quadrature Mixer |
| US11728962B2 (en) * | 2021-12-13 | 2023-08-15 | Xilinx, Inc. | Multi-phase clock signal generation circuitry |
| CN117118401B (en) * | 2023-09-13 | 2024-02-06 | 南京汇君半导体科技有限公司 | Phase self-correcting I/Q quadrature signal generator |
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| CN101807914A (en) * | 2009-07-21 | 2010-08-18 | 清华大学 | Frequency self-correction phase lock loop adopting bonding wire as electric inductance of oscillator |
| CN112448716A (en) * | 2019-08-28 | 2021-03-05 | 三星电子株式会社 | Local oscillator i/q multiplier |
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