CN101826869B - Phaselocked loop circuit comprising double current source charge pump and double comparator reset circuit - Google Patents
Phaselocked loop circuit comprising double current source charge pump and double comparator reset circuit Download PDFInfo
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- CN101826869B CN101826869B CN200910238803XA CN200910238803A CN101826869B CN 101826869 B CN101826869 B CN 101826869B CN 200910238803X A CN200910238803X A CN 200910238803XA CN 200910238803 A CN200910238803 A CN 200910238803A CN 101826869 B CN101826869 B CN 101826869B
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Abstract
The invention relates to a phaselocked loop circuit comprising a double current source charge pump and a double comparator reset circuit, comprising a phase detection discriminator, a charge pump and a reset circuit. The phase detection discriminator is used for receiving reference signals and feedback signals of the phaselocked loop of the charge pump and respectively generating UP and DN signals based on the reference signal and the feedback signal; the UP signals subjected to phase reversal and the DN signals are together sent to the charge pump for processing to generate current input signals of phase difference between indication reference signals and clock signals, i.e. signals needed by the next stage of circuit of the charge pump type phaselocked loop; the reset circuit receives voltage drip signals sampled from the current source of the charge pump and finally generates the reset signals needed by the resetting of the phase detection discriminator, and when the reset signals are input into the phase detection discriminator, the phase detection discriminator can reset. By using the technical scheme, the circuit reset has short delay time and no dead zone.
Description
Technical field the present invention relates to the automatic control of frequency or phase place with synchronously, particularly relates to each functional unit that constitutes phase-locked loop, relates in particular to the double-current source charge pump and the dual comparator reset circuit that are used for charge pump type phaselocked loop circuit.Background technology charge pump type phaselocked loop (Phase Locked Loop) has been widely used in fields such as digital communication system, wireless communication system, digital circuitry and disk drive system as the most important structure of phase-locked loop.The charge pump type phaselocked loop structure is as shown in Figure 3, is a reponse system of being made up of phase detection discriminator 101, charge pump 102, loop filter 103, voltage controlled oscillator 104 and frequency divider 105.Said charge pump type phaselocked loop adopts external crystal oscillator that reference signal is provided; Voltage controlled oscillator 104 produces the output signal on the sheet; Frequency divider 105 is realized the output signal of voltage controlled oscillator 104 is carried out Fractional-N frequency; Phase detection discriminator 101 carries out bit comparison mutually with the output signal (being feedback signal) of input reference signal and frequency divider 105, and the frequency of oscillation F of voltage controlled oscillator 104 is regulated in its output through charge pump 102 and after loop filter 103 filtering
Vco, make it finally be locked in N * F
RefOn, wherein N is the divider ratio of frequency divider 105, F
RefBe reference signal frequency.
Phase detection discriminator and charge pump are as the key components of charge pump type phaselocked loop; The greatest problem of its existence is that the phase difference when reference signal and feedback signal is when very little; UP that phase detection discriminator produces and DN signal pulse are too narrow and have insufficient time to and open charge pump switches; Make charge pump not have electric current output; The loop open-loop gain reduces to zero, thereby causes the phase-locked loop output phase can't lock, prolong the loop-locking time or the phase noise performance when causing pll lock degenerates.Usually this phase difference zone that can not differentiate is called the dead band.
For addressing the above problem; The researcher has proposed the method in multiple elimination dead band; Michael Henderson Perrott proposes wherein a kind of solution in document " Techniques for High Data Rate Modulation and Low Power Operation ofFractional-N Frequency Synthesizer "; Reference signal and feedback signal are carried out two divided-frequency respectively, carry out phase demodulation with XOR gate more afterwards and eliminate the dead band, but this method causes having bigger spuious component at 1/2nd reference frequency frequency deviation place; The bandwidth of the loop filter that requires is narrower, finally has influence on the stabilization time and the phase noise performance of phase-locked loop.
Another kind of commonly used method is, on the reset path of phase detection discriminator, adds delay cell (be δ time of delay), and is as shown in Figure 4, and this makes that the pulse of UP and DN signal is enough wide with the unlatching charge pump switches when loop-locking.Therefore, when phase difference changed a minimum amount, the charge pump total energy produced the clean output current of proportional variation, and the dead band is able to eliminate.But; The method has also been brought problems: 1. people such as Mehmet Soyuer proposes at document " Frequency Limitations of a Conventional Phase-Frequency Detector "; In order to guarantee the operating rate of phase detection discriminator, the reset delay time need be satisfied δ＜1/ (2 * f
PFD, max), f wherein
PFD, maxIt is the maximum operating speed of phase detection discriminator.In some applications, such as ethernet communication, phase demodulation frequency is hundreds of MHz or higher, so choosing of reset delay time exists certain constraint; 2. the existence of reset delay makes loop in the still conducting simultaneously of when locking charging and discharging currents, because the mismatch between charging and discharging currents can cause the net current of conduction period charge pump output simultaneously non-vanishing.Carry at document [Integrated Circuit Design for High-Speed FrequencySynthesis] according to people such as John Rogers, with reference to spuious
I wherein
CP, Δ I is respectively charge pump charging and discharging currents and mismatch current, K
VCOBe voltage controlled oscillator gain, C
2Be loop filter capacitance.Therefore, spuious in order to reduce reference, the reset delay time, δ should be as far as possible little.3. the reset delay unit is under different supply voltages, temperature and process conditions, and change greatly its time of delay.
In view of above background; In order to eliminate the dead-time problem of charge pump type phaselocked loop; The present invention proposes a kind of phase detection discriminator and charge pump circuit that does not have the dead band; Whether its reset signal detects according to two comparators in the reset circuit that the pressure drop on the charging and discharging currents source produces in the charge pump, forms the closed-loop control of reset delay, has overcome the influence that above-mentioned supply voltage, flow-route and temperature change.Can obtain enough little its resetting time, improved the operating rate of phase detection discriminator and the spurious performance of phase-locked loop.
Not enough below prior art exists:
1, adopt the method for frequency division to cause there is bigger spuious component the ring that requires at 1/2nd reference frequency frequency deviation place
The bandwidth of path filter is narrower, finally has influence on the stabilization time and the phase noise performance of phase-locked loop;
2, the method that on the reset path of phase detection discriminator, adds delay cell is because the existence of reset delay makes loop
Still conducting simultaneously of charging and discharging currents when locking is because the mismatch between charging and discharging currents can cause the conducting phase simultaneously
Between the net current of charge pump output non-vanishing; The reset delay unit is at different supply voltages, temperature and technology bar
Under the part, change greatly its time of delay.
The technical problem that summary of the invention the present invention will solve is to avoid the weak point of above-mentioned prior art and proposes a kind of phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit.
The present invention solve the technical problem and can realize through adopting following technical scheme: propose a kind of circuit that is used for charge pump type phaselocked loop; Comprise phase detection discriminator and charge pump; Also comprise reset circuit; Said phase detection discriminator is used to receive the reference signal and the feedback signal of charge pump type phaselocked loop, and produces UP (UP) and DN (Down) signal respectively based on described reference signal and feedback signal; The UP signal is sent to charge pump for processing with the DN signal after anti-phase, produce the current output signal of phase difference between indication reference signal and the clock signal, i.e. the required signal of charge pump type phaselocked loop next stage circuit; Said reset circuit receives the voltage drop signal that is upsampled to from charge pump first and second current sources, and finally produces the phase detection discriminator required reset signal that resets, and during this reset signal input phase detection discriminator phase detection discriminator is resetted.
Said phase detection discriminator is ternary phase detection discriminator structure, comprises first d type flip flop, second d type flip flop and inverter; Said first d type flip flop is used to receive reference signal, produces the UP signal and receives reset signal so that the UP signal is reset; Said second d type flip flop is used for receiving feedback signals, produces the DN signal and receives reset signal the DN signal is reset;
Said inverter carries out anti-phase to the UP signal that first d type flip flop produces, and delivers to charge pump for processing then.
Said first d type flip flop and second d type flip flop are d type flip flop that the edge triggers, that band resets.
First d type flip flop of said phase detection discriminator and the D of second d type flip flop input termination logic high; The input end of clock of first d type flip flop connects reference signal, and output produces the UP signal; The input end of clock of second d type flip flop connects feedback signal, and output produces the DN signal.
Said charge pump comprises first current source, second current source, first switch S 1 and the second switch S2 that is coupled in series between power supply and the circuit ground; Said first current source is used to provide charging current; Said second current source is used to let out leads discharging current.
Said inverter carries out anti-phase to the UP signal that first d type flip flop produces, and delivers to first switch S 1 of charge pump then.
Said first switch S 1 receives the inversion signal of UP signal, when UP is logic high, the charging current of current source (3021) is coupled to the current output terminal signal Iout of charge pump; Second switch S2 receives the DN signal, when DN is logic high, the discharging current of current source is coupled to the current output terminal signal Iout of charge pump.
Said reset circuit comprise comparator, comparator and with door, said comparator detects the voltage drop on first current source, comparator detects the voltage drop on second current source; When UP was logic low, switch S 1 was broken off, and the voltage on the charging current source reduces to zero, comparator output logic low level; When UP was logic high, switch S 1 was connected, and forward drop is arranged, comparator output logic high level on the current source; When DN was logic low, switch S 2 was broken off, and discharging current has forward drop on the source, comparator output logic low level; When DN was logic high, switch S 2 was connected, and the voltage on the current source is reduced to non-zero, comparator output logic high level; When the output of comparator and comparator is logic high, its via realize with door " with " logical operation, make reset signal become logic high, thereby after making this reset signal input to phase detection discriminator phase detection discriminator resetted by logic low.
When said reset signal was logic high, phase detection discriminator received replacement UP and DN signal after the reset signal, even UP and DN are logic high, and indicated holding time of its logic high to be enough to make charge pump switches to be opened.
When the UP signal became logic high by logic low, the indication reference signal became logic high by logic low; When the DN signal became logic high by logic low, the indication feedback signal became logic high by logic low.
Compare with prior art, the beneficial effect of technical scheme according to the invention is:
1, circuit according to the invention does not have the reset delay unit; Whether reset signal detects simultaneously according to two comparators in the reset circuit that the voltage drop on the charging and discharging currents source produces in the charge pump; Form the closed-loop control of reset delay time; Under various supply voltages, temperature and technique change condition; Its reset delay time can be enough little and guarantees that the charge pump switches total energy is opened under the loop-locking condition, can realize the high speed operation and the good spurious performance of phase-locked loop of phase detection discriminator;
2, circuit reset little, no dead band time of delay that is used for charge pump type phaselocked loop according to the invention.
Description of drawings
Fig. 1 contains the basic circuit diagram of the phase-locked loop circuit preferred embodiment of double-current source charge pump and dual comparator reset circuit for the present invention;
Fig. 2 is the sequential chart of said circuit;
Fig. 3 is a prior art charge pump type phaselocked loop structured flowchart;
Fig. 4 is the phase detection discriminator and the charge pump basic circuit diagram of prior art band delay cell;
Fig. 5 (a) is the time-domain-simulation oscillogram of prior art phase detection discriminator and charge pump construction;
Fig. 5 (b) is the time-domain-simulation oscillogram of the embodiment of the invention.
Embodiment is done further to detail below in conjunction with the preferred embodiment shown in each accompanying drawing.
A kind of circuit that is used for charge pump type phaselocked loop of the present invention; As shown in Figure 1; Comprise phase detection discriminator 301 and charge pump 302; Especially also comprise reset circuit 303, said phase detection discriminator 301 is used to receive the reference signal and the feedback signal of charge pump type phaselocked loop, and produces UP and DN (Down) signal respectively based on described reference signal and feedback signal; The UP signal is sent to charge pump 302 with the DN signal and handles after anti-phase, produce the current output signal of phase difference between indication reference signal and the clock signal, i.e. the required signal of charge pump type phaselocked loop next stage circuit; Said reset circuit 303 receives the voltage drop signal that is upsampled to from charge pump 302 first current sources 3021 and second current source 3022; And finally produce the phase detection discriminator 301 required reset signal that resets, during this reset signal input phase detection discriminator 301 phase detection discriminator 301 is resetted.
Said phase detection discriminator 301 is ternary phase detection discriminator structure, comprises first d type flip flop 3011, second d type flip flop 3012 and inverter 3013; Said first d type flip flop 3011 is used to receive reference signal, produces the UP signal and receives reset signal so that the UP signal is reset; Said second d type flip flop 3012 is used for receiving feedback signals, produces the DN signal and receives reset signal the DN signal is reset; The UP signal that 3013 pairs first d type flip flops of said inverter 3011 produce carries out anti-phase, delivers to charge pump 302 then and handles.
The d type flip flop that said first d type flip flop 3011 and second d type flip flop 3012 trigger for the edge, that band resets.
First d type flip flop 3011 of said phase detection discriminator 301 and the D of second d type flip flop 3012 input termination logic high; The input end of clock of first d type flip flop 3011 connects reference signal, and output produces the UP signal; The input end of clock of second d type flip flop 3012 connects feedback signal, and output produces the DN signal.
Said charge pump 302 comprises first current source 3021 that is coupled in series between power supply and the circuit ground, second current source 3022, first switch S 1 and second switch S2; Said first current source 3021 is used to provide charging current; Said second current source 3022 is used to let out leads discharging current.
The UP signal that 3013 pairs first d type flip flops of said inverter 3011 produce carries out anti-phase, delivers to first switch S 1 of charge pump 302 then.
Said first switch S 1 receives the inversion signal of UP signal, when UP is logic high, the charging current of first current source 3021 is coupled to the current output terminal signal Iout of charge pump 302; Second switch S2 receives the DN signal, when DN is logic high, the discharging current of second current source 3022 is coupled to the current output terminal signal Iout of charge pump.
Said reset circuit 303 comprise first comparator 3031, second comparator 3032 and with door 3033, the voltage drop that said first comparator 3031 detects on first current source 3021, the voltage drop that second comparator 3032 detects on second current source 3022; When UP was logic low, switch S 1 was broken off, and the voltage on first current source 3021 reduces to zero, first comparator, 3031 output logic low levels; When UP was logic high, switch S 1 was connected, and the voltage on first current source 3021 is reduced to non-zero, first comparator, 3031 output logic high level; When DN was logic low, switch S 2 was broken off, and on second current source 3022 forward drop is arranged, second comparator, 3032 output logic low levels; When DN was logic high, switch S 2 was connected, and on second current source 3022 forward drop is arranged, second comparator, 3032 output logic high level; When the output of first comparator 3031 and second comparator 3032 is logic high; Its via realize with door 3033 " with " logical operation; Make reset signal become logic high, thereby after making this reset signal input to phase detection discriminator 301 phase detection discriminator 301 is resetted by logic low.
When said reset signal was logic high, phase detection discriminator 301 received replacement UP and DN signal after the reset signal, even UP and DN are logic high, and indicated holding time of its logic high to be enough to make charge pump switches to be opened.
When the UP signal became logic high by logic low, the indication reference signal became logic high by logic low; When the DN signal became logic high by logic low, the indication feedback signal became logic high by logic low.
Fig. 2 is the sequential chart that is used for the circuit (being Fig. 3 phase detection discriminator 301 and charge pump 302 circuit) of charge pump type phaselocked loop according to the invention.Originally, UP signal and DN signal are logic low, and switch S 1 is broken off with switch S 2, and the voltage on first current source 3021 and second current source 3022 reduces to zero, and first comparator 3031 and second comparator, 3032 output logics are low, and reset signal is a logic low.When reference signal during prior to feedback signal, at time T 1 place, reference signal becomes logic high from logic low; Trigger d type flip flop 3011; Make that the UP signal is a logic high, after switch open time T on, switch S 1 is connected; Voltage drop on first current source 3021 raises by zero, and first comparator, 3031 output logics are high.At time T 2 places, feedback signal becomes logic high from logic low, triggers d type flip flop 3012; Make that the DN signal is a logic high, after switch open time T on, switch S 2 is connected; Voltage drop on second current source 3022 also raises by zero, and second comparator, 3032 output logics are high, and the logic high of first comparator 3031 and 3032 outputs of second comparator is through making reset signal become logic high by logic low with operation; D type flip flop 3011 and 3012 is reset; UP and DN signal become logic low again, and switch S 1 is broken off with S2, and the voltage drop on first current source 3021 and second current source 3022 reduces to zero again; First comparator 3031 and second comparator, 3032 output logics are low by hypermutation, and reset signal becomes logic low by logic high; When feedback signal during prior to reference signal, at time T 6 places, feedback signal becomes logic high from logic low; Trigger d type flip flop 3012; Make that the DN signal is a logic high, after switch open time T on, switch S 2 is connected; Voltage drop on second current source 3022 raises by zero, and second comparator, 3032 output logics are high.At time T 7 places, reference signal becomes logic high from logic low, triggers d type flip flop 3011; Make that the UP signal is a logic high, after switch open time T on, switch S 1 is connected; Voltage drop on first current source 3021 also raises by zero, and first comparator, 3031 output logics are high.The logic high of first comparator 3031 and 3032 outputs of second comparator is through making reset signal become logic high by logic low with operation; D type flip flop 3011 and 3012 is reset; UP and DN signal become logic low again, and switch S 1 is broken off with S2, and the voltage drop on first current source 3021 and second current source 3022 reduces to zero again; First comparator 3031 and second comparator, 3032 output logics are low by hypermutation, and reset signal becomes logic low by logic high; When the rising edge of reference signal and feedback signal arrived simultaneously, at time T 10 places, reference signal and feedback signal became logic high from logic low; D type flip flop 3011 and 3012 is triggered simultaneously; UP and DN signal become logic high by logic low simultaneously, and after switch open time T on, the voltage drop on first current source 3021 and second current source 3022 raises by zero; And detected by comparator 3031 and comparator 3032; The logic high that first comparator 3031 and second comparator 3032 are all exported is through making reset signal become logic high by logic low with operation, and d type flip flop 3011 and 3012 is reset, and UP and DN signal become logic low again; Switch S 1 is broken off with S2; Voltage drop on first current source 3021 and second current source 3022 is zero again, and first comparator 3031 and second comparator, 3032 output logics are low by hypermutation, and reset signal becomes logic low by logic high.
Fig. 5 (a) and Fig. 5 (b) have provided prior art phase-locked loop structures and the time-domain-simulation oscillogram of present embodiment structure when the rising edge of reference signal and feedback signal arrives simultaneously respectively.Can know by Fig. 5 (a) and Fig. 5 (b); The reset signal of present embodiment circuit structure just can become logic high by logic low rapidly after the rising edge of UP signal (or DN signal); And do not need unnecessary time margin; Reduce the time of charging and discharging currents conducting simultaneously in the charge pump, therefore improved the operating rate of phase detection discriminator and the spurious performance of phase-locked loop.Control belongs to closed-loop control owing to reset, and can guarantee that there is not the dead band in phase-locked loop under different supply voltages, temperature and process conditions.
Above-mentioned is preferred implementation procedure of the present invention, and common variation and replacement that those skilled in the art carries out on basis of the present invention are included within protection scope of the present invention.
Claims (7)
1. a phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit comprises that phase-locked loop circuit is whole, wherein has or not dead band phase detection discriminator (301) and charge pump (302), it is characterized in that:
Also comprise reset circuit (303);
Said phase detection discriminator (301) is used to receive the reference signal and the feedback signal of charge pump type phaselocked loop, and produces UP (UP) and DN (Down) signal respectively based on described reference signal and feedback signal;
The UP signal is sent to charge pump (302) with the DN signal and handles after anti-phase, produce the required signal of charge pump type phaselocked loop next stage circuit;
Said reset circuit (303) receives from charge pump (302) first and second current sources (3021; 3022) the voltage drop signal that is upsampled to; And finally produce phase detection discriminator (301) the required reset signal that resets, during this reset signal input phase detection discriminator (301) phase detection discriminator (301) is resetted;
Said phase detection discriminator (301) is ternary phase detection discriminator structure, comprises first d type flip flop (3011), second d type flip flop (3012) and inverter (3013); Said first d type flip flop (3011) is used to receive reference signal, produces the UP signal and receives reset signal so that the UP signal is reset;
Said second d type flip flop (3012) is used for receiving feedback signals, produces the DN signal and receives reset signal the DN signal is reset;
Said inverter (3013) carries out anti-phase to the UP signal that first d type flip flop (3011) produces, and delivers to charge pump (302) then and handles; Said charge pump (302) comprises first current source (3021), second current source (3022), first switch S 1 and the second switch S2 that is coupled in series between power supply and the circuit ground;
Said reset circuit (303) comprise first comparator (3031), second comparator (3032) and with door (3033); Said first comparator (3031) detects the voltage drop on first current source (3021), and second comparator (3032) detects the voltage drop on second current source (3022);
When UP was logic low, switch S 1 was broken off, and the voltage on first current source (3021) reduces to zero, first comparator (3031) output logic low level; When UP was logic high, switch S 1 was connected, and first current source has forward drop on (3021), first comparator (3031) output logic high level;
When DN was logic low, switch S 2 was broken off, and the voltage on second current source (3022) reduces to zero, second comparator (3032) output logic low level; When DN was logic high, switch S 2 was connected, and second current source has forward drop on (3022), second comparator (3032) output logic high level;
When the output of first comparator (3031) and second comparator (3032) is logic high; Its via realize with door (3033) " with " logical operation; Make reset signal become logic high, thereby after making this reset signal input to phase detection discriminator (301) phase detection discriminator (301) is resetted by logic low.
2. the phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit as claimed in claim 1 is characterized in that:
The d type flip flop that said first d type flip flop (3011) and second d type flip flop (3012) trigger for the edge, that band resets.
3. the phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit as claimed in claim 1 is characterized in that:
First d type flip flop (3011) of said phase detection discriminator (301) and the D of second d type flip flop (3012) input termination logic high;
The input end of clock of first d type flip flop (3011) connects reference signal, and output produces the UP signal;
The input end of clock of second d type flip flop (3012) connects feedback signal, and output produces the DN signal.
4. the phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit as claimed in claim 1 is characterized in that:
Said inverter (3013) carries out anti-phase to the UP signal that first d type flip flop (3011) produces, and delivers to first switch S 1 of charge pump (302) then.
5. the phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit as claimed in claim 4 is characterized in that:
Said first switch S 1 receives the inversion signal of UP signal, when UP is logic high, the charging current of first current source (3021) is coupled to the current output terminal signal Iout of charge pump (302); Second switch S2 receives the DN signal, when DN is logic high, the discharging current of second current source (3022) is coupled to the current output terminal signal Iout of charge pump.
6. the phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit as claimed in claim 1 is characterized in that:
When said reset signal was logic high, phase detection discriminator (301) received replacement UP and DN signal after the reset signal, even UP and DN are logic high, and indicated holding time of its logic high to be enough to make charge pump switches to be opened.
7. the phase-locked loop circuit that contains double-current source charge pump and dual comparator reset circuit as claimed in claim 1 is characterized in that:
When the UP signal became logic high by logic low, reference signal became logic high by logic low;
When the DN signal became logic high by logic low, feedback signal became logic high by logic low.
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| CN102497181B (en) * | 2011-12-22 | 2014-03-26 | 中国科学院上海微系统与信息技术研究所 | Ultra-low power consumption power-on reset circuit |
| US10826387B2 (en) * | 2018-11-27 | 2020-11-03 | Nxp B.V. | Charge pump and method for operating a charge pump |
| CN112181716B (en) * | 2019-07-02 | 2024-05-03 | 无锡有容微电子有限公司 | Data recovery circuit based on delay phase-locked loop |
| CN115656864B (en) * | 2022-09-09 | 2024-03-26 | 北京北方华创微电子装备有限公司 | Radio frequency power supply signal acquisition circuit and semiconductor process equipment |
| CN116232317B (en) * | 2023-03-03 | 2024-02-27 | 芯动微电子科技(武汉)有限公司 | High-speed frequency and phase discrimination circuit based on TSPC and phase-locked loop |
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| CN1253417A (en) * | 1998-11-06 | 2000-05-17 | 摩托罗拉公司 | Phase detector possessing frequency control |
| CN1691509A (en) * | 2004-04-28 | 2005-11-02 | 精工爱普生株式会社 | Differential Current Mode Phase/Frequency Detector Circuit |
| CN101542907A (en) * | 2006-11-30 | 2009-09-23 | 高通股份有限公司 | Linear phase frequency detector and charge pump for phase-locked loop |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1253417A (en) * | 1998-11-06 | 2000-05-17 | 摩托罗拉公司 | Phase detector possessing frequency control |
| CN1691509A (en) * | 2004-04-28 | 2005-11-02 | 精工爱普生株式会社 | Differential Current Mode Phase/Frequency Detector Circuit |
| CN101542907A (en) * | 2006-11-30 | 2009-09-23 | 高通股份有限公司 | Linear phase frequency detector and charge pump for phase-locked loop |
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