CN118232842A - Broadband injection locking frequency multiplier with variable frequency multiplication ratio - Google Patents
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Abstract
Description
技术领域Technical Field
本发明属于射频集成电路技术领域，具体涉及一种可变倍频比的宽带注入锁定倍频器。The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a broadband injection locked frequency multiplier with a variable frequency multiplication ratio.
背景技术Background technique
注入锁定倍频器将振荡器的输出信号倍频，产生高频输出，是锁相环和无线通讯中重要的部件。传统注入锁定倍频器带宽较窄，且难以实现可变倍频比，限制了其应用。可变倍频比的宽带注入锁定倍频器能够满足不同倍频比的使用场景，具有更好的普适性。The injection-locked frequency multiplier multiplies the output signal of the oscillator to generate a high-frequency output, and is an important component in phase-locked loops and wireless communications. Traditional injection-locked frequency multipliers have a narrow bandwidth and are difficult to achieve a variable multiplication ratio, which limits their application. The broadband injection-locked frequency multiplier with a variable multiplication ratio can meet the use scenarios of different multiplication ratios and has better universality.
目前提升带宽的方法主要有降低LC谐振腔的品质因素Q值和增大注入器的尺寸，但是降低LC谐振腔的品质因素Q值会使功耗变大；而通过增大注入器的尺寸来提升高次谐波的注入效率会导致工作频率下降。此外，当前实现可变倍频比的方法主要是通过多个D触发器和分频器级联，然后通过数据选择器选出需要的分频比信号，该方法电路较为复杂，版图面积大且功耗高。At present, the main methods to improve bandwidth are to reduce the quality factor Q value of the LC resonant cavity and increase the size of the injector. However, reducing the quality factor Q value of the LC resonant cavity will increase power consumption; and increasing the injection efficiency of high-order harmonics by increasing the size of the injector will cause the operating frequency to decrease. In addition, the current method of achieving variable multiplication ratio is mainly to cascade multiple D flip-flops and dividers, and then select the required division ratio signal through a data selector. This method has a relatively complex circuit, a large layout area and high power consumption.
因此，如何扩展注入锁定倍频器的带宽并同时实现可变倍频比，成为了亟待解决的问题。Therefore, how to expand the bandwidth of the injection-locked frequency multiplier and simultaneously achieve a variable multiplication ratio has become an urgent problem to be solved.
发明内容Summary of the invention
针对现有技术存在的问题，本发明提供一种可变倍频比的宽带注入锁定倍频器，包括第一极性可配置谐波发生器、第二极性可配置谐波发生器、第一注入器、第二注入器和注入锁定振荡器；In view of the problems existing in the prior art, the present invention provides a broadband injection-locked frequency multiplier with a variable frequency multiplication ratio, comprising a first polarity configurable harmonic generator, a second polarity configurable harmonic generator, a first injector, a second injector and an injection-locked oscillator;
所述第一极性可配置谐波发生器和所述第一注入器设置在所述注入锁定振荡器的其中一侧，且所述第一极性可配置谐波发生器与所述注入锁定振荡器通过所述第一注入器连接；所述第二极性可配置谐波发生器和所述第二注入器设置在所述注入锁定振荡器的另一侧，且所述第二极性可配置谐波发生器与所述注入锁定振荡器通过所述第二注入器连接；The first polarity configurable harmonic generator and the first injector are arranged on one side of the injection locked oscillator, and the first polarity configurable harmonic generator is connected to the injection locked oscillator through the first injector; the second polarity configurable harmonic generator and the second injector are arranged on the other side of the injection locked oscillator, and the second polarity configurable harmonic generator is connected to the injection locked oscillator through the second injector;
所述第一极性可配置谐波发生器和所述第二极性可配置谐波发生器用于产生不同阶数的谐波信号；The first polarity configurable harmonic generator and the second polarity configurable harmonic generator are used to generate harmonic signals of different orders;
所述注入锁定振荡器用于锁定所述极性可配置谐波发生器产生的谐波；The injection locked oscillator is used to lock the harmonics generated by the polarity configurable harmonic generator;
基波信号输入所述第一极性可配置谐波发生器和所述第二极性可配置谐波发生器产生谐波分量，通过控制所述第一极性可配置谐波发生器和所述第二极性可配置谐波发生器中变压器的耦合极性实现奇次或偶次谐波的放大，然后经所述注入器注入到所述注入锁定振荡器，实现可变倍频比倍频。The fundamental wave signal is input into the first polarity configurable harmonic generator and the second polarity configurable harmonic generator to generate harmonic components, and the odd or even harmonics are amplified by controlling the coupling polarity of the transformers in the first polarity configurable harmonic generator and the second polarity configurable harmonic generator. The harmonics are then injected into the injection locked oscillator through the injector to achieve variable frequency multiplication ratio.
进一步地，所述第一极性可配置谐波发生器包括第一变压器网络和第一信号输入网络；所述第二极性可配置谐波发生器包括第二变压器网络和第二信号输入网络；所述第一变压器网络的一端连接所述第一信号输入网络，所述第一变压器网络的另一端连接所述第一注入器；所述第二变压器网络的一端连接所述第二信号输入网络，所述第二变压器网络的另一端连接所述第二注入器。Further, the first polarity configurable harmonic generator includes a first transformer network and a first signal input network; the second polarity configurable harmonic generator includes a second transformer network and a second signal input network; one end of the first transformer network is connected to the first signal input network, and the other end of the first transformer network is connected to the first injector; one end of the second transformer network is connected to the second signal input network, and the other end of the second transformer network is connected to the second injector.
进一步地，所述第一变压器网络包括第一耦合电感、第二耦合电感、第三耦合电感、第四耦合电感、第一开关、第二开关、第三开关、第四开关、第五开关、第六开关、第七开关、第八开关；所述第一耦合电感的一端、所述第四耦合电感的一端分别连接电源；所述第一耦合电感的另一端、所述第四耦合电感的另一端分别连接所述第一信号输入网络；所述第二耦合电感的一端连接所述第一开关的一端和所述第四开关的一端，所述第二耦合电感的另一端连接所述第三开关的一端和所述第二开关的一端，所述第三耦合电感的一端连接所述第六开关的一端和所述第七开关的一端，所述第三耦合电感的另一端连接所述第五开关的一端和所述第八开关的一端；所述第一开关的另一端、所述第二开关的另一端、所述第五开关的另一端、所述第六开关的另一端连接所述第一注入器；所述第三开关的另一端、所述第四开关的另一端、所述第七开关的另一端、所述第八开关的另一端分别接地；Further, the first transformer network includes a first coupled inductor, a second coupled inductor, a third coupled inductor, a fourth coupled inductor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; one end of the first coupled inductor and one end of the fourth coupled inductor are respectively connected to a power supply; the other end of the first coupled inductor and the other end of the fourth coupled inductor are respectively connected to the first signal input network; one end of the second coupled inductor is connected to one end of the first switch and one end of the fourth switch, the other end of the second coupled inductor is connected to one end of the third switch and one end of the second switch, one end of the third coupled inductor is connected to one end of the sixth switch and one end of the seventh switch, and the other end of the third coupled inductor is connected to one end of the fifth switch and one end of the eighth switch; the other end of the first switch, the other end of the second switch, the other end of the fifth switch, and the other end of the sixth switch are connected to the first injector; the other end of the third switch, the other end of the fourth switch, the other end of the seventh switch, and the other end of the eighth switch are respectively grounded;
所述第二变压器网络包括第五耦合电感、第六耦合电感、第七耦合电感、第八耦合电感、第九开关、第十开关、第十一开关、第十二开关、第十三开关、第十四开关、第十五开关、第十六开关；所述第五耦合电感的一端、所述第八耦合电感的一端分别连接电源；所述第五耦合电感的另一端、所述第八耦合电感的另一端分别连接所述第二信号输入网络；所述第六耦合电感的一端连接所述第九开关的一端和所述第十二开关的一端，所述第六耦合电感的另一端连接所述第十开关的一端和所述第十一开关的一端，所述第七耦合电感的一端连接所述第十四开关的一端和所述第十五开关的一端，所述第七耦合电感的另一端连接所述第十三开关的一端和所述第十六开关的一端；所述第九开关的另一端、所述第十开关的另一端、所述第十三开关的另一端、所述第十四开关的另一端连接所述第二注入器；所述第十一开关的另一端、所述第十二开关的另一端、所述第十五开关的另一端、所述第十六开关的另一端分别接地。The second transformer network includes a fifth coupled inductor, a sixth coupled inductor, a seventh coupled inductor, an eighth coupled inductor, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a thirteenth switch, a fourteenth switch, a fifteenth switch, and a sixteenth switch; one end of the fifth coupled inductor and one end of the eighth coupled inductor are connected to a power supply respectively; the other end of the fifth coupled inductor and the other end of the eighth coupled inductor are connected to the second signal input network respectively; one end of the sixth coupled inductor is connected to one end of the ninth switch and one end of the twelfth switch, the other end of the sixth coupled inductor is connected to one end of the tenth switch and one end of the eleventh switch, one end of the seventh coupled inductor is connected to one end of the fourteenth switch and one end of the fifteenth switch, and the other end of the seventh coupled inductor is connected to one end of the thirteenth switch and one end of the sixteenth switch; the other end of the ninth switch, the other end of the tenth switch, the other end of the thirteenth switch, and the other end of the fourteenth switch are connected to the second injector; the other end of the eleventh switch, the other end of the twelfth switch, the other end of the fifteenth switch, and the other end of the sixteenth switch are grounded respectively.
进一步地，当所述第一变压器网络和所述第二变压器网络正向耦合，相反的奇次谐波相互抵消，相同的偶次谐波相互叠加，使所述第一极性可配置谐波发生器和所述第二极性可配置谐波发生器均产生二次谐波，实现二倍频比倍频；Further, when the first transformer network and the second transformer network are forward coupled, opposite odd harmonics cancel each other out, and identical even harmonics are superimposed on each other, so that the first polarity configurable harmonic generator and the second polarity configurable harmonic generator both generate second harmonics, achieving a doubling ratio of frequency doubling;
当所述第一变压器网络和所述第二变压器网络反向耦合，相同的偶次谐波相互抵消，相反的奇次谐波相互叠加，使所述第一极性可配置谐波发生器和所述第二极性可配置谐波发生器均产生三次谐波，实现三倍频比倍频。When the first transformer network and the second transformer network are reversely coupled, the same even harmonics cancel each other out, and the opposite odd harmonics are superimposed on each other, so that the first polarity configurable harmonic generator and the second polarity configurable harmonic generator both generate third harmonics, achieving a three-fold frequency ratio.
进一步地，所述第一信号输入网络包括第一NMOS晶体管、第二NMOS晶体管、第一电容、第二电容、第五电容、第一电阻、第二电阻；所述第一NMOS晶体管的源极、所述第二NMOS晶体管的源极分别接地；所述第一NMOS晶体管的栅极与偏置电压之间连接所述第一电阻，所述第二NMOS晶体管的栅极与偏置电压之间连接所述第二电阻；所述第一NMOS晶体管的栅极与基波信号的正极输入端之间连接所述第一电容，所述第二NMOS晶体管的栅极与基波信号的负极输入端之间连接所述第二电容；所述第一NMOS晶体管的漏极与所述第二NMOS晶体管的漏极之间连接所述第五电容和所述第一变压器网络的一端；Further, the first signal input network includes a first NMOS transistor, a second NMOS transistor, a first capacitor, a second capacitor, a fifth capacitor, a first resistor, and a second resistor; the source of the first NMOS transistor and the source of the second NMOS transistor are grounded respectively; the first resistor is connected between the gate of the first NMOS transistor and the bias voltage, and the second resistor is connected between the gate of the second NMOS transistor and the bias voltage; the first capacitor is connected between the gate of the first NMOS transistor and the positive input terminal of the fundamental signal, and the second capacitor is connected between the gate of the second NMOS transistor and the negative input terminal of the fundamental signal; the fifth capacitor and one end of the first transformer network are connected between the drain of the first NMOS transistor and the drain of the second NMOS transistor;
所述第二信号输入网络包括第三NMOS晶体管、第四NMOS晶体管、第三电容、第四电容、第六电容、第三电阻、第四电阻；所述第三NMOS晶体管的源极、所述第四NMOS晶体管的源极分别接地；所述第四NMOS晶体管的栅极与偏置电压之间连接所述第四电阻；所述第三NMOS晶体管的栅极与基波信号的正极输入端之间连接所述第三电容，所述第四NMOS晶体管的栅极与基波信号的负极输入端之间连接所述第四电容；所述第三NMOS晶体管的漏极与所述第四NMOS晶体管的漏极之间连接所述第六电容和所述第二变压器网络的一端。The second signal input network includes a third NMOS transistor, a fourth NMOS transistor, a third capacitor, a fourth capacitor, a sixth capacitor, a third resistor, and a fourth resistor; the source of the third NMOS transistor and the source of the fourth NMOS transistor are grounded respectively; the fourth resistor is connected between the gate of the fourth NMOS transistor and the bias voltage; the third capacitor is connected between the gate of the third NMOS transistor and the positive input terminal of the fundamental signal, and the fourth capacitor is connected between the gate of the fourth NMOS transistor and the negative input terminal of the fundamental signal; the sixth capacitor and one end of the second transformer network are connected between the drain of the third NMOS transistor and the drain of the fourth NMOS transistor.
进一步地，所述第一注入器包括第五NMOS晶体管、第七电容和第五电阻；所述第二注入器包括第六NMOS晶体管、第八电容和第六电阻；Further, the first injector includes a fifth NMOS transistor, a seventh capacitor and a fifth resistor; the second injector includes a sixth NMOS transistor, an eighth capacitor and a sixth resistor;
所述第五NMOS晶体管的源极和所述第六NMOS晶体管的源极分别接地；所述第五NMOS晶体管的漏极连接所述注入锁定振荡器的一端，所述第六NMOS晶体管的漏极分别连接所述注入锁定振荡器的另一端；所述第五NMOS晶体管的栅极与偏置电压之间连接所述第五电阻，所述第六NMOS晶体管的栅极与偏置电压之间连接所述第六电阻，所述第五NMOS晶体管的栅极与所述第一极性可配置谐波发生器之间连接所述第七电容，所述第六NMOS晶体管的栅极与所述第二极性可配置谐波发生器之间连接所述第八电容。The source of the fifth NMOS transistor and the source of the sixth NMOS transistor are grounded respectively; the drain of the fifth NMOS transistor is connected to one end of the injection locked oscillator, and the drain of the sixth NMOS transistor is connected to the other end of the injection locked oscillator respectively; the fifth resistor is connected between the gate of the fifth NMOS transistor and the bias voltage, the sixth resistor is connected between the gate of the sixth NMOS transistor and the bias voltage, the seventh capacitor is connected between the gate of the fifth NMOS transistor and the first polarity configurable harmonic generator, and the eighth capacitor is connected between the gate of the sixth NMOS transistor and the second polarity configurable harmonic generator.
进一步地，所述注入锁定振荡器包括谐振网络、第七NMOS晶体管、第八NMOS晶体管、第九NMOS晶体管、第十NMOS晶体管、第九电容；Further, the injection locked oscillator includes a resonant network, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and a ninth capacitor;
所述第九NMOS晶体管的源极和所述第十NMOS晶体管的源极分别接地，所述第九NMOS晶体管的漏极连接偏置电流，所述第九NMOS晶体管的栅极分别连接偏置电流和所述第十NMOS晶体管的栅极，所述第十NMOS晶体管的漏极连接所述第七NMOS晶体管的源极和所述第八NMOS晶体管的源极，所述第七NMOS晶体管的漏极连接所述第八NMOS晶体管的栅极、第九电容的一端和所述谐振网络的一端，所述第八NMOS晶体管的漏极连接所述第七NMOS晶体管的栅极、第九电容的另一端和所述谐振网络的另一端。The source of the ninth NMOS transistor and the source of the tenth NMOS transistor are grounded respectively, the drain of the ninth NMOS transistor is connected to the bias current, the gate of the ninth NMOS transistor is connected to the bias current and the gate of the tenth NMOS transistor respectively, the drain of the tenth NMOS transistor is connected to the source of the seventh NMOS transistor and the source of the eighth NMOS transistor, the drain of the seventh NMOS transistor is connected to the gate of the eighth NMOS transistor, one end of the ninth capacitor and one end of the resonant network, and the drain of the eighth NMOS transistor is connected to the gate of the seventh NMOS transistor, the other end of the ninth capacitor and the other end of the resonant network.
进一步地，所述谐振网络包括第九耦合电感、第十耦合电感、第十一耦合电感、第十二耦合电感、第十电容、第十一电容、第十二电容；Further, the resonant network includes a ninth coupled inductor, a tenth coupled inductor, an eleventh coupled inductor, a twelfth coupled inductor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor;
所述第十一耦合电感的一端连接所述第十电容的一端和所述第十二电容的一端，所述第十二耦合电感的一端连接所述第十一电容的一端和所述第十二电容的另一端，所述第十电容的另一端和所述第十一电容的另一端串联，所述第十一耦合电感的另一端和所述第十二耦合电感的另一端串联；所述第九耦合电感的一端和所述第十耦合电感的一端分别连接电源，所述第九耦合电感的另一端为所述谐振网络的一端，所述第十耦合电感的另一端为所述谐振网络的另一端。One end of the eleventh coupled inductor is connected to one end of the tenth capacitor and one end of the twelfth capacitor, one end of the twelfth coupled inductor is connected to one end of the eleventh capacitor and the other end of the twelfth capacitor, the other end of the tenth capacitor and the other end of the eleventh capacitor are connected in series, and the other end of the eleventh coupled inductor and the other end of the twelfth coupled inductor are connected in series; one end of the ninth coupled inductor and one end of the tenth coupled inductor are respectively connected to power supplies, the other end of the ninth coupled inductor is one end of the resonant network, and the other end of the tenth coupled inductor is the other end of the resonant network.
与现有技术相比，本发明具有以下有益的技术效果：Compared with the prior art, the present invention has the following beneficial technical effects:
第一，本发明通过控制极性可配置谐波发生器中变压器的耦合极性实现奇次或偶次谐波的放大，从而实现可变倍频比。First, the present invention realizes amplification of odd or even harmonics by controlling the coupling polarity of the transformer in the polarity configurable harmonic generator, thereby realizing a variable multiplication ratio.
第二，本发明中不同倍频模式对应的频带相互重叠，等效扩大了带宽。Second, in the present invention, the frequency bands corresponding to different frequency doubling modes overlap with each other, which effectively expands the bandwidth.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本公开的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制，其中：In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, rather than limiting the present disclosure, wherein:
图1是本发明可变倍频比的宽带注入锁定倍频器的电路原理图；FIG1 is a circuit diagram of a broadband injection-locked frequency multiplier with a variable frequency multiplication ratio according to the present invention;
图2是本发明分别实现二、三倍频时极性可配置谐波发生器的电路原理图，（a）为二倍频时极性可配置谐波发生器的电路原理图，（b）为三倍频时极性可配置谐波发生器的电路原理图；FIG2 is a circuit schematic diagram of a harmonic generator with configurable polarity when the present invention realizes double and triple frequencies, respectively, (a) is a circuit schematic diagram of a harmonic generator with configurable polarity when the frequency is doubled, and (b) is a circuit schematic diagram of a harmonic generator with configurable polarity when the frequency is tripled;
图3是本发明提供的电路工作频率范围仿真图。FIG. 3 is a simulation diagram of the operating frequency range of the circuit provided by the present invention.
具体实施方式Detailed ways
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.
因此，以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围，而是仅仅表示本发明的选定实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
在本发明的描述中，需要说明的是，术语、“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。In the description of the present invention, it should be noted that the terms, "upper", "lower", "left", "right", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
在本发明的描述中，还需要说明的是，除非另有明确的规定和限定，术语“设置”、“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
需要说明的是，在不冲突的情况下，本发明的实施例中的特征可以相互结合。It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.
本发明提供的一种可变倍频比的宽带注入锁定倍频器，具体包括第一极性可配置谐波发生器、第二极性可配置谐波发生器、第一注入器、第二注入器和注入锁定振荡器；第一极性可配置谐波发生器和第一注入器设置在注入锁定振荡器的其中一侧，且第一极性可配置谐波发生器与注入锁定振荡器通过第一注入器连接；第二极性可配置谐波发生器和第二注入器设置在注入锁定振荡器的另一侧，且第二极性可配置谐波发生器与注入锁定振荡器通过第二注入器连接。The present invention provides a broadband injection-locked frequency multiplier with a variable frequency multiplication ratio, which specifically comprises a first polarity configurable harmonic generator, a second polarity configurable harmonic generator, a first injector, a second injector and an injection-locked oscillator; the first polarity configurable harmonic generator and the first injector are arranged on one side of the injection-locked oscillator, and the first polarity configurable harmonic generator is connected to the injection-locked oscillator through the first injector; the second polarity configurable harmonic generator and the second injector are arranged on the other side of the injection-locked oscillator, and the second polarity configurable harmonic generator is connected to the injection-locked oscillator through the second injector.
第一极性可配置谐波发生器包括第一变压器网络和第一信号输入网络；第二极性可配置谐波发生器包括第二变压器网络和第二信号输入网络；第一变压器网络的一端连接第一信号输入网络，第一变压器网络的另一端连接第一注入器；第二变压器网络的一端连接第二信号输入网络，第二变压器网络的另一端连接第二注入器；其中第一变压器网络包括第一耦合电感L1、第二耦合电感L2、第三耦合电感L3、第四耦合电感L4、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6、第七开关S7、第八开关S8；The first polarity configurable harmonic generator includes a first transformer network and a first signal input network; the second polarity configurable harmonic generator includes a second transformer network and a second signal input network; one end of the first transformer network is connected to the first signal input network, and the other end of the first transformer network is connected to the first injector; one end of the second transformer network is connected to the second signal input network, and the other end of the second transformer network is connected to the second injector; wherein the first transformer network includes a first coupled inductor L1, a second coupled inductor L2, a third coupled inductor L3, a fourth coupled inductor L4, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8;
第一耦合电感L1的一端、第四耦合电感L4的一端分别连接电源；第一耦合电感L1的另一端、第四耦合电感L4的另一端分别连接第一信号输入网络；第二耦合电感L2的一端连接第一开关S1的一端和第四开关S4的一端，第二耦合电感L2的另一端连接第三开关S3的一端和第二开关S2的一端，第三耦合电感L3的一端连接第六开关S6的一端和第七开关S7的一端，第三耦合电感L3的另一端连接第五开关S5的一端和第八开关S8的一端；第一开关S1的另一端、第二开关S2的另一端、第五开关S5的另一端、第六开关S6的另一端连接第一注入器；第三开关S3的另一端、第四开关S4的另一端、第七开关S7的另一端、第八开关S8的另一端分别接地；One end of the first coupling inductor L1 and one end of the fourth coupling inductor L4 are connected to the power supply respectively; the other end of the first coupling inductor L1 and the other end of the fourth coupling inductor L4 are connected to the first signal input network respectively; one end of the second coupling inductor L2 is connected to one end of the first switch S1 and one end of the fourth switch S4, the other end of the second coupling inductor L2 is connected to one end of the third switch S3 and one end of the second switch S2, one end of the third coupling inductor L3 is connected to one end of the sixth switch S6 and one end of the seventh switch S7, and the other end of the third coupling inductor L3 is connected to one end of the fifth switch S5 and one end of the eighth switch S8; the other end of the first switch S1, the other end of the second switch S2, the other end of the fifth switch S5, and the other end of the sixth switch S6 are connected to the first injector; the other end of the third switch S3, the other end of the fourth switch S4, the other end of the seventh switch S7, and the other end of the eighth switch S8 are grounded respectively;
第二变压器网络包括第五耦合电感L5、第六耦合电感L6、第七耦合电感L7、第八耦合电感L8、第九开关S9、第十开关S10、第十一开关S11、第十二开关S12、第十三开关S13、第十四开关S14、第十五开关S15、第十六开关S16；The second transformer network includes a fifth coupled inductor L5, a sixth coupled inductor L6, a seventh coupled inductor L7, an eighth coupled inductor L8, a ninth switch S9, a tenth switch S10, an eleventh switch S11, a twelfth switch S12, a thirteenth switch S13, a fourteenth switch S14, a fifteenth switch S15, and a sixteenth switch S16;
第五耦合电感L5的一端、第八耦合电感L8的一端分别连接电源；第五耦合电感L5的另一端、第八耦合电感L8的另一端分别连接第二信号输入网络；第六耦合电感L6的一端连接第九开关S9的一端和第十二开关S12的一端，第六耦合电感L6的另一端连接第十开关S10的一端和第十一开关S11的一端，第七耦合电感L7的一端连接第十四开关S14的一端和第十五开关S15的一端，第七耦合电感L7的另一端连接第十三开关S13的一端和第十六开关S16的一端；第九开关S9的另一端、第十开关S10的另一端、第十三开关S13的另一端、第十四开关S14的另一端连接第二注入器；第十一开关S11的另一端、第十二开关S12的另一端、第十五开关S15的另一端、第十六开关S116的另一端分别接地。One end of the fifth coupled inductor L5 and one end of the eighth coupled inductor L8 are connected to the power supply respectively; the other end of the fifth coupled inductor L5 and the other end of the eighth coupled inductor L8 are connected to the second signal input network respectively; one end of the sixth coupled inductor L6 is connected to one end of the ninth switch S9 and one end of the twelfth switch S12, the other end of the sixth coupled inductor L6 is connected to one end of the tenth switch S10 and one end of the eleventh switch S11, one end of the seventh coupled inductor L7 is connected to one end of the fourteenth switch S14 and one end of the fifteenth switch S15, and the other end of the seventh coupled inductor L7 is connected to one end of the thirteenth switch S13 and one end of the sixteenth switch S16; the other end of the ninth switch S9, the other end of the tenth switch S10, the other end of the thirteenth switch S13, and the other end of the fourteenth switch S14 are connected to the second injector; the other end of the eleventh switch S11, the other end of the twelfth switch S12, the other end of the fifteenth switch S15, and the other end of the sixteenth switch S16 are grounded respectively.
第一信号输入网络包括第一NMOS晶体管M1、第二NMOS晶体管M2、第一电容C1、第二电容C2、第五电容C5、第一电阻R1、第二电阻R2；The first signal input network includes a first NMOS transistor M1, a second NMOS transistor M2, a first capacitor C1, a second capacitor C2, a fifth capacitor C5, a first resistor R1, and a second resistor R2;
第二信号输入网络包括第三NMOS晶体管M3、第四NMOS晶体管M4、第三电容C3、第四电容C4、第六电容C6、第三电阻R3、第四电阻R4；其中，第一NMOS晶体管M1的源极、第二NMOS晶体管M2的源极、第三NMOS晶体管M3的源极、第四NMOS晶体管M4的源极分别接地；第一NMOS晶体管M1的栅极与偏置电压之间连接第一电阻R1，第二NMOS晶体管M2的栅极与偏置电压之间连接第二电阻R2，第三NMOS晶体管M3的栅极与偏置电压之间连接第三电阻R3，第四NMOS晶体管M4的栅极与偏置电压之间连接第四电阻R4；第一NMOS晶体管M1的栅极与基波信号的正极输入端INP之间连接所述第一电容C1，第二NMOS晶体管M2的栅极与基波信号的负极输入端INN之间连接第二电容C2，第三NMOS晶体管M3的栅极与基波信号的正极输入端INP之间连接第三电容C3，第四NMOS晶体管M4的栅极与基波信号的负极输入端INN之间连接第四电容C4；第一NMOS晶体管M1的漏极与第二NMOS晶体管M2的漏极之间连接第五电容C5和第一变压器网络的一端，第三NMOS晶体管M3的漏极与第四NMOS晶体管M4的漏极之间连接第六电容C6和第二变压器网络的一端。The second signal input network includes a third NMOS transistor M3, a fourth NMOS transistor M4, a third capacitor C3, a fourth capacitor C4, a sixth capacitor C6, a third resistor R3, and a fourth resistor R4; wherein the source of the first NMOS transistor M1, the source of the second NMOS transistor M2, the source of the third NMOS transistor M3, and the source of the fourth NMOS transistor M4 are grounded respectively; the first resistor R1 is connected between the gate of the first NMOS transistor M1 and the bias voltage, the second resistor R2 is connected between the gate of the second NMOS transistor M2 and the bias voltage, the third resistor R3 is connected between the gate of the third NMOS transistor M3 and the bias voltage, and the fourth resistor R4 is connected between the gate of the fourth NMOS transistor M4 and the bias voltage; the first The first capacitor C1 is connected between the gate of the NMOS transistor M1 and the positive input terminal INP of the fundamental signal, the second capacitor C2 is connected between the gate of the second NMOS transistor M2 and the negative input terminal INN of the fundamental signal, the third capacitor C3 is connected between the gate of the third NMOS transistor M3 and the positive input terminal INP of the fundamental signal, and the fourth capacitor C4 is connected between the gate of the fourth NMOS transistor M4 and the negative input terminal INN of the fundamental signal; the fifth capacitor C5 and one end of the first transformer network are connected between the drain of the first NMOS transistor M1 and the drain of the second NMOS transistor M2, and the sixth capacitor C6 and one end of the second transformer network are connected between the drain of the third NMOS transistor M3 and the drain of the fourth NMOS transistor M4.
本发明实施例提供的一种可变倍频比的宽带注入锁定倍频器中，极性可配置谐波发生器为左右对称结构，分别将基频信号通过正极输入端INP和负极输入端INN输入，第一NMOS晶体管M1、第二NMOS晶体管M2、第三NMOS晶体管M3和第四NMOS晶体管M4栅端所接电容均起到了隔直的作用，偏置电压均通过电阻加到栅端。通过控制极性可配置谐波发生器中变压器的开关来调节变压器的耦合极性。变压器正向耦合时，极性可配置谐波发生器产生二次谐波；变压器反向耦合时，极性可配置谐波发生器将产生三次谐波。图2(a)为极性可配置谐波发生器实现二倍频时的电路原理图，图2(b)为极性可配置谐波发生器实现三倍频时的电路原理图。极性可配置谐波发生器的第一NMOS晶体管M1和第二NMOS晶体管M2产生的信号中，偶次极性相同，奇次极性相反。如图2(a)所示，变压器正向耦合时，相反的奇次谐波相互抵消，相同的偶次谐波叠加，并选出二倍频信号，从而实现二倍频比倍频；如图2(b)所示，变压器反向耦合时，相同的偶次谐波相互抵消，相反的奇次谐波相互叠加，从中选出三倍频信号，从而实现三倍频比倍频；其中，第一耦合电感L1与第二耦合电感L2耦合的耦合系数为k1，第三耦合电感L3与第四耦合电感L4耦合的耦合系数为k2，第五耦合电感L5与第六耦合电感L6耦合的耦合系数为k3，第七耦合电感L7与第八耦合电感L8耦合的耦合系数为k4。In a broadband injection-locked frequency multiplier with a variable frequency multiplication ratio provided by an embodiment of the present invention, a polarity-configurable harmonic generator is a left-right symmetrical structure, and the baseband signal is input through the positive input terminal INP and the negative input terminal INN respectively. The capacitors connected to the gate terminals of the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3 and the fourth NMOS transistor M4 all play a role of direct current isolation, and the bias voltage is added to the gate terminal through a resistor. The coupling polarity of the transformer is adjusted by controlling the switch of the transformer in the polarity-configurable harmonic generator. When the transformer is forward coupled, the polarity-configurable harmonic generator generates a second harmonic; when the transformer is reversely coupled, the polarity-configurable harmonic generator will generate a third harmonic. Figure 2 (a) is a circuit schematic diagram of the polarity-configurable harmonic generator when realizing double frequency, and Figure 2 (b) is a circuit schematic diagram of the polarity-configurable harmonic generator when realizing triple frequency. In the signals generated by the first NMOS transistor M1 and the second NMOS transistor M2 of the polarity-configurable harmonic generator, the even polarities are the same and the odd polarities are opposite. As shown in FIG2(a), when the transformer is forward coupled, opposite odd harmonics cancel each other, the same even harmonics are superimposed, and a double frequency signal is selected, thereby achieving a double frequency ratio of double frequency; as shown in FIG2(b), when the transformer is reverse coupled, the same even harmonics cancel each other, the opposite odd harmonics are superimposed, and a triple frequency signal is selected therefrom, thereby achieving a triple frequency ratio of double frequency; wherein, the coupling coefficient of the first coupling inductor L1 and the second coupling inductor L2 is k1, the coupling coefficient of the third coupling inductor L3 and the fourth coupling inductor L4 is k2, the coupling coefficient of the fifth coupling inductor L5 and the sixth coupling inductor L6 is k3, and the coupling coefficient of the seventh coupling inductor L7 and the eighth coupling inductor L8 is k4.
谐波发生器中晶体管可产生丰富的非线性信号进入振荡器，以第一NMOS晶体管M1为例，其漏极电流Id(t)可用傅里叶级数表示为如下形式：The transistors in the harmonic generator can generate rich nonlinear signals that enter the oscillator. Taking the first NMOS transistor M1 as an example, its drain current Id(t) can be expressed by Fourier series as follows:
其中ωinj为第一NMOS晶体管M1的栅极输入信号的频率，t为时间，I0、I1、I2、...In为第一NMOS晶体管M1的漏极电流各阶谐波的傅里叶系数， n代表第n 阶谐波。如图2(a)和(b)所示时，输出电压VOUT2和VOUT3可表示为：Where ω inj is the frequency of the gate input signal of the first NMOS transistor M1, t is the time, I 0 , I 1 , I 2 , ...I n are the Fourier coefficients of the harmonics of the drain current of the first NMOS transistor M1, and n represents the nth harmonic. As shown in Figures 2(a) and (b), the output voltages V OUT2 and V OUT3 can be expressed as:
； ;
其中n2/n1为第二耦合电感L2和第一耦合电感L1的匝数比，ωinj为第一NMOS晶体管M1的栅极输入信号的频率，I2为第一NMOS晶体管M1漏极电流第二阶谐波的傅里叶系数，I3为第一NMOS晶体管M1漏极电流第三阶谐波的傅里叶系数，t为时间，RL1为电感L1的内阻，L1和L2组成的变压器与L3和L4组成的变压器左右对称。由上式可知通过调节变压器的正向和反向耦合极性可以分别实现二次谐波和三次谐波电压。Where n 2 /n 1 is the turns ratio of the second coupling inductor L2 and the first coupling inductor L1, ω inj is the frequency of the gate input signal of the first NMOS transistor M1, I 2 is the Fourier coefficient of the second-order harmonic of the drain current of the first NMOS transistor M1, I 3 is the Fourier coefficient of the third-order harmonic of the drain current of the first NMOS transistor M1, t is time, RL1 is the internal resistance of the inductor L1, and the transformer composed of L1 and L2 is symmetrical with the transformer composed of L3 and L4. It can be seen from the above formula that the second harmonic and third harmonic voltages can be achieved respectively by adjusting the forward and reverse coupling polarities of the transformer.
第一注入器包括第五NMOS晶体管M5、第七电容C7和第五电阻R5；第二注入器包括第六NMOS晶体管M6、第八电容C8和第六电阻R6；第五NMOS晶体管M5的源极和第六NMOS晶体管M6的源极分别接地；第五NMOS晶体管M5的漏极连接注入锁定振荡器的一端，第六NMOS晶体管M6的漏极连接注入锁定振荡器的另一端；第五NMOS晶体管M5的栅极与偏置电压之间连接第五电阻R5，第六NMOS晶体管M6的栅极与偏置电压之间连接第六电阻R6，第五NMOS晶体管M5的栅极与第一极性可配置谐波发生器之间连接第七电容C7，第六NMOS晶体管M6的栅极与第二极性可配置谐波发生器之间连接第八电容C8。The first injector includes a fifth NMOS transistor M5, a seventh capacitor C7 and a fifth resistor R5; the second injector includes a sixth NMOS transistor M6, an eighth capacitor C8 and a sixth resistor R6; the source of the fifth NMOS transistor M5 and the source of the sixth NMOS transistor M6 are grounded respectively; the drain of the fifth NMOS transistor M5 is connected to one end of the injection locked oscillator, and the drain of the sixth NMOS transistor M6 is connected to the other end of the injection locked oscillator; the fifth resistor R5 is connected between the gate of the fifth NMOS transistor M5 and the bias voltage, the sixth resistor R6 is connected between the gate of the sixth NMOS transistor M6 and the bias voltage, the seventh capacitor C7 is connected between the gate of the fifth NMOS transistor M5 and the first polarity configurable harmonic generator, and the eighth capacitor C8 is connected between the gate of the sixth NMOS transistor M6 and the second polarity configurable harmonic generator.
注入锁定振荡器包括谐振网络、第七NMOS晶体管M7、第八NMOS晶体管M8、第九NMOS晶体管M9、第十NMOS晶体管M10、第九电容C9；第九NMOS晶体管M9的源极和第十NMOS晶体管M10的源极分别接地，第九NMOS晶体管M9的漏极连接偏置电流，第九NMOS晶体管M9的栅极分别连接偏置电流和第十NMOS晶体管M10的栅极，第十NMOS晶体管M10的漏极连接第七NMOS晶体管M7的源极和第八NMOS晶体管M8的源极，第七NMOS晶体管M7的漏极连接第八NMOS晶体管M8的栅极、第九电容C9的一端和谐振网络的一端，第八NMOS晶体管M8的漏极连接第七NMOS晶体管M7的栅极、第九电容C9的另一端和谐振网络的另一端。The injection locked oscillator includes a resonant network, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, and a ninth capacitor C9; the source of the ninth NMOS transistor M9 and the source of the tenth NMOS transistor M10 are grounded respectively, the drain of the ninth NMOS transistor M9 is connected to the bias current, the gate of the ninth NMOS transistor M9 is connected to the bias current and the gate of the tenth NMOS transistor M10 respectively, the drain of the tenth NMOS transistor M10 is connected to the source of the seventh NMOS transistor M7 and the source of the eighth NMOS transistor M8, the drain of the seventh NMOS transistor M7 is connected to the gate of the eighth NMOS transistor M8, one end of the ninth capacitor C9 and one end of the resonant network, and the drain of the eighth NMOS transistor M8 is connected to the gate of the seventh NMOS transistor M7, the other end of the ninth capacitor C9 and the other end of the resonant network.
谐振网络包括第九耦合电感L9、第十耦合电感L10、第十一耦合电感L11、第十二耦合电感L12、第十电容C10、第十一电容C11、第十二电容C12；第十一耦合电感L11的一端连接第十电容C10的一端和第十二电容C12的一端，第十二耦合电感L12的一端连接第十一电容C11的一端和第十二电容C12的另一端，第十电容C10的另一端和第十一电容C11的另一端串联，第十一耦合电感L11的另一端和第十二耦合电感L12的另一端串联；第九耦合电感L9的一端和第十耦合电感L10的一端分别连接电源，第九耦合电感L9的另一端为谐振网络的一端，第十耦合电感L10的另一端为谐振网络的另一端。The resonant network includes a ninth coupled inductor L9, a tenth coupled inductor L10, an eleventh coupled inductor L11, a twelfth coupled inductor L12, a tenth capacitor C10, an eleventh capacitor C11, and a twelfth capacitor C12; one end of the eleventh coupled inductor L11 is connected to one end of the tenth capacitor C10 and one end of the twelfth capacitor C12, one end of the twelfth coupled inductor L12 is connected to one end of the eleventh capacitor C11 and the other end of the twelfth capacitor C12, the other end of the tenth capacitor C10 and the other end of the eleventh capacitor C11 are connected in series, and the other end of the eleventh coupled inductor L11 and the other end of the twelfth coupled inductor L12 are connected in series; one end of the ninth coupled inductor L9 and one end of the tenth coupled inductor L10 are connected to a power supply respectively, the other end of the ninth coupled inductor L9 is one end of the resonant network, and the other end of the tenth coupled inductor L10 is the other end of the resonant network.
本发明实施例提供的一种可变倍频比的宽带注入锁定倍频器中，谐波信号通过注入器注入到注入锁定振荡器，注入锁定振荡器的电容和电感谐振在二次或三次谐波频率，其频带随着倍频比变化而变化。第七NMOS晶体管M7和第八NMOS晶体管M8为负阻对，用于抵消注入锁定振荡器中的寄生电阻，负阻对通过第九NMOS晶体管M9和第十NMOS晶体管M10给偏置电流，保证负阻对有足够的gm来持续震荡。对于注入锁定振荡器的LC谐振腔，其注入锁定范围为：In a broadband injection-locked frequency multiplier with a variable multiplication ratio provided by an embodiment of the present invention, a harmonic signal is injected into an injection-locked oscillator through an injector, and the capacitance and inductance of the injection-locked oscillator resonate at the second or third harmonic frequency, and its frequency band changes with the multiplication ratio. The seventh NMOS transistor M7 and the eighth NMOS transistor M8 are a negative resistance pair, which are used to offset the parasitic resistance in the injection-locked oscillator. The negative resistance pair is biased by the ninth NMOS transistor M9 and the tenth NMOS transistor M10 to ensure that the negative resistance pair has enough gm to continue to oscillate. For the LC resonant cavity of the injection-locked oscillator, its injection locking range is:
其中ω0为注入锁定振荡器的自由振荡频率，ωinj为注入信号频率，Q为谐振腔品质因数，Iinj为注入信号电流，IOSC为振荡器振荡电流。可变倍频比的谐波信号通过正极输出端OUTP和负极输出端OUTN输出，输出信号的频率为为输入基波信号频率的二倍或三倍。Where ω 0 is the free oscillation frequency of the injection locked oscillator, ω inj is the injection signal frequency, Q is the resonant cavity quality factor, I inj is the injection signal current, and I OSC is the oscillation current of the oscillator. The harmonic signal with variable frequency multiplication ratio is output through the positive output terminal OUTP and the negative output terminal OUTN, and the frequency of the output signal is twice or three times the frequency of the input fundamental signal.
基于本发明提供的可变倍频比的宽带注入锁定倍频器进行仿真实验：A simulation experiment is conducted based on the broadband injection locked frequency multiplier with variable frequency multiplication ratio provided by the present invention:
本发明仿真实验元件采用SMIC 55nm RF CMOS工艺，基于Cadence IC618仿真实验平台搭建本发明仿真电路。The simulation experiment element of the present invention adopts SMIC 55nm RF CMOS technology, and the simulation circuit of the present invention is built based on the Cadence IC618 simulation experiment platform.
本发明仿真采用Spectre RF仿真工具对本发明电路进行仿真，给定电源电压VDD为1.2 V，工作温度为27摄氏度，偏置电压VB1为0.8 V，偏置电压VB2为0.35 V。在正极输出端OUTP和负极输出端OUTN分别添加对应的输出端口，对本发明进行仿真。如图3所示为工作频率范围仿真图，其中横坐标代表输出频率（GHz），纵坐标代表输入功率（dBm），三角标曲线代表二倍频，圆形标曲线代表三倍频。从工作频率仿真结果可知，二倍频时带宽为16.2 GHz到34.4 GHz，三倍频时带宽为27 GHz到48 GHz，总带宽为16.2 GHz到48 GHz。本发明中不同倍频模式对应的频带相互重叠，等效扩大了带宽。The present invention uses the Spectre RF simulation tool to simulate the circuit of the present invention, with a given power supply voltage VDD of 1.2 V, an operating temperature of 27 degrees Celsius, a bias voltage VB1 of 0.8 V, and a bias voltage VB2 of 0.35 V. Corresponding output ports are added to the positive output terminal OUTP and the negative output terminal OUTN, respectively, to simulate the present invention. As shown in FIG3, a simulation diagram of the operating frequency range is shown, in which the abscissa represents the output frequency (GHz), the ordinate represents the input power (dBm), the triangular curve represents the double frequency, and the circular curve represents the triple frequency. From the simulation results of the operating frequency, it can be seen that the bandwidth is 16.2 GHz to 34.4 GHz when the frequency is doubled, the bandwidth is 27 GHz to 48 GHz when the frequency is tripled, and the total bandwidth is 16.2 GHz to 48 GHz. In the present invention, the frequency bands corresponding to different frequency multiplication modes overlap with each other, which is equivalent to expanding the bandwidth.
以上给出的实施例是实现本发明较优的例子，本发明不限于上述实施例。本领域的技术人员根据本发明技术方案的技术特征所做出的任何非本质的添加、替换，均属于本发明的保护范围。The above embodiments are preferred examples for implementing the present invention, and the present invention is not limited to the above embodiments. Any non-essential additions and substitutions made by those skilled in the art based on the technical features of the technical solution of the present invention shall fall within the protection scope of the present invention.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11112341A (en) * | 1997-10-08 | 1999-04-23 | Sharp Corp | Microwave/millimeter wave synchronous injection type oscillator |
| CN103219945A (en) * | 2013-04-12 | 2013-07-24 | 中国科学技术大学 | Injection locking frequency doubler with odd harmonic restraint mechanism |
| US20130328633A1 (en) * | 2012-06-08 | 2013-12-12 | Hittite Microwave Corporation | Injection Locked Pulsed Oscillator |
| US9257939B1 (en) * | 2014-08-29 | 2016-02-09 | The Board Of Regents, The University Of Texas System | Quadrature LC VCO with passive coupling and phase combining network |
| CN107093984A (en) * | 2017-04-20 | 2017-08-25 | 中国电子技术标准化研究院 | One kind injection locking frequency tripler |
| CN110784178A (en) * | 2019-10-28 | 2020-02-11 | 东南大学 | Broadband Injection Locked Frequency Multiplier |
| CN114826159A (en) * | 2022-05-12 | 2022-07-29 | 中国工程物理研究院电子工程研究所 | Novel balanced Schottky double frequency structure and using method thereof |
| CN115378365A (en) * | 2022-07-19 | 2022-11-22 | 太景科技(南京)有限公司 | Frequency multiplier circuit and frequency multiplier |
-
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- 2024-05-23 CN CN202410642048.6A patent/CN118232842B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11112341A (en) * | 1997-10-08 | 1999-04-23 | Sharp Corp | Microwave/millimeter wave synchronous injection type oscillator |
| US20130328633A1 (en) * | 2012-06-08 | 2013-12-12 | Hittite Microwave Corporation | Injection Locked Pulsed Oscillator |
| CN103219945A (en) * | 2013-04-12 | 2013-07-24 | 中国科学技术大学 | Injection locking frequency doubler with odd harmonic restraint mechanism |
| US9257939B1 (en) * | 2014-08-29 | 2016-02-09 | The Board Of Regents, The University Of Texas System | Quadrature LC VCO with passive coupling and phase combining network |
| CN107093984A (en) * | 2017-04-20 | 2017-08-25 | 中国电子技术标准化研究院 | One kind injection locking frequency tripler |
| CN110784178A (en) * | 2019-10-28 | 2020-02-11 | 东南大学 | Broadband Injection Locked Frequency Multiplier |
| CN114826159A (en) * | 2022-05-12 | 2022-07-29 | 中国工程物理研究院电子工程研究所 | Novel balanced Schottky double frequency structure and using method thereof |
| CN115378365A (en) * | 2022-07-19 | 2022-11-22 | 太景科技(南京)有限公司 | Frequency multiplier circuit and frequency multiplier |
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