CN118198081A - Photomultiplier and preparation method thereof - Google Patents

Abstract

The invention relates to a photomultiplier and a preparation method thereof. A photomultiplier includes a substrate and a plurality of grooves provided on the substrate; sequentially stacking an N-type doped semiconductor layer and a P-type doped semiconductor layer on a substrate; the trench penetrates through the P-type doped semiconductor layer to be in contact with the N-type doped semiconductor layer, a first insulating layer is arranged on the side wall of the trench, and conductive metal is filled in the center of the trench; the grooves are intersected to form a grid shape; the shallow surface layer of the P-type doped semiconductor layer is provided with a plurality of high-concentration P-type doped wells which are distributed at intervals; the surface of each high-concentration P-type doped well is provided with a light absorption region; the plurality of high-concentration P-type doped wells are connected to the quenching resistor in a one-to-one correspondence manner; each group of high-concentration P-type doped well and quenching resistor are led out together to form an anode; and a cathode is led out from the upper end of the conductive metal in the groove. The light blocking metal in the deep groove is used as the cathode extraction electrode, and the extraction electrode is not required to be additionally manufactured, so that the area of a chip is saved; while the dark count rate is reduced.

Description

Photomultiplier tube and preparation method thereof

Technical Field

The present invention relates to the field of photoelectric detectors, and in particular to a photomultiplier tube and a preparation method thereof.

Background technique

Silicon photomultiplier (SiPM) is a photoelectric detection device with photon number resolution capability. It has the characteristics of high gain, high sensitivity, low bias voltage, and no interference from magnetic fields. It is widely used in medical imaging, laser radar ranging, high-energy particle detection and other fields. As shown in Figure 1, the structure of SiPM is a surface array composed of a large number of single-photon avalanche diode (SPAD) micro-elements connected in parallel. Each micro-element is composed of a SPAD and a large resistance quenching resistor in series. When working, a reverse bias is added to the SiPM. The reverse bias is slightly greater than the breakdown voltage of the SPAD diode. At this time, there is a high electric field in the depletion layer. If a photon is incident on the depletion region, the electron absorbs the photon energy and transitions to the excitation energy level to form electrons or holes. These electrons or holes are accelerated under the action of the electric field. After collision ionization, more electron-hole pairs are formed, and finally an avalanche occurs. After the avalanche, the current in each micro-element will suddenly increase, and the voltage dropped on the quenching resistor will also suddenly increase. The current in the micro-element will instantly decrease, and the avalanche will stop. This excitation-quenching process forms an instantaneous current pulse. Since the structure and quenching resistor value of each microelement in SiPM are exactly the same, theoretically each microelement excited by photons will output the same pulse, and the current output by the parallel array is proportional to the number of excited microelements. Therefore, the number of incident photons can be calculated based on the peak value of the current.

Most of the existing SiPM structures are vertical structures, that is, the cathode and anode are located on the front and back sides of the wafer, respectively, as shown in Figure 2. The high degree of customization of this structure is not conducive to integration with the existing planar CMOS process.

To this end, the present invention is proposed.

Summary of the invention

The main purpose of the present invention is to provide a photomultiplier tube and a preparation method thereof, in which the light-blocking metal in the deep groove is used as the cathode lead-out electrode, and no additional lead-out electrode is required, thereby saving chip area; at the same time, a PIN structure is used to make a SPAD microelement, thereby reducing the dark count rate.

In order to achieve the above objectives, the present invention provides the following technical solutions.

A first aspect of the present invention provides a photomultiplier tube, which comprises a substrate and a plurality of grooves arranged on the substrate; an N-type doped semiconductor layer and a P-type doped semiconductor layer are sequentially stacked from bottom to top on the upper surface of the substrate; the groove penetrates the P-type doped semiconductor layer until it contacts the N-type doped semiconductor layer, and the sidewall of the groove is provided with a first insulating layer, and the center of the groove is filled with a conductive metal; the plurality of grooves intersect to form a grid shape;

A plurality of high-concentration P-type doped wells are arranged at intervals on the shallow surface of the P-type doped semiconductor layer, and two adjacent high-concentration P-type doped wells are isolated by the trench; the doping concentration of the high-concentration P-type doped well is greater than the doping concentration of the P-type doped semiconductor layer; and a light absorption region is arranged on the surface of each high-concentration P-type doped well;

The plurality of high-concentration P-type doped wells are connected to the quenching resistors one by one; each group of the high-concentration P-type doped wells and the quenching resistors together leads to an anode; and a cathode is led to the upper end of the conductive metal in the groove.

Therefore, the present invention uses a stacked structure of an N-type doped semiconductor layer, a P-type doped semiconductor layer and a high-concentration P-type doped well as a PIN structure. Compared with the traditional P+/N well or N+/P well junction, due to the low doping concentration of the P-type doped semiconductor layer and the high-concentration P-type doped well, the tunnel effect is reduced, making the dark count rate lower.

In addition, the metal in the groove of the present invention has multiple functions, which can block light and serve as a cathode lead-out electrode. There is no need to make additional lead-out electrodes, thus saving chip area.

At the same time, the cathode and anode (ie, cathode and anode) of the present invention are led out from the same side, which is compatible with the existing CMOS process.

On this basis, the layer structure of the photomultiplier tube or the materials used in each layer can be further improved, as listed below.

Furthermore, the substrate is a P-type silicon substrate, which has a faster integration speed.

Furthermore, the shallow layer of the high-concentration P-type doped well is a P-type heavily doped region, the doping concentration of the P-type heavily doped region is greater than the doping concentration of the high-concentration P-type doped well, and the anode is connected to the P-type heavily doped region. The P-type heavily doped region has a higher doping concentration, which can reduce the contact resistance.

Furthermore, the conductive metal in the trench is connected to the N-type doped semiconductor layer via a metal silicide layer, which can reduce the contact resistance between metal and silicon.

Furthermore, the high-concentration P-type doped well is provided with an anti-reflection layer on the surface of the light absorption region. Adding the anti-reflection layer can improve the light absorption rate, improve the photoelectric detection efficiency and the result accuracy.

Furthermore, the quenching resistor is arranged around the periphery of the high-concentration P-type doped well corresponding to it, and has two opposite free ends, one end of which is conductively connected to the high-concentration P-type doped well corresponding to it, and the other end is connected to the anode. The quenching resistor adopts such a structure to achieve the following effect: the resistance size can be adjusted by the length of the quenching resistor bypassing the high-concentration P-type doped well.

Furthermore, it also includes: a second insulating layer stacked from bottom to top on the quenching resistor, the anode is electrically connected to the quenching resistor through a contact plug penetrating the second insulating layer, and the cathode is connected to the upper end of the conductive metal in the groove through a contact plug penetrating the second insulating layer. The above design can protect the electrode and facilitate processing.

The second aspect of the present invention provides a method for preparing the photomultiplier tube of the first aspect, comprising:

providing a semiconductor substrate;

forming an N-type doped semiconductor layer on the upper surface of the semiconductor substrate;

forming a P-type doped semiconductor layer on the upper surface of the N-type doped semiconductor layer;

Etching a trench in the P-type doped semiconductor layer that penetrates to the N-type doped semiconductor layer;

A first insulating layer is formed only on the sidewalls of the trench, and a conductive metal is filled in the center;

Continue to dope P-type ions in multiple regions of the shallow layer of the P-type doped semiconductor layer to form multiple high-concentration P-type doped wells, and two adjacent high-concentration P-type doped wells are isolated by the trench;

A quenching resistor is formed one by one above each of the high-concentration P-type doped wells as a pixel unit, and a portion of the surface of each of the high-concentration P-type doped wells is used as a light absorption area;

The high-concentration P-type doped well and the quenching resistor in each pixel unit are interconnected, and the anode is led out together, and the upper end of the conductive metal in the groove is led out to the cathode.

Therefore, the present invention prepares a photomultiplier tube with low dark count rate and high integration by sequentially forming layers, the whole process is simple, the designed steps are easy to operate, and it is easier to promote and mass produce.

Furthermore, after the high-concentration P-type doping well, the method further includes: continuing to perform P-type doping in the shallow layer of the high-concentration P-type doping well to form a P-type heavily doped region, and the anode is connected to the P-type heavily doped region.

Further, the method of forming the first insulating layer includes:

The first insulating layer is formed by a thermal oxidation growth method or by a chemical vapor deposition method.

Furthermore, after forming the first insulating layer on the sidewall of the trench and before filling the conductive metal in the center of the trench, the method further includes:

A metal silicide layer is formed at the bottom of the trench.

Furthermore, it also includes: forming an anti-reflection layer on the surface of the light absorption region of the high-concentration P-type doped well.

In summary, compared with the prior art, the present invention achieves the following technical effects:

(1) The PIN structure is different from the existing technology, which reduces the tunnel effect and makes the dark count rate lower.

(2) The micro-elements are isolated by trenches, which are filled with conductive metal and contacted with the N-type buried layer through metal silicide. The conductive metal can serve as a light-blocking layer to prevent optical crosstalk and as a cathode lead-out electrode. No additional electrodes are required, which can save chip area.

(3) The cathode and anode are led out from the same side, which is compatible with the existing CMOS process.

(4) The preparation process is simple.

BRIEF DESCRIPTION OF THE DRAWINGS

Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the following detailed description of the preferred embodiment.The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the invention.

FIG1 is a circuit diagram of a SiPM;

FIG2 is a schematic diagram of a vertical structure SiPM;

FIG3 is a cross-sectional view of a photomultiplier tube provided by the present invention;

FIG4 is a top view of one of the pixel units of the photomultiplier tube shown in FIG3 (only the conductive metal is shown in the groove);

FIG. 5 is a top view of the array layout of the photomultiplier tubes shown in FIG. 3 (the ellipsis in the figure represents pixel units not shown, and the number of units is not limited).

Reference numerals:

1-substrate, 2-N-type doped semiconductor layer, 3-P-type doped semiconductor layer, 4-anti-reflection layer, 5-second insulating layer, 6-passivation layer, 7-first insulating layer, 8-conductive metal, 9-metal silicide layer, 10-high-concentration P-type doped well, 11-P-type heavily doped region, 12-contact plug, 13-light absorption region, 14-quenching resistor, 15-metal layer, 16-trench, 17-anode, 18-cathode.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions/layers with different shapes, sizes, and relative positions according to actual needs.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element or an intervening layer/element may exist between them. In addition, if a layer/element is "on" another layer/element in one orientation, the layer/element may be "below" the other layer/element when the orientation is reversed.

Since the existing photomultiplier tubes have a low degree of integration and usually have a high dark count rate, the present invention provides a photomultiplier tube. The photomultiplier tube improves the degree of integration, saves chip area, and reduces the dark count rate by changing the structural design of the PIN and the lead-out structure of the anode and cathode. The specific structure is described below.

As shown in Figures 3 to 5, a photomultiplier tube includes a substrate 1 and a plurality of grooves 16 disposed on the substrate 1; an N-type doped semiconductor layer 2 and a P-type doped semiconductor layer 3 are sequentially stacked from bottom to top on the upper surface of the substrate 1. The groove 16 penetrates the P-type doped semiconductor layer 3 until it contacts the N-type doped semiconductor layer 2, and a first insulating layer 7 is disposed on the sidewall of the groove 16, and a conductive metal 8 is filled in the center of the groove 16; the plurality of grooves 16 intersect to form a grid.

The shallow layer of the P-type doped semiconductor layer 3 is provided with a plurality of high-concentration P-type doped wells 10 distributed at intervals, and two adjacent high-concentration P-type doped wells 10 are isolated by a groove 16; the doping concentration of the high-concentration P-type doped well 10 is greater than the doping concentration of the P-type doped semiconductor layer 3; and a light absorption region 13 is provided on the surface of each high-concentration P-type doped well 10.

A plurality of high-concentration P-type doped wells 10 are connected to the quenching resistors 14 one by one; each group of high-concentration P-type doped wells 10 and quenching resistors 14 together leads to an anode; and a cathode is led to the upper end of the conductive metal 8 in the groove 16 .

In the above photomultiplier tube, the N-type doped semiconductor layer 2, the P-type doped semiconductor layer 3 and the high-concentration P-type doped well 10 are stacked to form a PIN structure, which serves as a single-photon avalanche diode; the electrode drawn out from the groove 16 is the cathode 18, and the electrode connected in series with the quenching resistor 14 and the PIN is used as the anode 17; the single-photon avalanche diode and a quenching resistor 14 are combined into a microelement; the grid-shaped groove 16 separates multiple microelements to achieve parallel connection of multiple microelements. Compared with the photomultiplier tube shown in FIG2, the photomultiplier tubes of FIGS. 3 to 5 have the following advantages: (1) Due to the low doping concentration of the P-type doped semiconductor layer 3 and the high-concentration P-type doped well 10, the tunnel effect is reduced, resulting in a lower dark count rate; (2) The metal in the groove 16 has multiple functions, which can block light and serve as the cathode 18 lead electrode, without the need to make an additional lead electrode, saving chip area; (3) The cathode 18 and the anode 17 are led out from the same side of the substrate 1, which is compatible with the existing CMOS process.

In the above photomultiplier tube provided by the present invention, the substrate 1 can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, such as silicon-on-insulator (SOI), bulk silicon, silicon carbide, germanium, silicon germanium, gallium arsenide or germanium on insulator, etc., and the corresponding top semiconductor material is silicon, germanium, silicon germanium or gallium arsenide, etc. The substrate 1 can also be a stacked structure of multiple layers of semiconductor materials. The substrate 1 can also be doped. In some embodiments, the substrate 1 is a P-type silicon substrate 1, which exhibits a faster integration speed.

In the above photomultiplier tube, a P-type heavily doped region 11 can also be set in the shallow layer of the high-concentration P-type doped well 10, and the setting method can be ion implantation or the like. The doping concentration of the P-type heavily doped region 11 is greater than the doping concentration of the high-concentration P-type doped well 10, and the P-type heavily doped region 11 is connected to the anode, which can play a role in reducing the contact resistance. That is, the P-type heavily doped region 11 doped with a higher concentration is used to connect the electrode.

The doping concentration of each P region can be adjusted appropriately according to actual needs, as long as the doping concentration of the P-type doped semiconductor layer 3 is less than the doping concentration of the high-concentration P-type doped well 10 and less than the doping concentration of the P-type heavily doped region 11. For example, in some embodiments, the doping concentration of the P-type doped semiconductor layer 3 is about 10 ¹⁶ cm ^-3 , the doping concentration of the high-concentration P-type doped well 10 is about 10 ¹⁷ cm ^-3 , and the doping concentration of the P-type heavily doped region 11 is about 10 ²⁰ cm ^-3 .

In addition, the conductive metal 8 in the groove 16 can be connected to the N-type doped semiconductor layer 2 through a metal silicide layer 9. The metal silicide layer 9 can reduce the contact resistance between the metal and silicon. The conductive metal 8 can be Al or other metal materials. The metal silicide layer 9 can be a silicide of Co, Ni, Cr, etc. The first insulating layer 7 on the side wall of the groove 16 can be a material with good insulation and easy integration such as silicon oxide, and the bottom wall of the groove 16 does not have an insulating material.

In some embodiments, in order to make the cathode 18 better in conductive contact with the N-type doped semiconductor layer 2 , the trench 16 may penetrate a portion of the depth of the N-type doped semiconductor layer 2 .

In some embodiments, the high-concentration P-type doped well 10 is provided with an anti-reflection layer 4 on the surface of the light absorption region 13. If there is no anti-reflection layer 4, the light absorption region 13 of the high-concentration P-type doped well 10 is usually its exposed surface, and adding the anti-reflection layer 4 to the exposed surface can improve the light absorption rate, improve the photoelectric detection efficiency and the accuracy of the results.

In some embodiments, as shown in FIGS. 3 to 5 , the quenching resistor 14 is disposed around the periphery of the corresponding high-concentration P-type doped well 10 and has two opposite free ends, one end of which is conductively connected to the corresponding high-concentration P-type doped well 10 and the other end is connected to the anode. The quenching resistor 14 adopts such a structure to achieve the following effect: the resistance size can be adjusted by the length of the quenching resistor 14 bypassing the high-concentration P-type doped well 10. The quenching resistor 14 can be made of polysilicon.

Furthermore, the second insulating layers 5 are stacked sequentially from bottom to top above the quenching resistor 14, the anode is electrically connected to the quenching resistor 14 through the contact plug 12 penetrating the second insulating layer 5, and the cathode is connected to the upper end of the conductive metal 8 in the groove 16 through the contact plug 12 penetrating the second insulating layer 5. The above design can protect the electrode and facilitate processing.

In addition, a passivation layer 6 is usually disposed above the second insulating layer 5 to protect the device.

The present invention also provides a method for preparing the photomultiplier tube of Figures 3 to 5, which mainly includes the following steps (introduced with reference to Figures 3 to 5).

Step S1, providing a semiconductor substrate 1, and performing corresponding treatment according to whether the substrate 1 needs to be doped or not.

Step S2, forming an N-type doped semiconductor layer 2 on the upper surface of the semiconductor substrate 1, which can be formed by depositing a new N-type doped semiconductor layer 2, or by implanting N-type ions into the shallow surface layer of the semiconductor substrate 1. The doping concentration of the N-type doped semiconductor layer 2 can be about 10 ²⁰ cm ^-3 . If a new N-type doped semiconductor layer 2 is deposited, it can be any semiconductor material, such as silicon, germanium, germanium-silicon composite, etc.

Step S3, forming a P-type doped semiconductor layer 3 on the upper surface of the N-type doped semiconductor layer 2, and a P-type epitaxial layer can be grown on a silicon wafer by vapor phase epitaxy, with a doping concentration of about 10 ¹⁶ cm ^-3 and a thickness of 5 to 10 μm.

Step S4, etching a groove 16 in the P-type doped semiconductor layer 3 that penetrates to the N-type doped semiconductor layer 2. This step can be achieved with the aid of multiple steps. For example, a silicon dioxide buffer layer and a silicon nitride layer are first grown on the P-type doped semiconductor layer 3 as a hard mask, and then a deep groove 16 is etched on the epitaxial layer using a photolithography and etching process. The depth of the groove 16 can be slightly greater than the thickness of the P-type doped semiconductor layer 3, and is in contact with the N-type doped semiconductor layer 2.

Step S5, forming the first insulating layer 7 only on the sidewalls of the trench 16. This step can be completed by any one of the following two steps.

Step S5A, SiO ₂ is filled into the trench 16 by chemical vapor deposition, and the SiO ₂ is flattened by chemical mechanical polishing. Then, the SiO ₂ filling in the center and bottom wall of the trench 16 is removed by photolithography and etching, and the bottom N-type doped semiconductor layer 2 is exposed, leaving only the SiO ₂ on the side wall.

Alternatively, in step S5B, a thin oxide layer is grown in the trench 16 by thermal oxidation, and the thermal oxide layer at the bottom of the trench 16 is removed by anisotropic etching to expose the N-type doped semiconductor layer 2 at the bottom, leaving only the sidewall layer as the first insulating layer 7.

In the next step S6, the conductive metal 8, which may be Al, may be filled into the center of the groove 16 by sputtering, and then planarized by chemical mechanical polishing, and then the sacrificial layers such as the hard mask that may be used in the previous steps may be removed by chemical etching solution.

Before step S6, a metal silicide layer 9 may be formed at the bottom of the trench 16, and the following step S6' may be adopted:

A thin layer of metal is made by sputtering, which can be Co, Ni, Cr and other metals, and then an annealing operation can be performed to allow the thin layer of metal to chemically react with the silicon at the bottom of the groove 16 to generate metal silicide. The excess metal that does not participate in the chemical reaction is then removed with a chemical etching solution. The metal silicide layer 9 formed in this way is conducive to reducing contact resistance.

Step S7, continue to dope P-type ions in multiple areas of the shallow layer of the P-type doped semiconductor layer 3 to form multiple high-concentration P-type doped wells 10, and two adjacent high-concentration P-type doped wells 10 are isolated by the trench 16, and the doping concentration can be 10 ¹⁷ cm ^-3 . In order to reduce the resistance of the P-type doped semiconductor layer 3 connecting the electrode, the predetermined light absorption area 13 (for example, the center position) of the P-type doped semiconductor layer 3 can also be doped to form a P-type heavily doped area 11, and the doping concentration can be 10 ²⁰ cm ^-3 .

Step S8, growing an anti-reflection layer 4 on the P-type doped semiconductor layer 3 by chemical vapor deposition, this step is optional.

Step S9, forming a quenching resistor 14 on each P-type heavily doped region 11 in a one-to-one correspondence as a pixel unit (i.e., microelement). The quenching resistor 14 can be arranged around the periphery of the corresponding P-type heavily doped region 11, and has two opposite free ends, one end is conductively connected to the corresponding high-concentration P-type doped well 10, and the other end is used for leading out the electrode. The material of the quenching resistor 14 can be selected from polysilicon, and the pattern thereof can be formed by means such as photolithography.

Step S10, a second insulating layer 5 is formed by chemical vapor deposition, and a plurality of contact holes are formed by photolithography and etching processes. For each pixel unit, there is a contact hole leading to the free end of the lead-out electrode of the quenching resistor 14, and a contact hole leading to the conductive metal 8 in the groove 16. Then, metal is filled into the contact hole and flattened to form a contact plug 12.

In step S11, a metal layer 15 may be sputtered on the upper end of the contact plug 12, and patterned by photolithography and etching processes, that is, an anode (i.e., anode 17) and a cathode (i.e., cathode 18) are drawn out. Since all pixel units share the N-type doped semiconductor layer, if the grooves are interconnected, it is sufficient to draw out the cathode in the groove of one pixel unit, thereby eliminating the need for complex wiring.

Step S12: forming a passivation layer 6 by chemical vapor deposition.

Step S13, using photolithography and etching processes to remove the passivation layer and the insulating layer and other layers that are not conducive to light absorption above the predetermined light absorption area 13 (usually set on the partial surface of the P-type heavily doped area 11), exposing the anti-reflection layer (if there is no anti-reflection layer, the surface of the P-type heavily doped area 11 is directly exposed).

The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims (12)

1. A photomultiplier tube comprising a substrate and a plurality of trenches disposed on the substrate; sequentially stacking an N-type doped semiconductor layer and a P-type doped semiconductor layer on the upper surface of the substrate from bottom to top; the groove penetrates through the P-type doped semiconductor layer to be in contact with the N-type doped semiconductor layer, a first insulating layer is arranged on the side wall of the groove, and the center of the groove is filled with conductive metal; the grooves are intersected to form a grid shape;

The shallow surface layer of the P-type doped semiconductor layer is provided with a plurality of high-concentration P-type doped wells distributed at intervals, and two adjacent high-concentration P-type doped wells are isolated by the groove; the doping concentration of the high-concentration P-type doping well is larger than that of the P-type doping semiconductor layer; the surface of each high-concentration P-type doped well is provided with a light absorption region;

The plurality of high-concentration P-type doped wells are connected to the quenching resistor in a one-to-one correspondence manner; each group of high-concentration P-type doped wells and the quenching resistor are led out together to form an anode; and a cathode is led out from the upper end of the conductive metal in the groove.

2. The photomultiplier tube of claim 1, wherein the substrate is a P-type silicon substrate.

3. The photomultiplier tube of claim 1, wherein the shallow surface of the high-concentration P-type doped well is a P-type heavily doped region having a doping concentration greater than that of the high-concentration P-type doped well, and the anode is connected to the P-type heavily doped region.

4. The photomultiplier tube of claim 1, wherein the conductive metal in the trench is connected to the N-doped semiconductor layer by a metal silicide layer.

5. The photomultiplier tube of any one of claims 1-4, wherein the high concentration P-type doped well is provided with an anti-reflective layer on a surface of the light absorbing region.

6. The photomultiplier tube of any one of claims 1-4, wherein the quenching resistor is disposed around the periphery of its corresponding high concentration P-doped well and has two opposite free ends, one end conductively connected to its corresponding high concentration P-doped well and the other end connected to the anode.

7. The photomultiplier of any one of claims 1-4, further comprising: and the anode is electrically connected with the quenching resistor through a contact plug penetrating through the second insulating layer, and the cathode is connected with the upper end of the conductive metal in the groove through the contact plug penetrating through the second insulating layer.

8. The method for manufacturing a photomultiplier tube according to claim 1, comprising:

Providing a semiconductor substrate;

Forming an N-type doped semiconductor layer on the upper surface of the semiconductor substrate;

forming a P-type doped semiconductor layer on the upper surface of the N-type doped semiconductor layer;

etching a groove penetrating to the N-type doped semiconductor layer in the P-type doped semiconductor layer;

Forming a first insulating layer only on the side wall of the groove, and filling conductive metal in the center;

continuing doping P-type ions in a plurality of areas of the shallow surface layer of the P-type doped semiconductor layer to form a plurality of high-concentration P-type doped wells, wherein two adjacent high-concentration P-type doped wells are isolated by the groove;

Forming quenching resistors above each high-concentration P-type doped well in a one-to-one correspondence manner, wherein the quenching resistors are used as pixel units, and part of the surface of each high-concentration P-type doped well is used as a light absorption region;

interconnecting the high-concentration P-type doped well and the quenching resistor in each pixel unit, leading out an anode together, and leading out a cathode from the upper end of the conductive metal in the groove.

9. The method of claim 8, further comprising, after the high concentration P-type doped well: and continuing to perform P-type doping on the shallow surface layer of the high-concentration P-type doping well to form a P-type heavily doped region, wherein the anode is connected with the P-type heavily doped region.

10. The method of manufacturing a photomultiplier tube according to claim 8, wherein the method of forming the first insulating layer comprises:

the first insulating layer is formed by a thermal oxidation growth method or a chemical vapor deposition method.

11. The method of manufacturing a photomultiplier tube according to claim 8, further comprising, after forming the first insulating layer on the side walls of the trench and before filling the center of the trench with a conductive metal:

And forming a metal silicide layer at the bottom of the groove.

12. The method of manufacturing a photomultiplier tube of claim 8, further comprising: and forming an anti-reflection layer on the surface of the light absorption region of the high-concentration P-type doped well.