CN118173587B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN118173587B CN118173587B CN202410311990.4A CN202410311990A CN118173587B CN 118173587 B CN118173587 B CN 118173587B CN 202410311990 A CN202410311990 A CN 202410311990A CN 118173587 B CN118173587 B CN 118173587B
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon oxide
- oxide layer
- silicon carbide
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims description 68
- 239000010410 layer Substances 0.000 claims abstract description 318
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 138
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 136
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 99
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 99
- 229910052751 metal Inorganic materials 0.000 claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 68
- 238000005530 etching Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 239000011241 protective layer Substances 0.000 claims abstract description 55
- 230000008569 process Effects 0.000 claims description 53
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 238000012545 processing Methods 0.000 claims description 13
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 10
- 229910052731 fluorine Inorganic materials 0.000 claims description 10
- 239000011737 fluorine Substances 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 239000001257 hydrogen Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000001771 vacuum deposition Methods 0.000 claims description 10
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 8
- 230000009467 reduction Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 238000005516 engineering process Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- -1 aluminum ions Chemical class 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000009489 vacuum treatment Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/62—Electrodes ohmically coupled to a semiconductor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/035—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon carbide [SiC] technology
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises a substrate, a silicon carbide layer and a grid structure, wherein the silicon carbide layer and the grid structure are sequentially arranged on the substrate, the grid structure comprises a silicon oxide layer, a grid electrode and a protective layer, the silicon oxide layer is arranged between the grid electrode and the silicon carbide layer, the protective layer wraps one side surface and the side surface of the grid electrode, which are away from the substrate, of the silicon carbide layer, a metal electrode is arranged on an area, which is not covered by the grid structure, of the silicon carbide layer, and the metal electrode and the silicon carbide layer form ohmic contact. The protective layer positioned on the side surface of the gate electrode is overlapped with the orthographic projection of the silicon oxide layer on the substrate, the edge of one side, which is away from the substrate, of the silicon oxide layer is provided with a first width, and the edge of one side, which is towards the substrate, of the silicon oxide layer is provided with a second width, and the first width is smaller than the second width, so that the damage of the silicon oxide layer between the gate electrode and the silicon carbide layer due to etching can be effectively reduced, the risk of electric leakage of the gate electrode is reduced, and the performance and the reliability of the semiconductor device are improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
In the process of manufacturing the semiconductor device, the silicon oxide layer between the gate electrode and the silicon carbide layer is easy to be damaged due to etching, so that the risk of electric leakage of the gate electrode is increased, and the performance and reliability of the semiconductor device are reduced. How to reduce the damage of the silicon oxide layer between the gate electrode and the silicon carbide layer to improve the performance and reliability of the semiconductor device is a technical problem to be solved in the art.
Disclosure of Invention
The embodiment of the invention provides a semiconductor device and a manufacturing method thereof, which are used for reducing the damage of a silicon oxide layer between a gate electrode and a silicon carbide layer, thereby improving the performance and the reliability of the semiconductor device.
In a first aspect, an embodiment of the present invention provides a semiconductor device, including a substrate, and a silicon carbide layer and a gate structure sequentially located over the substrate;
the grid structure comprises a silicon oxide layer, a grid electrode and a protective layer, wherein the silicon oxide layer is arranged between the grid electrode and the silicon carbide layer, and the protective layer wraps one side surface and the side surface of the grid electrode, which are away from the substrate, of the protective layer;
And a metal electrode is arranged on the area, which is not covered by the grid structure, of the silicon carbide layer, ohmic contact is formed between the metal electrode and the silicon carbide layer, a first width is formed on one side edge, which is away from the substrate, of the silicon oxide layer in a cross section parallel to a reference plane, a second width is formed on one side edge, which is towards the substrate, of the silicon oxide layer, the first width is smaller than the second width, and the reference plane is perpendicular to the surface of the substrate and parallel to the arrangement direction of the metal electrode and the grid structure.
In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
sequentially forming a silicon carbide layer and a silicon oxide layer on a substrate;
Forming a gate electrode over the silicon oxide layer;
forming a protective layer which wraps the gate electrode and exposes the silicon oxide layer, wherein the etching rates of the protective layer and the silicon oxide layer are different under the same etching condition; the grid structure comprises a silicon oxide layer, a grid electrode and a protective layer, wherein the protective layer positioned on the side surface of the grid electrode is overlapped with orthographic projection of the silicon oxide layer on the substrate;
Etching the exposed silicon oxide layer to reduce the thickness of the exposed silicon oxide layer, wherein the thickness of the exposed silicon oxide layer after reduction is greater than 0; then adopting siconi technology to etch the exposed silicon oxide layer after reduction so as to expose the silicon carbide layer and keep the protective layer;
And forming a metal electrode on the area, which is not covered by the grid structure, of the silicon carbide layer, wherein the metal electrode and the silicon carbide layer form ohmic contact, a first width is formed on one side edge, which is away from the substrate, of the silicon oxide layer in a cross section parallel to a reference plane, a second width is formed on one side edge, which is towards the substrate, of the silicon oxide layer, the first width is smaller than the second width, and the reference plane is perpendicular to the surface of the substrate and parallel to the arrangement direction of the metal electrode and the grid structure.
The invention has the following beneficial effects:
The semiconductor device comprises a substrate, a silicon carbide layer and a grid structure, wherein the silicon carbide layer and the grid structure are sequentially arranged on the substrate, the grid structure comprises a silicon oxide layer, a grid electrode and a protective layer, the silicon oxide layer is arranged between the grid electrode and the silicon carbide layer, the protective layer wraps one side surface and the side surface of the grid electrode, which are away from the substrate, of the silicon carbide layer, a metal electrode is arranged on an area, which is not covered by the grid structure, of the silicon carbide layer, and the metal electrode and the silicon carbide layer form ohmic contact. The reference surface is perpendicular to the surface of the substrate and parallel to the arrangement direction of the metal electrode and the grid structure, one side edge of the silicon oxide layer, which is parallel to the reference surface, is provided with a first width, one side edge of the silicon oxide layer, which is opposite to the substrate, is provided with a second width, and the first width is smaller than the second width, so that the damage of the silicon oxide layer between the grid electrode and the silicon carbide layer caused by etching can be effectively reduced, the risk of electric leakage of the grid electrode is reduced, the performance and the reliability of the semiconductor device are improved, and the process can effectively reduce the damage to the silicon carbide layer by adopting siconi when the silicon oxide layer is formed, and can effectively reduce the damage of an ohmic contact interface when the silicon carbide layer and the metal electrode form ohmic contact, and further improve the performance and the reliability of the semiconductor device.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor device provided in an embodiment of the present invention;
fig. 2 is a partial enlarged view of a gate structure of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a partial enlarged view of a gate structure of another semiconductor device provided in an embodiment of the present invention;
Fig. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Detailed Description
A specific implementation manner of a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a semiconductor device, as shown in fig. 1, comprising a substrate 100, a silicon carbide layer 200 and a gate structure S, wherein the silicon carbide layer 200 and the gate structure S are sequentially arranged on the substrate;
The grid structure S comprises a silicon oxide layer 300, a grid electrode 400 and a protective layer 500, wherein the silicon oxide layer 300 is arranged between the grid electrode 400 and the silicon carbide layer 200, and the protective layer 500 wraps one side surface and the side surface of the grid electrode 400, which are away from the substrate 100;
The silicon carbide layer 200 is provided with a metal electrode 600 over the area uncovered by the gate structure S, the metal electrode 600 forms ohmic contact with the silicon carbide layer 200, the silicon oxide layer 300 has a first width d1 on a side edge facing away from the substrate 100 in a cross section parallel to the reference plane, the silicon oxide layer 300 has a second width d2 on a side edge facing toward the substrate 100, the first width d1 is smaller than the second width d2, and the reference plane is perpendicular to the surface of the substrate 100 and parallel to the arrangement direction of the metal electrode 600 and the gate structure S, i.e. the reference plane is a plane formed by the x direction and the z direction in fig. 1.
Therefore, as the protective layer positioned on the side surface of the gate electrode is overlapped with the orthographic projection of the silicon oxide layer on the substrate, the damage of the silicon oxide layer is smaller, the electric leakage of the gate electrode is further reduced, and the performance and the reliability of the semiconductor device are improved.
It should be understood that the semiconductor device provided in the embodiment of the present application may be, but not limited to, a metal oxide semiconductor field effect transistor (i.e., MOSFET), an insulated gate bipolar transistor (i.e., IGBT), etc., as long as the semiconductor device relates to an ohmic contact and needs to reduce interface damage of the ohmic contact, which falls within the protection scope of the embodiment of the present application. The following description will take a mosfet as an example.
As shown in fig. 1, when the semiconductor device is a mosfet, the surface of the silicon carbide layer 200 away from the substrate 100 further includes a P-doped region 201, an n+ doped region 202, a p+ doped region 203, and an N-doped region 204, where the arrangement of the P-doped region 201, the n+ doped region 202, the p+ doped region 203, and the N-doped region 204 may be designed according to practical needs, and is not limited herein.
As shown in fig. 1, the structure in the region X between the broken lines may be regarded as a structure of a minimum repeating unit of the metal oxide semiconductor field effect transistor, and the structure included in the region X may be repeatedly extended to both sides.
Alternatively, as shown in fig. 1, a side surface M of the silicon oxide layer 300 in contact with the metal electrode 600 is a slope, or as shown in fig. 2, fig. 2 shows a gate structure of a semiconductor device, the side surface M of the silicon oxide layer 300 in contact with the metal electrode has a step.
The silicon oxide layer is formed by a multi-step etching method, wherein the side surface of the silicon oxide layer, which is contacted with the metal electrode, is an inclined surface, or the side surface of the silicon oxide layer, which is contacted with the metal electrode, is provided with a step. Therefore, through multi-step etching, the side surface of the silicon oxide layer, which is contacted with the metal electrode, forms an inclined plane or has a step, so that the damage to the silicon oxide layer is reduced, the electric leakage of the semiconductor device is reduced, and the performance and the reliability of the semiconductor device are improved.
Alternatively, as shown in fig. 2, the step of the silicon oxide layer 300 on the side surface in contact with the metal electrode is a first step, wherein the first step may be formed by a two-step etching method to reduce the etching steps. Thus, the process complexity of the semiconductor device can be reduced, the damage to the silicon oxide layer is reduced, and the performance and reliability of the semiconductor device are improved. Of course, the step of the silicon oxide layer on the side surface in contact with the metal electrode is not limited to the first step, but may be a second step, a third step or more steps, and may be specifically set according to actual needs, and is not limited thereto.
Optionally, the surface of the silicon carbide layer not covered by the gate structure contains hydrogen and fluorine. Thus, when the hydrogen element and the fluorine element are on the surface of the silicon carbide layer, holes and defects on the surface of the silicon carbide layer can be filled so as to passivate the defects on the surface of the silicon carbide layer, thereby reducing interface defects of ohmic contact, improving ohmic contact and improving the performance and reliability of the semiconductor device.
Alternatively, as shown in FIG. 3, which is a partial enlarged view of the semiconductor device, the silicon oxide layer 300 may be made of a material including, but not limited to, silicon oxide, the protective layer 500 may be made of a material including, but not limited to, any of silicon nitride, aluminum oxide, silicon oxide and silicon nitride disposed in a stack, silicon oxide and silicon oxynitride disposed in a stack, and silicon oxide and aluminum oxide disposed in a stack, and as shown in FIG. 3 (b), the silicon oxide in the protective layer 500 is located on a side of the silicon nitride, silicon oxynitride, or aluminum oxide facing away from the gate electrode 400.
Therefore, various film laminated layers can be arranged to form a protective layer, and the protective effect of the protective layer on the gate electrode can be improved, so that the gate electrode is prevented from being damaged in the etching process. The specific structure of the protective layer can be designed according to actual requirements, so that the requirements of different application scenes are met, and the flexibility of design is improved.
Optionally, the gate structure further includes an oxide layer disposed between the gate electrode and the protective layer. Therefore, the oxide layer can further protect the gate electrode, the gate electrode is prevented from being damaged in the etching process, and the reliability of the semiconductor device is improved.
Alternatively, the thickness of the oxide layer may be set toTo the point ofThus, the thickness of the oxide layer is set in a proper range, the gate electrode is protected while the manufacturing difficulty is reduced, the reliability of the semiconductor device can be improved, and the manufacturing efficiency of the semiconductor device can be improved.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 4, including:
s401, sequentially forming a silicon carbide layer and a silicon oxide layer on a substrate;
s402, forming a gate electrode on the silicon oxide layer;
S403, forming a protective layer which wraps the gate electrode and exposes the silicon oxide layer, wherein the etching rates of the protective layer and the silicon oxide layer are different under the same etching condition;
S404, etching the exposed silicon oxide layer to reduce the thickness of the exposed silicon oxide layer, wherein the thickness of the exposed silicon oxide layer after reduction is more than 0;
The siconi process is a pre-cleaning process, and can remove the silicon dioxide film at a low-intensity and low-rate chemical etching rate, and the specific etching process can comprise two steps, namely, a first step of performing remote plasma etching by utilizing NF 3 and NH 3, a second step of performing in-situ annealing, and a third step of performing in-situ annealing, wherein the two steps are completed in the same cavity, so that when the siconi process is adopted for etching the silicon oxide layer, two steps of reactions are required, the reaction rate is slower, the etching rate is slower and the control is easy, and the damage to the silicon carbide layer can be reduced during etching.
And S405, forming a metal electrode on the area, which is not covered by the grid structure, of the silicon carbide layer, wherein the metal electrode and the silicon carbide layer form ohmic contact, the silicon oxide layer has a first width on one side edge, which is away from the substrate, in a cross section parallel to the reference plane, and a second width on one side edge, which is towards the substrate, of the silicon oxide layer, wherein the first width is smaller than the second width, and the reference plane is perpendicular to the surface of the substrate and parallel to the arrangement direction of the metal electrode and the grid structure.
Therefore, as the etching time and the etching speed are lower by adopting the siconi process, the damage of the silicon oxide layer between the gate electrode and the silicon carbide layer caused by etching can be effectively reduced, the risk of electric leakage of the gate electrode is reduced, and the performance and the reliability of the semiconductor device are improved; in addition, the siconi process can also effectively reduce the damage to the silicon carbide layer, and further can effectively reduce the damage of an ohmic contact interface when the silicon carbide layer and the metal electrode form ohmic contact, thereby improving the performance and the reliability of the semiconductor device. And, through reducing the thickness of the silicon oxide layer exposed first and then adopting siconi technology to etch, the etching efficiency of the silicon oxide layer can be improved, thereby improving the manufacturing efficiency of the semiconductor device.
Optionally, in the step S404, the exposed silicon oxide layer is subjected to an etching process to reduce the thickness of the exposed silicon oxide layer, which may include reducing the thickness of the exposed silicon oxide layer by dry etching or wet etching. The dry etching and the wet etching may be performed by a process known to those skilled in the art, and are not limited thereto.
Therefore, the thickness of the exposed silicon oxide layer is reduced by adopting dry etching or wet etching, so that the silicon oxide layer to be etched is thinner when the siconi process is adopted for etching later, the etching efficiency is improved, and the manufacturing efficiency of the semiconductor device is further improved.
Alternatively, the thickness of the thinned exposed silicon oxide layer may beTo the point ofTherefore, the silicon carbide layer can be prevented from being etched due to the fact that the thickness of the residual silicon oxide layer is too thin, and the time required for etching by adopting a siconi process due to the fact that the thickness of the residual silicon oxide layer is too thick can be prevented, so that the thickness of the residual silicon oxide layer is controlled within a proper range, the manufacturing efficiency of a semiconductor device is improved, and damage of an ohmic contact interface can be reduced.
Optionally, after the siconi process is adopted to etch the exposed silicon oxide layer after the reduction, the surface of the exposed silicon carbide layer contains hydrogen element and fluorine element, the atomic percentage content of the hydrogen element in the surface of the silicon carbide layer is 0.5 to 1.5 percent, and the atomic percentage content of the fluorine element in the surface of the silicon carbide layer is 0.5 to 1.5 percent.
The siconi process adopts NF 3 and NH 3 to carry out remote plasma etching, so that hydrogen and fluorine remain on the surface of the silicon carbide layer, and holes and defects on the surface of the silicon carbide layer can be filled with the hydrogen and fluorine when the hydrogen and fluorine are on the surface of the silicon carbide layer, so that the defects on the surface of the silicon carbide layer can be passivated. And, based on the etching characteristics of siconi process, the depth of the hydrogen element and the fluorine element entering the silicon carbide layer is generallyTo the point ofTherefore, the hydrogen element or the fluorine element basically acts on the surface of the silicon carbide layer to reduce the defects of the surface of the silicon carbide layer, thereby further reducing the interface defects of ohmic contact and further improving the performance and the reliability of the semiconductor device.
Optionally, performing etching treatment on the thinned exposed silicon oxide layer by adopting siconi technology, and forming a metal electrode on the exposed silicon carbide layer, including:
The vacuum reaction equipment comprises a vacuum etching cavity, a vacuum coating cavity and a vacuum processing cavity, wherein a first vacuum transferring cavity is arranged between the vacuum etching cavity and the vacuum coating cavity, and a second vacuum transferring cavity is arranged between the vacuum coating cavity and the vacuum processing cavity:
etching the cut bare silicon oxide layer in the vacuum etching cavity by adopting siconi technology to obtain a first treated piece;
Transferring the first treatment piece into a vacuum coating cavity through a first vacuum transferring cavity, forming a metal layer on the surface of the first treatment piece, and covering the exposed silicon carbide layer and the protective layer with the metal layer to obtain a second treatment piece;
Transferring the second treatment piece into the vacuum treatment cavity through the second vacuum transfer cavity, and performing heat treatment on the second treatment piece to enable the metal layer covering the exposed silicon carbide layer to form ohmic contact with the silicon carbide layer;
and etching the metal layer to etch away the metal layer covering the protective layer, reserving the metal layer covering the silicon carbide layer, and forming a metal electrode by the reserved metal layer.
The first processing piece is always in the vacuum environment and is not in contact with the external environment in the process of transferring the first processing piece into the vacuum coating cavity through the first vacuum transferring cavity, and is always in the vacuum environment and is not in contact with the external environment in the process of transferring the second processing piece into the vacuum processing cavity through the second vacuum transferring cavity. Therefore, the whole process of forming the ohmic contact is completed in a vacuum environment, so that the contact with oxygen in the air is avoided, the oxidation of an ohmic contact interface is avoided, the problem that the ohmic contact fails due to oxidation is solved, and the reliability of the ohmic contact and the performance of a semiconductor device are improved.
The material for forming the metal electrode may be, but not limited to, other metal materials including nickel, aluminum, copper, gold, titanium, etc., and specifically may be selected depending on factors such as the material for forming the silicon carbide layer, and is not particularly limited herein.
Optionally, in conjunction with the structure shown in FIG. 1, the fabrication method further includes forming an oxide layer 700 on the surface of the gate electrode 400 facing away from the silicon carbide layer 200 and on the sides of the gate electrode 400 using a thermal oxidation process prior to forming the protective layer 500. Before the protective layer 500 is formed, the silicon oxide layer 300 is not etched, the gate electrode 400 is disposed above the silicon oxide layer 300, and no other film layer is disposed on a surface and a side surface of the gate electrode 400 facing away from the substrate 100, at this time, the oxide layer 700 may be formed only on a surface and a side surface of the gate electrode 400 facing away from the substrate 100 by a thermal oxidation process, and other positions may not be oxidized due to the silicon oxide layer 300.
Therefore, the oxide layer can be formed on the surface and the side surface of the gate electrode through a simple process, the manufacturing difficulty of the semiconductor device is reduced, the damage of the surface and the side surface of the gate electrode caused by etching can be eliminated through the oxide layer, and the stability of the semiconductor device is improved.
Further, the thickness of the oxide layer may beTo the point ofTherefore, the damage caused by etching due to the fact that the oxide layer is too thin can be avoided from being effectively improved, the situation that the thermal oxidation time is too long due to the fact that the oxide layer is too thick can also be avoided, and accordingly the thickness of the oxide layer is set in a proper range, stability of the semiconductor device can be improved, and manufacturing efficiency of the semiconductor device can be improved.
Optionally, when the oxide layer and the silicon oxide layer are made of the same material, the oxide layer is located between the gate electrode and the protective layer. Therefore, when the silicon oxide layer is etched, the protection layer can protect the oxide layer and the gate electrode at the same time, so that the oxide layer is prevented from being etched by etching the silicon oxide layer, further, the damage to the gate electrode is prevented, the structural integrity of the oxide layer and the gate electrode is ensured, the manufacturing yield of the semiconductor device is improved, and the performance of the manufactured semiconductor device can be improved.
Of course, the materials for forming the oxide layer and the silicon oxide layer may be different, and in this case, the oxide layer may be provided between the gate electrode and the protective layer, so that the oxide layer and the gate electrode are effectively protected by the protective layer.
Optionally, forming the protective layer includes:
Depositing a dielectric layer on the substrate with the gate electrode, wherein the dielectric layer wraps the gate electrode and covers the silicon oxide layer exposed by the gate electrode;
And etching the dielectric layer by adopting a plasma etching process, so that the dielectric layer wrapping the gate electrode remains, and the dielectric layer covering the exposed silicon oxide layer is etched to form a protective layer.
The dielectric layer may be, but is not limited to, any of silicon nitride, aluminum oxide, stacked silicon oxide and silicon nitride, stacked silicon oxide and silicon oxynitride, and stacked silicon oxide and aluminum oxide described in the foregoing. Therefore, the dielectric layer covering the exposed silicon oxide layer is etched, the dielectric layer wrapping the gate electrode is reserved, and a protective layer is further formed, so that the gate electrode and the oxide layer are protected, and the gate electrode and the oxide layer are prevented from being damaged in the etching process.
The method for manufacturing the semiconductor device according to the embodiment of the invention will be explained below with reference to specific embodiments, in which the semiconductor device is used as a mosfet.
Referring to fig. 5, a specific manufacturing process may include:
S1, as shown in fig. 5 (a), a silicon carbide layer is formed on a substrate by an epitaxial technique, wherein the size of the substrate may be, but not limited to, 4 inches, 6 inches, 8 inches, etc., and may be specifically selected according to actual needs, and is not specifically limited herein.
S2, as shown in (b) of FIG. 5, a P-doped region 201, an N+ doped region 202, a P+ doped region 203 and an N-doped region 204 are respectively formed on the surface of the silicon carbide layer, which is away from the substrate, wherein the N+ doped region 202 and the P+ doped region 203 are positioned in the P-doped region 201, the P+ doped region 203 is positioned between two adjacent N+ doped regions 202, and the N-doped region 204 is positioned between two adjacent P-doped regions 201.
The specific process for forming the P-doped region comprises the steps of firstly cleaning the surface of the silicon carbide layer, then forming a first mask layer with a preset pattern on the surface of one side of the silicon carbide layer far away from the substrate, and implanting aluminum ions into the exposed region of the first mask layer by adopting an ion implantation method so as to form the P-doped region.
Wherein, forming the first mask layer with the predetermined pattern may specifically include:
Depositing silicon nitride on the surface of the silicon carbide layer and taking the silicon nitride as an etching barrier layer, preparing a layer of silicon oxide on the surface of the etching barrier layer by adopting a PECVD (PLASMA ENHANCED CHEMICAL Vapor Deposition) method and taking the silicon oxide as a first mask layer, forming photoresist on the surface of the first mask layer, carrying out patterning treatment on the photoresist to obtain photoresist with a preset pattern, etching the exposed area of the photoresist, and transferring the preset pattern into the first mask layer to form the first mask layer with the preset pattern.
The specific process of forming the N+ doped region can include cleaning the surface of the structure where the P-doped region is formed, forming a second mask layer having a predetermined pattern in a similar manner to the first mask layer, and implanting nitrogen ions into the exposed region of the second mask layer by ion implantation to form the N+ doped region.
The specific process of forming the P+ doped region comprises the steps of firstly cleaning the surface of a structure for forming the N+ doped region, then forming a third mask layer with a preset pattern by using polysilicon in a similar manner to the first mask layer, and implanting aluminum ions into the region exposed by the third mask layer by using an ion implantation method so as to form the P+ doped region.
The specific process of forming the N-doped region may include cleaning the surface of the structure where the P+ doped region is formed, forming a fourth mask layer having a predetermined pattern in a similar manner to the first mask layer, and implanting nitrogen ions into the exposed region of the fourth mask layer by ion implantation to form the N-doped region. Of course, the N-doped region may also be formed prior to forming the P-doped region, as not limited herein.
The first to third mask layers may not be removed immediately after each ion implantation, but may be removed uniformly after the ion implantation is completed by using the fourth mask layer, so that the process can be simplified, and the corresponding mask layers may be removed after each ion implantation, which is not limited herein.
In addition, after the P-doped region, the N+ doped region, the P+ doped region and the N-doped region are formed, the doped regions are subjected to activation annealing, and the specific process of activation annealing comprises the steps of firstly cleaning the surface of the silicon carbide layer, then depositing a carbon film on the surface of one side of the silicon carbide layer far away from the substrate, then performing high-temperature annealing, and finally removing the carbon film. Wherein, the carbon film can prevent carbon precipitation in the silicon carbide layer during high-temperature annealing, thereby protecting the silicon carbide layer.
S3, as shown in fig. 5 (c), a silicon oxide layer 300 and a gate electrode are sequentially formed on the surface of the silicon carbide layer on the side facing away from the substrate.
The process of fabricating the silicon oxide layer and the gate electrode may include cleaning the surface of the silicon carbide layer, forming a whole silicon oxide layer on a surface of the silicon carbide layer far from the substrate by a thermal oxidation process, forming a whole polysilicon layer on the silicon oxide layer by an LPCVD (Low Pressure Chemical Vapor Deposition ) process, forming a fifth mask layer having a predetermined pattern in a similar manner to the first mask layer, and finally etching the exposed polysilicon layer of the fifth mask layer to the silicon oxide layer, thereby forming the gate electrode while the polysilicon remains without etching.
S4, as shown in fig. 5 (d), an oxide layer 700 and a protective layer 500 are formed.
The specific process of forming the oxide layer may include forming an oxide layer on a side surface and a side surface of the gate electrode facing away from the substrate using a thermal oxidation process.
The specific process of forming the protective layer comprises the steps of adopting a CVD (Chemical Vapor Deposition) process to deposit a whole layer of silicon nitride so that the silicon nitride covers the oxide layer and the silicon oxide layer, then adopting a plasma etching process to etch the silicon nitride until the silicon oxide layer is etched, and forming a groove between two adjacent gate electrodes, wherein the etching rate in the groove is higher than that of other positions, so that the silicon nitride in the groove is etched firstly, the silicon nitride in other positions is not completely etched at the moment, silicon nitride with a certain thickness can be reserved on the surface and the side surface of the gate electrode, which are away from the substrate, and the silicon nitride on the silicon oxide layer is etched, so that the protective layer which wraps the gate electrode and exposes the silicon oxide layer is formed.
The process of forming the protective layer is also called as a Spacer process, that is, when silicon nitride is deposited, the deposition thickness of the silicon nitride on the surface of the gate electrode is larger than the deposition thickness of the silicon nitride in the trench, and when plasma etching is performed, plasma is more likely to gather in the trench, and then the etching speed of the silicon nitride in the trench is higher than that of the silicon nitride on the surface of the gate electrode, so that the silicon nitride at the bottom of the trench can be completely etched, and the silicon nitride with a certain thickness is reserved on the surface and the side surface of the gate electrode to form the protective layer. Therefore, the Spacer process is adopted, a mask plate is not required to be manufactured, and photoetching is not required, so that the manufacturing process is simplified, the manufacturing efficiency of the semiconductor device is improved, and the manufacturing cost is reduced.
S5, as shown in fig. 5 (e) and (f), the exposed silicon oxide layer 300 is etched.
The specific process can comprise the following two steps:
And step one, adopting a wet etching process or a dry etching process to reduce the thickness of the exposed silicon oxide layer.
And secondly, etching the thinned exposed silicon oxide layer in the vacuum etching cavity by adopting a siconi process, so as to expose the silicon carbide layer, and obtaining the first processing piece.
Therefore, the silicon oxide layer can be etched through the two steps, so that the etching speed can be increased, the damage of the etching to the surface of the silicon carbide layer can be reduced, the reliability of ohmic contact is further improved when ohmic contact is formed, and the performance of the semiconductor device is improved.
S6, as shown in fig. 5 (g), a metal electrode 600 is formed.
The method comprises the steps of transferring a first treatment piece to a vacuum coating cavity through a first vacuum transferring cavity, depositing a metal layer on the surface of one side, far away from a substrate, of the first treatment piece, wherein the metal layer covers the exposed silicon carbide layer and covers a protective layer, so that a second treatment piece is obtained, transferring the second treatment piece to the vacuum treatment cavity through the second vacuum transferring cavity, conducting high-temperature annealing to enable the metal layer covering the exposed silicon carbide layer to form ohmic contact with the silicon carbide layer, and finally enabling the metal layer covering the protective layer to be etched through a wet etching process, retaining the metal layer covering the silicon carbide layer, and enabling the retained metal layer to form a metal electrode.
It should be appreciated that after the ohmic contact is formed, elements in the silicon carbide layer may enter the metal layer in contact with the silicon carbide layer, and the material of the metal layer at other positions may remain unchanged, so that the material forming the ohmic contact metal layer is different from the material at other positions, and thus the metal layer at other positions may be etched while the metal layer in contact with the silicon carbide layer may remain. In addition, in the drawings of the present invention, only the shape of the side face M of the silicon oxide layer in contact with the metal electrode is shown in fig. 1 and 2, and neither of fig. 3 and 5 is shown.
Thus, the semiconductor device can be manufactured through steps S1 to S6, and the semiconductor device manufactured by the manufacturing method has the following advantages:
1. By reducing the thickness and etching the silicon oxide layer by adopting siconi process, the side surface of the silicon oxide layer contacted with the metal electrode is less damaged, the electric leakage of the gate electrode is reduced, and the performance and the reliability of the semiconductor device are improved
2. Oxidation of an ohmic contact interface is reduced, the purity of ohmic contact is guaranteed, potential barriers are reduced, and the performance of the semiconductor device is improved;
3. When the siconi process is adopted to etch the silicon oxide layer, the damage to the silicon carbide layer can be reduced, so that the reliability of ohmic contact is improved when ohmic contact is formed, and the performance of the semiconductor device is improved;
4. the oxide layer can eliminate damages on the surface and the side surface of the gate electrode caused by etching, so that the stability of the semiconductor device is enhanced;
5. And a Spacer process is adopted when the protective layer is etched, a mask layer is not required to be manufactured, and photoetching is not required, so that the manufacturing process is simplified, the manufacturing efficiency of the semiconductor device is improved, and the manufacturing cost is reduced.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. A semiconductor device is characterized by comprising a substrate, a silicon carbide layer and a grid structure, wherein the silicon carbide layer and the grid structure are sequentially arranged on the substrate;
the grid structure comprises a silicon oxide layer, a grid electrode and a protective layer, wherein the silicon oxide layer is arranged between the grid electrode and the silicon carbide layer, and the protective layer wraps one side surface and the side surface of the grid electrode, which are away from the substrate, of the protective layer;
A metal electrode is arranged on the area, which is not covered by the grid structure, of the silicon carbide layer, and the metal electrode and the silicon carbide layer form ohmic contact, wherein in the section of the silicon oxide layer parallel to a reference surface, one side edge, which is away from the substrate, of the silicon oxide layer is provided with a first width, one side edge, which is towards the substrate, of the silicon oxide layer is provided with a second width, the first width is smaller than the second width, and the reference surface is perpendicular to the surface of the substrate and parallel to the arrangement direction of the metal electrode and the grid structure;
Wherein, the side surface of the silicon oxide layer, which is contacted with the metal electrode, is provided with a step.
2. The semiconductor device according to claim 1, wherein the step is a one-stage step.
3. The semiconductor device according to claim 1, wherein a surface of the silicon carbide layer not covered by the gate structure contains a hydrogen element and a fluorine element.
4. The semiconductor device according to claim 1, wherein the protective layer is made of a material including any one of silicon nitride, aluminum oxide, silicon oxide and silicon nitride provided in a stacked layer, silicon oxide and silicon oxynitride provided in a stacked layer, and silicon oxide and aluminum oxide provided in a stacked layer, and silicon oxide in the protective layer is located on a side of the silicon nitride, the silicon oxynitride, or the aluminum oxide facing away from the gate electrode.
5. The semiconductor device of any one of claims 1-4, wherein the gate structure further comprises an oxide layer disposed between the gate electrode and the protective layer.
6. The semiconductor device according to claim 5, wherein the oxide layer has a thickness ofTo the point of
7. A method of fabricating a semiconductor device, comprising:
sequentially forming a silicon carbide layer and a silicon oxide layer on a substrate;
Forming a gate electrode over the silicon oxide layer;
forming a protective layer which wraps the gate electrode and exposes the silicon oxide layer, wherein the etching rates of the protective layer and the silicon oxide layer are different under the same etching condition; the grid structure comprises a silicon oxide layer, a grid electrode and a protective layer, wherein the protective layer positioned on the side surface of the grid electrode is overlapped with orthographic projection of the silicon oxide layer on the substrate;
Etching the exposed silicon oxide layer to reduce the thickness of the exposed silicon oxide layer, wherein the thickness of the exposed silicon oxide layer after reduction is greater than 0; then adopting siconi technology to etch the exposed silicon oxide layer after reduction so as to expose the silicon carbide layer and keep the protective layer;
Forming a metal electrode on a region, which is not covered by the grid structure, of the silicon carbide layer, wherein the metal electrode and the silicon carbide layer form ohmic contact, a first width is formed on one side edge, which is away from the substrate, of the silicon oxide layer in a section parallel to a reference surface, a second width is formed on one side edge, which is towards the substrate, of the silicon oxide layer, the first width is smaller than the second width, the reference surface is perpendicular to the surface of the substrate and parallel to the arrangement direction of the metal electrode and the grid structure, and a step is formed on the side surface, which is in contact with the metal electrode, of the silicon oxide layer.
8. The method according to claim 7, wherein the thickness of the exposed silicon oxide layer after the reduction isTo the point of
9. The method of claim 7 or 8, wherein etching the thinned exposed silicon oxide layer and forming a metal electrode on the exposed silicon carbide layer by siconi process comprises:
The vacuum reaction equipment comprises a vacuum etching cavity, a vacuum coating cavity and a vacuum processing cavity, wherein a first vacuum transferring cavity is arranged between the vacuum etching cavity and the vacuum coating cavity, and a second vacuum transferring cavity is arranged between the vacuum coating cavity and the vacuum processing cavity:
Etching the exposed silicon oxide layer after reduction by adopting the siconi process in the vacuum etching cavity to obtain a first processing piece;
Transferring the first treatment piece into the vacuum coating cavity through the first vacuum transferring cavity, forming a metal layer on the surface of the first treatment piece, wherein the metal layer covers the exposed silicon carbide layer and the protective layer to obtain a second treatment piece;
Transferring the second processing piece into the vacuum processing cavity through the second vacuum transferring cavity, and performing heat treatment on the second processing piece so that the metal layer covering the exposed silicon carbide layer and the silicon carbide layer form ohmic contact;
And etching the metal layer to etch away the metal layer covering the protective layer, reserving the metal layer covering the silicon carbide layer, and forming the metal electrode by the reserved metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410311990.4A CN118173587B (en) | 2024-03-14 | 2024-03-14 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410311990.4A CN118173587B (en) | 2024-03-14 | 2024-03-14 | Semiconductor device and method for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118173587A CN118173587A (en) | 2024-06-11 |
| CN118173587B true CN118173587B (en) | 2025-01-14 |
Family
ID=91349979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410311990.4A Active CN118173587B (en) | 2024-03-14 | 2024-03-14 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118173587B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009032919A (en) * | 2007-07-27 | 2009-02-12 | Sumitomo Electric Ind Ltd | Oxide field effect transistor and manufacturing method thereof |
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
| CN115769380A (en) * | 2020-04-22 | 2023-03-07 | 沃孚半导体公司 | Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115377181A (en) * | 2021-05-21 | 2022-11-22 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
-
2024
- 2024-03-14 CN CN202410311990.4A patent/CN118173587B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009032919A (en) * | 2007-07-27 | 2009-02-12 | Sumitomo Electric Ind Ltd | Oxide field effect transistor and manufacturing method thereof |
| CN101740338A (en) * | 2008-11-24 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Method for removing film |
| CN115769380A (en) * | 2020-04-22 | 2023-03-07 | 沃孚半导体公司 | Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118173587A (en) | 2024-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102290350B (en) | Utilize the trench MOS barrier Schottky rectifier with flat surfaces of CMP technology | |
| CN109742148B (en) | Silicon carbide UMOSFET device and preparation method thereof | |
| US20170229557A1 (en) | Method for manufacturing semiconductor device | |
| JP2010171417A (en) | Semiconductor device | |
| TWI527096B (en) | MOS transistor and method of forming same | |
| JP7555467B2 (en) | Semiconductor device manufacturing method | |
| JP2010171418A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| TW200901386A (en) | Method for fabricating semiconductor device | |
| TWI759878B (en) | Semiconductor device and manufacturing method thereof | |
| US20070155079A1 (en) | Gate structure of semiconductor device and method of manufacturing the same | |
| KR101088207B1 (en) | Manufacturing Method of Semiconductor Device | |
| CN112185890B (en) | Semiconductor device preparation method and semiconductor device | |
| CN118173587B (en) | Semiconductor device and method for manufacturing the same | |
| JP2007311547A (en) | Manufacturing method of semiconductor device | |
| JP2021082689A (en) | Silicon carbide semiconductor device, and method for manufacturing the same | |
| CN114512403B (en) | Manufacturing method of semiconductor device | |
| US20050059211A1 (en) | Method of manufacturing semiconductor device | |
| CN103219395B (en) | Multi-trench termination structure for semiconductor element and method of making same | |
| CN113675078A (en) | Method of forming a MOS device | |
| JP2014241426A (en) | Semiconductor device | |
| CN113327848B (en) | Flash memory device and method of manufacturing the same | |
| CN114256150B (en) | Method for forming semiconductor structure | |
| CN222638984U (en) | Silicon carbide device | |
| JP7294156B2 (en) | Semiconductor device manufacturing method | |
| JP2009152392A (en) | Semiconductor device manufacturing method and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |