CN118170594A - Method, device and medium for testing equipment link loop - Google Patents
Method, device and medium for testing equipment link loop Download PDFInfo
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Abstract
The invention discloses a method, a device and a medium for testing loop back of a device link, which are applied to the technical field of loop back testing. In the method, the loop test jig compares the test data with the returned data to obtain the current error rate. And if the obtained current error rate is not higher than the preset signal margin value, judging that the signal channel of the PCIe equipment is qualified. If the obtained current error rate is higher than the signal margin value, updating a preset curve value through an adaptive correction algorithm at the moment; and finally, writing the new preset curve value into a register of the PCIe equipment, and returning to the step of sending test data to the PCIe equipment. Compared with the original scheme, the scheme not only can detect the transmitted test data and the return data, but also can adjust parameters of PCIe equipment according to detection results, so that the situation that the error rate is high when the PCIe equipment channel transmits data is improved, further the accuracy of loop test of the PCIe equipment is improved, and misjudgment is avoided.
Description
Technical Field
The present invention relates to the field of loop testing technologies, and in particular, to a method, an apparatus, and a medium for testing a loop of a device link.
Background
In order to ensure performance and reliability of peripheral component interconnect express (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIe) devices, it is critical to conduct various tests prior to system integration and device production. Loop-back testing is a common method used in testing PCIe devices to detect the performance and reliability of the device in sending and receiving data. Currently, in the process of performing loop-back testing, in order to evaluate the transmission capability of equipment without involving other system components, a signal sent by a loop-back testing jig is directly returned to a receiving end, and then the sent test data and the returned data are compared to obtain a test result.
Therefore, the original scheme only detects the transmitted test data and the returned data, and does not adjust the parameters of the PCIe device to be tested, but different PCIe devices have different characteristics, and if the parameters of the PCIe device are not optimal parameters in the current test process, the error rate between the transmitted data and the returned data is higher. That is, the current scheme cannot adapt to the characteristics of the PCIe device to realize detection, so that the test result is misjudged.
It can be seen that how to improve the accuracy of loop-back testing of PCIe devices is a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method, a device and a medium for testing loop back of a device link, so as to solve the problem of misjudgment when loop back test is carried out on PCIe devices.
In order to solve the technical problems, the invention provides a testing method for loop back of an equipment link, which is applied to a loop back testing jig connected with quick peripheral component interconnection equipment; the method comprises the following steps:
Sending test data to the rapid peripheral component interconnect device;
Receiving return data sent by the rapid peripheral component interconnect device;
comparing the test data with the return data to obtain a current error rate;
if the obtained current error rate is not higher than a preset signal margin value, judging that a signal channel of the rapid peripheral component interconnection equipment is qualified;
If the obtained current error rate is higher than the signal margin value, updating a preset curve value through an adaptive correction algorithm; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between the current error rate and the signal margin value and a history adjustment influence function;
Writing the new preset curve value into a register of the rapid peripheral component interconnection equipment, and returning the test data to the rapid peripheral component interconnection equipment.
In one aspect, if the obtained current error rate is higher than the signal margin value, updating the preset curve value through the adaptive correction algorithm includes:
Determining the error rate difference between the current error rate and the signal margin value;
Determining a first adjustment amount according to the error rate difference value and a preset scale factor and a nonlinear adjustment factor; wherein the scaling factor is used for adjusting the first adjustment amount based on the error rate difference value, and the nonlinear adjustment factor is used for adjusting the sensitivity of the first adjustment amount to the error rate difference value;
Constructing the history adjustment influence function;
Determining a second adjustment amount according to the history adjustment influence function and a preset history adjustment weight factor; the history adjustment weight factors are used for adjusting the influence degree of history adjustment data on the new preset curve values;
acquiring the current preset curve value;
Calling the self-adaptive correction algorithm to obtain a new preset curve value according to the current preset curve value, the first adjustment amount and the second adjustment amount;
Wherein the adaptive correction algorithm comprises:
Presetnew＝Presetcurrent-α×tanh(β×ΔBER)+γ×H(Presethistory)；
Preset new is the new Preset curve value, preset current is the current Preset curve value, ΔBER is the error rate difference, α is the scaling factor, β is the nonlinear adjustment factor, γ is the history adjustment weight factor, and H (Preset history) is the history adjustment influence function.
In another aspect, the history adjustment influence function includes:
Wherein Preseti is a preset curve value of the ith iteration, wi is a weight of the ith iteration, and k is the number of historical adjustment times.
On the other hand, the weight of the previous iteration is larger than that of the next iteration in the history adjustment influence function.
On the other hand, after the step of writing the new preset curve value into the register of the peripheral component interconnect express device and returning the sending test data to the peripheral component interconnect express device, the method further includes:
Acquiring the update times of the preset curve value;
comparing the update times of the preset curve value and the preset value;
and if the update times of the preset curve value exceeds the preset value and the obtained current error rate is still higher than the preset signal margin value, judging that the signal channel of the quick peripheral component interconnection equipment is unqualified.
On the other hand, if the obtained current error rate is higher than the signal margin value, updating the preset curve value through the adaptive correction algorithm includes:
and if the obtained current error rate is higher than the signal margin value, updating the pre-emphasis parameter and the equalization parameter of the quick peripheral component interconnection equipment through the self-adaptive correction algorithm.
In another aspect, after receiving the return data sent by the peripheral component interconnect express device, the method further includes:
acquiring the data state of the returned data;
Generating diagnostic information according to the acquired data state; wherein the diagnostic information includes: the number and frequency of data errors, the distribution of the channels of the errors, the integrity and correctness of the data packets, and the signal quality.
In order to solve the technical problems, the invention also provides a device for testing the loop of the equipment link, which is applied to a loop testing jig connected with the quick peripheral component interconnection equipment; the device comprises:
The sending module is used for sending the test data to the quick peripheral component interconnection equipment;
The receiving module is used for receiving the return data sent by the rapid peripheral component interconnection equipment;
The comparison module is used for comparing the test data with the return data to obtain the current error rate;
The judging module is used for judging that the signal channel of the rapid peripheral component interconnection equipment is qualified if the obtained current error rate is not higher than a preset signal margin value;
The updating module is used for updating a preset curve value through an adaptive correction algorithm if the obtained current error rate is higher than the signal margin value; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between the current error rate and the signal margin value and a history adjustment influence function;
And the writing module is used for writing the new preset curve value into a register of the quick peripheral component interconnection equipment and triggering the sending module.
On the other hand, the updating module is specifically configured to determine the error rate difference between the current error rate and the signal margin value;
Determining a first adjustment amount according to the error rate difference value and a preset scale factor and a nonlinear adjustment factor; wherein the scaling factor is used for adjusting the first adjustment amount based on the error rate difference value, and the nonlinear adjustment factor is used for adjusting the sensitivity of the first adjustment amount to the error rate difference value;
Constructing the history adjustment influence function;
Determining a second adjustment amount according to the history adjustment influence function and a preset history adjustment weight factor; the history adjustment weight factors are used for adjusting the influence degree of history adjustment data on the new preset curve values;
acquiring the current preset curve value;
and calling the self-adaptive correction algorithm to obtain a new preset curve value according to the current preset curve value, the first adjustment amount and the second adjustment amount.
On the other hand, the device for testing the equipment link loop further comprises: the acquisition module is used for acquiring the update times of the preset curve value after the step of writing the new preset curve value into a register of the quick peripheral component interconnection device and returning the test data to the quick peripheral component interconnection device;
The comparison module is also used for comparing the update times of the preset curve value and the preset value;
And the judging module is further used for judging that the signal channel of the rapid peripheral component interconnection device is unqualified if the update times of the preset curve value exceeds the preset value and the obtained current error rate is still higher than the preset signal margin value.
On the other hand, the obtaining module is further configured to obtain a data state of the returned data after the returned data sent by the peripheral component interconnect express device is received;
the device for testing the equipment link loop further comprises: the generation module is used for generating diagnosis information according to the acquired data state; wherein the diagnostic information includes: the number and frequency of data errors, the distribution of the channels of the errors, the integrity and correctness of the data packets, and the signal quality.
In order to solve the technical problem, the invention also provides a device link loop-back testing device, which comprises: a memory for storing a computer program;
And the processor is used for realizing the steps of the method for testing the equipment link loop when executing the computer program.
In order to solve the technical problem, the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes the steps of the method for testing the equipment link loop when being executed by a processor.
The testing method of the equipment link loop provided by the invention is applied to a loop testing jig connected with PCIe equipment; the loop test jig firstly sends test data to the PCIe device, the test data sent by the loop test jig is directly returned by the PCIe device, the loop test jig receives the return data sent by the PCIe device, and then the test data and the return data are compared to obtain the current error rate. If the obtained current error rate is not higher than the preset signal margin value, the error rate of the current channel is lower, and the signal channel of the PCIe equipment is judged to be qualified. If the obtained current error rate is higher than the signal margin value, the error rate of the current channel is higher, and the reason for the higher error rate is possibly that parameters of PCIe equipment are not matched, at the moment, a preset curve value is updated through an adaptive correction algorithm; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between a current error rate and a signal margin value and a history adjustment influence function. And finally, writing the new preset curve value into a register of the PCIe equipment, and returning to the step of sending test data to the PCIe equipment.
Compared with the original scheme, the method has the beneficial effects that the transmitted test data and the return data can be detected, parameters of PCIe equipment can be adjusted according to the detection result, and therefore the situation that the error rate is high when the PCIe equipment channel transmits data is improved, the accuracy of loop test of the PCIe equipment is improved, and misjudgment is avoided.
In addition, the invention also provides a specific scheme for updating the preset curve value, and the self-adaptive correction algorithm can obtain a better preset curve value, so that the error code condition of a PCIe device channel is improved. The specific scheme of the history adjustment influence function is provided, wherein the weight of the previous iteration is larger than that of the next iteration in the history adjustment influence function, so that the influence of the latest adjustment is larger than that of the earlier adjustment. After multiple updates, if the error rate is still higher, the PCIe device channel is characterized as being unqualified, and invalid parameter adjustment is avoided. The preset curve value specifically comprises a pre-emphasis parameter and an equalization parameter of the PCIe device, and the channel error condition can be improved by adjusting the pre-emphasis parameter and the equalization parameter. By generating more comprehensive diagnostic information, manufacturers and engineers can be helped to locate and resolve potential problems more quickly.
The invention also provides a device link loop testing device and a computer readable storage medium, which correspond to the method, and have the same beneficial effects as the method.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a flowchart of a method for testing a device link loop according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an actual test of a loop test fixture according to an embodiment of the present invention;
FIG. 3 is a block diagram of a device link loop test apparatus according to an embodiment of the present invention;
Fig. 4 is a block diagram of a device link loop testing apparatus according to another embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The core of the invention is to provide a method, a device and a medium for testing loop back of a device link, so as to solve the problem of misjudgment when loop back test is carried out on PCIe devices.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
PCIe devices are used to connect motherboards to various peripheral devices such as graphics cards, hard disks, solid state drives, and network adapters. PCIe is widely used in modern computer systems and data centers because of its high performance, scalability, and low latency characteristics. The invention provides a testing method for a link loop of PCIe equipment, which is applied to a loop testing jig connected with PCIe, and the loop testing jig analyzes channel distribution conditions of dislocation data by counting the conditions of data transmission of the PCIe equipment and adaptively matches hardware calibration parameters of a transmitting end and a receiving end. The fixture can accurately provide an optimized parameter set, provides an effective technical means for evaluating the PCIe signal compatibility margin, and can improve the loop test efficiency of PCIe equipment. Fig. 1 is a flowchart of a method for testing a device link loop according to an embodiment of the present invention; as shown in fig. 1, the method comprises the steps of:
s10: and sending the test data to the rapid peripheral component interconnect device.
S11: and receiving the return data sent by the quick peripheral component interconnection device.
S12: comparing the test data with the return data to obtain a current error rate, and judging whether the current error rate is higher than a preset signal margin value; if not, the process proceeds to step S13, and if yes, the process proceeds to step S14.
S13: and judging that the signal channel of the rapid peripheral component interconnection equipment is qualified.
S14: and updating the preset curve value through an adaptive correction algorithm.
The self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between a current error rate and a signal margin value and a history adjustment influence function.
S15: and writing the new preset curve value into a register of the quick peripheral component interconnection device, and returning to the step S10.
FIG. 2 is a schematic diagram of an actual test of a loop test fixture according to an embodiment of the present invention; as shown in fig. 2, a loop test fixture 1 is connected with a PCIe device 2, and in the embodiment of the present invention, an adaptive detection module is introduced into the loop test fixture 1 of the PCIe device 2, where the fixture includes a PCIe connector, and a hardware-level connection is formed between a receiving channel and a transmitting channel on the PCIe connector, and the adaptive detection module, so as to implement direct signal loop inside the PCIe device 2 and automatically perform adaptive intelligent detection, and evaluate signal quality of each channel. And detecting the whole data path inside the chip through the designed self-adaptive detection module. The adaptive detection module is located before the receiving end (RX interface) of the PCIe device 2, and comprises a loop circuit and an adaptive detection module. The adaptive correction algorithm of the adaptive detection module performs adaptive adjustment for the link state of the PCIe device 2, so that the signal quality of different chips of an individual approaches to a set threshold value. When the loop test starts, a predefined data format is configured through the interface of the adaptive detection module, the data arrives at the RX end of the PCIe device 2 from the adaptive detection module, and the transmitting end (TX interface) of the PCIe device 2 returns the data. The self-adaptive detection module compares the received data with the original data to obtain the error rate, and establishes a self-adaptive model. After the self-adaptive detection module detects that the error count reaches a preset threshold, the self-adaptive detection module can evaluate the link quality of the related channel and record the result in a register.
During the period, if the self-adaptive detection module judges that the link cannot meet the signal margin value, the current link parameter is input into the self-adaptive correction algorithm, the calibrated optimal parameter set is iterated and written into a register of the PCIe equipment, the calibrated value is used for retesting according to the flow, and if the error rate still cannot meet the signal requirement after the preset times, the channel is considered to be disqualified. The adaptive correction algorithm includes:
Presetnew＝Presetcurrent-α×tah(β×ΔBER)+γ×H(Presethistory) (1)
Wherein, preset new is a new Preset curve value, preset current is a current Preset curve value, Δber is an error rate difference value, α is a positive scale factor, β is a positive nonlinear adjustment factor, γ is a positive history adjustment weight factor, and H (Preset history) is a history adjustment influence function. The error rate difference, the scaling factor and the nonlinear adjustment factor form a first adjustment quantity; the scale factor is used for adjusting the first adjustment amount based on the error rate difference value, and the nonlinear adjustment factor is used for adjusting the sensitivity of the first adjustment amount to the error rate difference value. the tanh (·) is a hyperbolic tangent function that ensures that the first adjustment is not excessive when the error rate difference is large, so as to avoid excessive adjustment. The history adjustment influence function and the history adjustment weight factor form a second adjustment quantity; the history adjustment weight factors are used for adjusting the influence degree of the history adjustment data on a new preset curve value. The history adjustment influencing function is used for influencing the current adjustment according to the past preset curve value adjustment condition. The history adjustment influence function includes:
Wherein Preseti is a preset curve value of the ith iteration, wi is a weight of the ith iteration, and k is the number of historical adjustment times. The weight of the previous iteration is larger than that of the next iteration in the history adjustment influence function, namely w1> w2> … … > wn is satisfied, so that the influence of the latest adjustment is larger than that of the earlier adjustment.
Such self-diagnostic functionality not only provides more accurate test results, but also provides more diagnostic information in a shorter time, thereby helping manufacturers and engineers locate and resolve potential problems more quickly.
The testing method of the equipment link loop provided by the embodiment of the invention is applied to the loop testing jig connected with the PCIe equipment; the loop test jig firstly sends test data to the PCIe device, the test data sent by the loop test jig is directly returned by the PCIe device, the loop test jig receives the return data sent by the PCIe device, and then the test data and the return data are compared to obtain the current error rate. If the obtained current error rate is not higher than the preset signal margin value, the error rate of the current channel is lower, and the signal channel of the PCIe equipment is judged to be qualified. If the obtained current error rate is higher than the signal margin value, the error rate of the current channel is higher, and the reason for the higher error rate is possibly that parameters of PCIe equipment are not matched, at the moment, a preset curve value is updated through an adaptive correction algorithm; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between a current error rate and a signal margin value and a history adjustment influence function. And finally, writing the new preset curve value into a register of the PCIe equipment, and returning to the step of sending test data to the PCIe equipment. The scheme not only can detect the transmitted test data and the return data, but also can adjust parameters of the PCIe equipment according to the detection result, thereby improving the condition of high error rate when the PCIe equipment channel transmits data, further improving the accuracy of loop test of the PCIe equipment and avoiding misjudgment.
In practical application, in order to update the preset curve value, the error rate difference between the current error rate and the signal margin value can be determined first, and then the first adjustment amount is determined according to the error rate difference, the preset scale factor and the nonlinear adjustment factor. And simultaneously constructing a history adjustment influence function, and determining a second adjustment amount according to the history adjustment influence function and a preset history adjustment weight factor. And obtaining a current preset curve value, and finally, calling a self-adaptive correction algorithm to obtain a new preset curve value according to the current preset curve value, the first adjustment amount and the second adjustment amount. The specific content of the adaptive correction algorithm can be referred to formula (1), and the specific content of the history adjustment influence function can be referred to formula (2). The self-adaptive correction algorithm can obtain a better preset curve value, so that the situation of error codes of a PCIe device channel is improved.
In addition, if the error rate still cannot meet the requirement after updating the preset curve value for a plurality of times, the characterization channel has a problem. Therefore, the embodiment of the invention provides a scheme that after writing a new preset curve value into a register of PCIe equipment and returning test data to the PCIe equipment, the update times of the preset curve value are obtained, and the update times of the preset curve value and the preset value are compared; if the update times of the preset curve value exceeds the preset value and the obtained current error rate is still higher than the preset signal margin value, judging that the signal channel of the PCIe equipment is unqualified. By the scheme provided by the embodiment, invalid parameter adjustment can be avoided.
In the above embodiments, it is mentioned that the Preset curve value Preset is a predefined set of settings or parameters for adjusting and optimizing the performance of the high-speed serial communication interface. The set of parameters may include equalizer settings, gain of the driver and receiver, voltage offset, etc. to optimize signal quality and improve reliability of the data transmission. When a new device is added to the system or when channel conditions change, the Preset curve value Preset can be used to quickly set and adjust the interface parameters without lengthy manual adjustments. The preset curve value of the embodiment includes a pre-emphasis parameter and an equalization parameter of the PCIe device, if the obtained current bit error rate is higher than the signal margin value, updating the preset curve value through the adaptive correction algorithm includes: if the obtained current error rate is higher than the signal margin value, updating the pre-emphasis parameter and the equalization parameter of the PCIe device through the self-adaptive correction algorithm.
The self-diagnosis function provided by the invention not only can provide more accurate test results, but also can provide more diagnosis information in a shorter time, for example, after receiving return data sent by PCIe equipment, the data state of the return data can be obtained; generating diagnostic information according to the acquired data state; wherein the diagnostic information includes: the number and frequency of data errors, the distribution of the channels of errors, the integrity and correctness of the data packets, the signal quality, etc., by means of which the diagnostic information generated in this embodiment can help manufacturers and engineers locate and solve potential problems more quickly.
The invention provides a high-efficiency and reliable PCIe loop test fixture. The fixture can provide a convenient and low-cost test solution for manufacturers and maintenance providers of PCIe devices, and is helpful for ensuring the performance and reliability of the PCIe devices.
The following are some of the potential application scenarios and advantages of the present invention, production line testing: in the production process, a manufacturer can use the PCIe loop test fixture to perform quick and accurate performance test on mass-produced equipment. This will help to improve production efficiency, reduce reject ratio, thereby reducing production costs and improving product quality. Equipment maintenance and debugging: when a maintainer or a system integrator maintains or debugs PCIe equipment, the hardware-level loop test can be performed by using the loop test jig, so that the equipment problem can be rapidly positioned, and the maintenance efficiency is improved. Compatibility test: for newly developed PCIe devices or drivers, the developer can use the loop-back test jig of the invention to perform compatibility test so as to ensure the stability and performance of the device under different system environments. The test cost is reduced: compared with the traditional hardware loop test equipment, the loop test fixture has lower design and manufacturing cost. Meanwhile, due to the simple use method, the testers do not need to receive complex training, so that the test cost is further reduced.
In summary, the invention provides a novel PCIe loop test fixture, which has the advantages of simplicity, high efficiency, strong universality and the like. By adopting the technical scheme of the invention, the problems in the prior art can be effectively solved, the loop test efficiency of the PCIe equipment is improved, and convenience is provided for manufacturers, maintenance providers and developers of the PCIe equipment.
The current PCIe device loop test technology can meet the requirements of device test to a certain extent, but has some disadvantages. For example, hardware test jigs may be costly to design and manufacture, and require a complete motherboard and PCIe slot for related testing. Therefore, a novel PCIe loop test fixture is developed to solve the problems and improve the test efficiency, and has important practical value. In the scheme provided by the embodiment of the invention, the loop test jig adopts the special golden finger connector which is matched with the golden finger interface on the PCIe equipment, and the hardware-level connection is formed between the sending channel and the interface channel on the golden finger connector so as to realize the direct loop of the signal in the PCIe equipment. In the design process, the correct corresponding relation between the receiving channel and the sending channel on the golden finger connector is ensured, so that the data can be correctly transmitted in the loop test process. In order to ensure the integrity and stability of signals in the loop test process, the loop test fixture also considers the impedance matching problem in the design process, and proper impedance matching can be realized by optimizing wiring and selecting proper materials, so that the attenuation and reflection of signals are reduced. This helps ensure signal integrity and stability during loop-back testing. Meanwhile, corresponding loss can be configured to simulate long and short links in a real environment. The embodiment of the invention can adapt to PCIe slots of various types and PCIe interfaces with different rates and specifications, such as PCIe 3.0, PCIe 4.0 and the like by designing the testing jig with universality and expandability. The test fixture directly realizes the loop data path of the PCIe end at the hardware level, simplifies the loop test process, and can perform loop test without additional software or hardware support.
In the above embodiment, the detailed description is given to the testing method of the device link loop, and the invention also provides a corresponding embodiment of the testing device of the device link loop. It should be noted that the present invention describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Based on the angle of the functional module, the embodiment provides a testing device for loop back of an equipment link, which is applied to a loop back testing jig connected with PCIe equipment; fig. 3 is a structural diagram of a device link loop testing apparatus provided in an embodiment of the present invention, as shown in fig. 3, where the device includes:
a sending module 10, configured to send test data to a PCIe device;
a receiving module 11, configured to receive return data sent by a PCIe device;
a comparison module 12, configured to compare the test data with the return data to obtain a current bit error rate;
The judging module 13 is configured to judge that the signal channel of the PCIe device is qualified if the obtained current error rate is not higher than a preset signal margin value;
The updating module 14 is configured to update the preset curve value through an adaptive correction algorithm if the obtained current error rate is higher than the signal margin value; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between a current error rate and a signal margin value and a history adjustment influence function;
The writing module 15 is configured to write a new preset curve value into a register of the PCIe device, and trigger the sending module.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
In some embodiments, the updating module is specifically configured to determine an error rate difference between the current error rate and the signal margin value;
determining a first adjustment amount according to the error rate difference value and a preset scale factor and a nonlinear adjustment factor; the scale factor is used for adjusting the first adjustment amount based on the error rate difference value, and the nonlinear adjustment factor is used for adjusting the sensitivity of the first adjustment amount to the error rate difference value;
Constructing a history adjustment influence function;
Determining a second adjustment amount according to a history adjustment influence function and a preset history adjustment weight factor; the history adjustment weight factors are used for adjusting the influence degree of the history adjustment data on a new preset curve value;
Acquiring a current preset curve value;
And calling an adaptive correction algorithm to obtain a new preset curve value according to the current preset curve value, the first adjustment amount and the second adjustment amount.
In some embodiments, the device link loop-back testing apparatus further includes: the acquisition module is used for acquiring the update times of the preset curve value after writing the new preset curve value into a register of the PCIe device and returning the step of sending the test data to the PCIe device;
the comparison module is also used for comparing the update times of the preset curve value and the preset value;
and the judging module is also used for judging that the signal channel of the PCIe equipment is unqualified if the update times of the preset curve value exceeds the preset value and the obtained current error rate is still higher than the preset signal margin value.
In some embodiments, the obtaining module is further configured to obtain a data state of the return data after receiving the return data sent by the PCIe device;
the device link loop-back testing device further comprises: the generation module is used for generating diagnosis information according to the acquired data state; wherein the diagnostic information includes: the number and frequency of data errors, the distribution of the channels of the errors, the integrity and correctness of the data packets, and the signal quality.
The device for testing the equipment link loop provided by the embodiment corresponds to the method, so that the device has the same beneficial effects as the method.
Based on the hardware angle, this embodiment provides another device link loop testing apparatus, and fig. 4 is a structural diagram of the device link loop testing apparatus provided in another embodiment of the present invention, as shown in fig. 4, where the device link loop testing apparatus includes: a memory 20 for storing a computer program;
a processor 21 for implementing the steps of the method for testing a device link loop as mentioned in the above embodiments when executing a computer program.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The Processor 21 may be implemented in at least one hardware form of a digital signal Processor (DIGITAL SIGNAL Processor, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 21 may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with an image processor (Graphics Processing Unit, GPU) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, where the computer program, after being loaded and executed by the processor 21, can implement the relevant steps of the device link loop-back testing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. Operating system 202 may include Windows, unix, linux, among other things. The data 203 may include, but is not limited to, data related to a testing method of the device link loop, and the like.
In some embodiments, the testing apparatus of the device link loop may further include a communication bus 22, an input/output interface 23, a communication interface 24, and a power supply 25.
Those skilled in the art will appreciate that the structures shown in the figures do not constitute limitations on the testing apparatus of the device link loop, and may include more or fewer components than shown.
The device for testing the equipment link loop comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory: a testing method for equipment link loop.
The device for testing the equipment link loop provided by the embodiment corresponds to the method, so that the device has the same beneficial effects as the method.
Finally, the invention also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution contributing to the prior art, or may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The computer readable storage medium provided in the present embodiment corresponds to the above method, and thus has the same advantageous effects as the above method.
The method, the device and the medium for testing the equipment link loop provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. The testing method of the equipment link loop is characterized by being applied to a loop testing jig connected with the quick peripheral component interconnection equipment; the method comprises the following steps:
Sending test data to the rapid peripheral component interconnect device;
Receiving return data sent by the rapid peripheral component interconnect device;
comparing the test data with the return data to obtain a current error rate;
if the obtained current error rate is not higher than a preset signal margin value, judging that a signal channel of the rapid peripheral component interconnection equipment is qualified;
If the obtained current error rate is higher than the signal margin value, updating a preset curve value through an adaptive correction algorithm; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between the current error rate and the signal margin value and a history adjustment influence function;
Writing the new preset curve value into a register of the rapid peripheral component interconnection equipment, and returning the test data to the rapid peripheral component interconnection equipment.
2. The method for testing the loop back of the equipment link according to claim 1, wherein if the obtained current error rate is higher than the signal margin value, updating the preset curve value by the adaptive correction algorithm comprises:
Determining the error rate difference between the current error rate and the signal margin value;
Determining a first adjustment amount according to the error rate difference value and a preset scale factor and a nonlinear adjustment factor; wherein the scaling factor is used for adjusting the first adjustment amount based on the error rate difference value, and the nonlinear adjustment factor is used for adjusting the sensitivity of the first adjustment amount to the error rate difference value;
Constructing the history adjustment influence function;
Determining a second adjustment amount according to the history adjustment influence function and a preset history adjustment weight factor; the history adjustment weight factors are used for adjusting the influence degree of history adjustment data on the new preset curve values;
acquiring the current preset curve value;
Calling the self-adaptive correction algorithm to obtain a new preset curve value according to the current preset curve value, the first adjustment amount and the second adjustment amount;
Wherein the adaptive correction algorithm comprises:
Presetnew＝Presetcurrent-α×tanh(β×ΔBER)+γ×H(Presethistory)；
Preset new is the new Preset curve value, preset current is the current Preset curve value, ΔBER is the error rate difference, α is the scaling factor, β is the nonlinear adjustment factor, γ is the history adjustment weight factor, and H (Preset history) is the history adjustment influence function.
3. The method for testing a device link loop according to claim 2, wherein the history adjustment influence function comprises:
Wherein Preseti is a preset curve value of the ith iteration, wi is a weight of the ith iteration, and k is the number of historical adjustment times.
4. A method of testing a device link loop according to claim 3 and wherein the weight of a previous iteration is greater than the weight of a subsequent iteration in the history adjustment influencing function.
5. The method for testing a device link loop according to any one of claims 1to 4, further comprising, after the step of writing the new preset curve value into a register of the peripheral component interconnect express device and returning the sending test data to the peripheral component interconnect express device:
Acquiring the update times of the preset curve value;
comparing the update times of the preset curve value and the preset value;
and if the update times of the preset curve value exceeds the preset value and the obtained current error rate is still higher than the preset signal margin value, judging that the signal channel of the quick peripheral component interconnection equipment is unqualified.
6. The method for testing the loop back of the equipment link according to claim 1, wherein if the obtained current error rate is higher than the signal margin value, updating the preset curve value by the adaptive correction algorithm comprises:
and if the obtained current error rate is higher than the signal margin value, updating the pre-emphasis parameter and the equalization parameter of the quick peripheral component interconnection equipment through the self-adaptive correction algorithm.
7. The method for testing a device link loop according to claim 1, further comprising, after said receiving the return data sent by the peripheral component interconnect express device:
acquiring the data state of the returned data;
Generating diagnostic information according to the acquired data state; wherein the diagnostic information includes: the number and frequency of data errors, the distribution of the channels of the errors, the integrity and correctness of the data packets, and the signal quality.
8. The device for testing the loop of the equipment link is characterized by being applied to a loop testing jig connected with the quick peripheral component interconnection equipment; the device comprises:
The sending module is used for sending the test data to the quick peripheral component interconnection equipment;
The receiving module is used for receiving the return data sent by the rapid peripheral component interconnection equipment;
The comparison module is used for comparing the test data with the return data to obtain the current error rate;
The judging module is used for judging that the signal channel of the rapid peripheral component interconnection equipment is qualified if the obtained current error rate is not higher than a preset signal margin value;
The updating module is used for updating a preset curve value through an adaptive correction algorithm if the obtained current error rate is higher than the signal margin value; the self-adaptive correction algorithm obtains a new preset curve value through a current preset curve value, an error rate difference value between the current error rate and the signal margin value and a history adjustment influence function;
And the writing module is used for writing the new preset curve value into a register of the quick peripheral component interconnection equipment and triggering the sending module.
9. A device link loop-back testing apparatus, comprising a memory for storing a computer program;
a processor for implementing the steps of the method for testing a device link loop back according to any one of claims 1 to 7 when executing said computer program.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the method for testing a device link loop according to any of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119011406A (en) * | 2024-10-23 | 2024-11-22 | 苏州元脑智能科技有限公司 | Bandwidth adjustment method, device, program product, medium and server |
| CN119917360A (en) * | 2025-04-03 | 2025-05-02 | 四川华鲲振宇智能科技有限责任公司 | A equipment detection system and method based on standard PCIE connector |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN119011406A (en) * | 2024-10-23 | 2024-11-22 | 苏州元脑智能科技有限公司 | Bandwidth adjustment method, device, program product, medium and server |
| CN119011406B (en) * | 2024-10-23 | 2025-02-25 | 苏州元脑智能科技有限公司 | A bandwidth adjustment method, device, program product, medium and server |
| CN119917360A (en) * | 2025-04-03 | 2025-05-02 | 四川华鲲振宇智能科技有限责任公司 | A equipment detection system and method based on standard PCIE connector |
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