CN118138037B - Voltage level conversion circuit - Google Patents
Voltage level conversion circuit Download PDFInfo
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- CN118138037B CN118138037B CN202410550999.0A CN202410550999A CN118138037B CN 118138037 B CN118138037 B CN 118138037B CN 202410550999 A CN202410550999 A CN 202410550999A CN 118138037 B CN118138037 B CN 118138037B
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 78
- 238000003708 edge detection Methods 0.000 claims abstract description 43
- 230000005540 biological transmission Effects 0.000 claims abstract description 28
- 238000001514 detection method Methods 0.000 claims abstract description 19
- 101150110971 CIN7 gene Proteins 0.000 claims description 24
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
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Abstract
The invention provides a voltage level conversion circuit which comprises an automatic signal edge detection module and a voltage level conversion circuit module. The voltage level conversion circuit module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic signal edge detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end. The invention can automatically identify and configure the transmission direction of the bidirectional voltage level conversion circuit, and the circuit is simple and easy to realize.
Description
Technical Field
The invention relates to the technical field of bus communication, in particular to a voltage level conversion circuit.
Background
The development of very large scale integrated circuit technology has enabled complex systems on chip, where modules of different functions, such as analog circuits, digital circuits, passive components, etc., are integrated into a single chip. Different functional modules have different performances and constraints, and can be operated with different voltages to realize the optimal performance-power consumption ratio. In current system-on-chip designs, it is common to have two or more voltage domains in a single chip. In order to solve the problem of uncoordinated input-output logic to achieve normal communication between different voltage domains inside a chip, a voltage level conversion circuit is required to convert a logic signal from one voltage level to another voltage level.
As shown in fig. 1, the conventional bidirectional voltage level conversion circuit generates 2 paths of control signals AQ and BQ for controlling the transmission direction of bidirectional voltage level conversion by using two inverters INV3a and INV3 b. The existing bidirectional voltage level conversion circuit realizes bidirectional voltage level conversion, but needs to set additional direction signals to control the transmission direction, and has complex circuit structure and difficult realization.
Disclosure of Invention
The present invention has been made in view of the above problems, and has an object to provide a voltage level converting circuit capable of automatically recognizing and configuring a transmission direction of a bidirectional voltage level converting circuit, which is simple and easy to implement.
The invention discloses a voltage level conversion circuit, which particularly comprises an automatic signal edge detection module and a voltage level conversion circuit module;
the voltage level conversion circuit module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic signal edge detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end.
Further, the automatic signal edge detection module automatically detects the voltage level change of the first signal end or the second signal end, judges the transmission direction of the voltage level conversion circuit module, and controls the transmission direction of the voltage level conversion circuit module.
Further, the automatic signal edge detection module detects a voltage level rising edge of the first signal end or the second signal end.
Further, the automatic signal edge detection module includes a first transistor NM1a, a second transistor NM1b, a third transistor NM2a, a fourth transistor NM2b, a fifth transistor NM3, a first resistor R1a, a second resistor R1b, a third resistor R2a, and a fourth resistor R2b;
The first resistor R1a and the first end of the third resistor R2a are connected to the first power supply voltage VDD, the second end of the first resistor R1a is connected to the first end of the second resistor R1b and the gate of the fourth transistor NM2b, and is used as the first judgment signal output end of the automatic signal edge detection module, the first judgment signal AQ is generated, the second end of the second resistor R1b is connected to the drain of the first transistor NM1a, the gate of the first transistor NM1a is used as the first detection end of the automatic signal edge detection module, the source of the first transistor NM1a is connected to the drain of the second transistor NM1b, the gate of the second transistor NM1b is connected to the second end of the third resistor R2a and the first end of the fourth resistor R2b, and is used as the second judgment signal output end of the automatic signal edge detection module, the source of the second transistor NM1b is connected to the source of the fifth transistor NM2b, the source of the fifth transistor NM3 is connected to the drain of the automatic signal edge detection module, and the source of the third transistor NM2b is connected to the source of the automatic signal edge detection module.
Further, when the first judgment signal AQ is at a low level and the second judgment signal BQ is at a high level, the voltage level conversion circuit module is controlled to be in a first transmission direction, and signals are transmitted from the first signal end to the second signal end; when the first judgment signal AQ is at a high level and the second judgment signal BQ is at a low level, the voltage level conversion circuit module is controlled to be at a second transmission direction, and signals are transmitted from the second signal end to the first signal end.
Further, the first transistor NM1a, the second transistor NM1b, the third transistor NM2a, the fourth transistor NM2b, and the fifth transistor NM3 are NMOS transistors.
Further, the voltage level conversion circuit module specifically includes a first inverter INV0, a first gate inverter INV1, a second inverter INV3, and a second gate inverter INV2;
The input end of the first inverter INV0 is used as a second signal end of the voltage level conversion circuit module, the output end of the first inverter INV0 is connected with the input end of the first gating inverter INV1, the output end of the first gating inverter INV1 is connected with the first signal end, and the control end of the first gating inverter INV1 is used as a second control end of the voltage level conversion circuit module and receives a second judging signal BQ; the input end of the second inverter INV3 is used as the first signal end of the voltage level conversion circuit module, the output end of the second inverter INV3 is connected with the input end of the second gating inverter INV2, the output end of the second gating inverter INV2 is connected with the second signal end, the control end of the first gating inverter INV1 is used as the first control end of the voltage level conversion circuit module, the first judgment signal AQ is received, and the first control end and the second control end of the voltage level conversion circuit module jointly form the control end of the voltage level conversion circuit module.
Further, when the first judgment signal AQ is at a low level and the second judgment signal BQ is at a high level, the first gating inverter INV1 is controlled to be not operated, the second gating inverter INV2 is controlled to be operated, and the voltage level conversion circuit module is controlled to be in a first transmission direction, so that signals are transmitted from the first signal end to the second signal end; when the first judgment signal AQ is at a high level and the second judgment signal BQ is at a low level, the first gating inverter INV1 is controlled to operate, the second gating inverter INV2 is controlled to be not operated, the voltage level conversion circuit module is controlled to be at a second transmission direction, and signals are transmitted from the second signal end to the first signal end.
Further, the first gate inverter INV1 and the second gate inverter INV2 include a third inverter INV4a, a fourth inverter INV4b, a sixth transistor PM4b, a seventh transistor PM4c, an eighth transistor NM4b, and a ninth transistor NM4c, respectively;
The input end of the third inverter INV4a is used as the control end of the gating inverter, the output end of the third inverter INV4a is connected with the input end of the fourth inverter INV4b and the gate of the eighth transistor NM4b, the output end of the fourth inverter INV4b is connected with the gate of the sixth transistor PM4b, the gate of the seventh transistor PM4c is connected with the gate of the ninth transistor NM4c and is used as the input end of the gating inverter, the source of the seventh transistor PM4c is connected with the second power supply voltage, the drain of the seventh transistor PM4c is connected with the source of the sixth transistor PM4b, the drain of the sixth transistor PM4b is connected with the drain of the eighth transistor NM4b and is used as the output end of the gating inverter, the source of the eighth transistor NM4b is connected with the drain of the ninth transistor NM4c, and the source of the ninth transistor NM4c is grounded.
Further, the sixth transistor PM4b and the seventh transistor PM4c are PMOS transistors, and the eighth transistor NM4b and the ninth transistor NM4c are NMOS transistors.
The beneficial effects of the invention are as follows:
(1) The invention provides a voltage level conversion circuit, which can automatically identify and configure the transmission direction of a bidirectional voltage level conversion circuit by utilizing an automatic signal edge detection module, and has simple circuit and easy realization.
(2) The invention provides an automatic signal edge detection module, which has simple circuit, can automatically identify and configure the transmission direction of a bidirectional voltage level conversion circuit by adopting only five transistors, and is easy to realize.
(3) The application provides a gating inverter which only adopts four transistors and two inverters, and has simple circuit and easy realization.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of a conventional bidirectional voltage level conversion circuit;
FIG. 2 is a block diagram of a voltage level conversion circuit according to the present invention;
FIG. 3 is a circuit diagram of a voltage level conversion circuit according to the present invention;
FIG. 4 is a diagram illustrating an exemplary operational waveform of an automatic signal edge detection module according to the present invention;
FIG. 5 is a circuit diagram of a gated inverter according to the present invention;
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
The invention will be further described with reference to the drawings and the specific examples.
First embodiment
As shown in fig. 2, the present application provides a voltage level conversion circuit. The voltage level conversion circuit specifically comprises an automatic signal edge detection module and a voltage level conversion circuit module.
The voltage level conversion circuit module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic signal edge detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end. The automatic signal edge detection module automatically detects the voltage level change of the first signal A or the second signal B, generates a judgment signal after judging the transmission direction of the voltage level conversion circuit module, inputs the judgment signal to the control end of the voltage level conversion circuit module, and controls the transmission direction of the voltage level conversion circuit module.
Specifically, when the first signal A is input, the voltage level of the first signal end changes first, and after the automatic signal edge detection module detects the voltage level change of the first signal end, the voltage level conversion circuit module is controlled to be in a first transmission direction, so that signals are transmitted from the first signal end to the second signal end; when the second signal B is input, the voltage level of the second signal end changes first, and after the automatic signal edge detection module detects the voltage level change of the second signal end, the voltage level conversion circuit module is controlled to be in a second transmission direction, so that signals are transmitted from the second signal end to the first signal end.
In the application, the voltage level conversion circuit utilizes the automatic signal edge detection module, can automatically identify and configure the transmission direction of the bidirectional voltage level conversion circuit, and has simple circuit and easy realization.
As a preferred embodiment, the automatic signal edge detection module detects a voltage level rising edge of the first signal terminal or the second signal terminal.
Second embodiment
As shown in fig. 3, the present application further provides a circuit structure diagram of the voltage level conversion circuit. The automatic signal edge detection module comprises a first transistor NM1a, a second transistor NM1b, a third transistor NM2a, a fourth transistor NM2b, a fifth transistor NM3, a first resistor R1a, a second resistor R1b, a third resistor R2a and a fourth resistor R2b.
The first resistor R1a and the first end of the third resistor R2a are connected to the first power supply voltage VDD, the second end of the first resistor R1a is connected to the first end of the second resistor R1b and the gate of the fourth transistor NM2b, and is used as the first judgment signal output end of the automatic signal edge detection module, the first judgment signal AQ is generated, the second end of the second resistor R1b is connected to the drain of the first transistor NM1a, the gate of the first transistor NM1a is used as the first detection end of the automatic signal edge detection module, the source of the first transistor NM1a is connected to the drain of the second transistor NM1b, the gate of the second transistor NM1b is connected to the second end of the third resistor R2a and the first end of the fourth resistor R2b, and is used as the second judgment signal output end of the automatic signal edge detection module, the source of the second transistor NM1b is connected to the source of the fifth transistor NM2b, the source of the fifth transistor NM3 is connected to the drain of the automatic signal edge detection module, and the source of the third transistor NM2b is connected to the source of the automatic signal edge detection module.
Specifically, the automatic signal edge detection module works, the enable control signal EN controls the fifth transistor NM3 to be turned on, when the first signal a is input, the first signal a changes from low level to high level, the automatic signal edge detection module detects that the voltage level of the first signal end changes first, the first transistor NM1a is turned on, the second signal B is at low level at this time, the third transistor NM2a is turned off, the second judgment signal BQ is at high level, meanwhile, the second transistor NM1B is controlled to be turned on, the first judgment signal AQ is at low level, the fourth transistor NM2B is controlled to be turned off, and then the second judgment signal BQ is locked and kept at high level, and the working waveform chart is shown in fig. 4.
When the second signal B is input, the second signal B changes from low level to high level, the automatic signal edge detection module detects that the voltage level of the second signal end changes first, the third transistor NM2a is turned on, the first signal a is at low level, the first transistor NM1a is turned off, the first judgment signal AQ is at high level, meanwhile, the fourth transistor NM2B is controlled to be turned on, the second judgment signal BQ is at low level, the second transistor NM1B is controlled to be turned off, and the first judgment signal AQ is locked and kept at high level.
When the first judgment signal AQ is in a low level and the second judgment signal BQ is in a high level, controlling the voltage level conversion circuit module to be in a first transmission direction, and transmitting signals from the first signal end to the second signal end; when the first judgment signal AQ is at a high level and the second judgment signal BQ is at a low level, the voltage level conversion circuit module is controlled to be at a second transmission direction, and signals are transmitted from the second signal end to the first signal end.
As a preferred embodiment, the first transistor NM1a, the second transistor NM1b, the third transistor NM2a, the fourth transistor NM2b, and the fifth transistor NM3 are NMOS transistors.
Further, as shown in fig. 3, the voltage level conversion circuit further includes a voltage level conversion circuit module. The voltage level conversion circuit module specifically comprises a first inverter INV0, a first gating inverter INV1, a second inverter INV3 and a second gating inverter INV2.
The input end of the first inverter INV0 is used as a second signal end of the voltage level conversion circuit module, the output end of the first inverter INV0 is connected with the input end of the first gating inverter INV1, the output end of the first gating inverter INV1 is connected with the first signal end, and the control end of the first gating inverter INV1 is used as a second control end of the voltage level conversion circuit module and receives a second judging signal BQ; the input end of the second inverter INV3 is used as the first signal end of the voltage level conversion circuit module, the output end of the second inverter INV3 is connected with the input end of the second gating inverter INV2, the output end of the second gating inverter INV2 is connected with the second signal end, the control end of the first gating inverter INV1 is used as the first control end of the voltage level conversion circuit module, the first judgment signal AQ is received, and the first control end and the second control end of the voltage level conversion circuit module jointly form the control end of the voltage level conversion circuit module.
Specifically, when the first judgment signal AQ is at a low level and the second judgment signal BQ is at a high level, the first gating inverter INV1 is controlled to be not operated, the second gating inverter INV2 is controlled to be operated, the voltage level conversion circuit module is controlled to be in a first transmission direction, and signals are transmitted from the first signal end to the second signal end; when the first judgment signal AQ is at a high level and the second judgment signal BQ is at a low level, the first gating inverter INV1 is controlled to operate, the second gating inverter INV2 is controlled to be not operated, the voltage level conversion circuit module is controlled to be at a second transmission direction, and signals are transmitted from the second signal end to the first signal end.
In the application, the automatic signal edge detection module circuit is simple, only five transistors are adopted, the transmission direction of the bidirectional voltage level conversion circuit can be automatically identified and configured, and the implementation is easy.
Third embodiment
As shown in fig. 5, the present application further provides a circuit structure diagram of a gate inverter, which is used to implement a first gate inverter INV1 and a second gate inverter INV2, where the gate inverter is enabled to operate or not operate by a judgment signal input to a control terminal.
The gate inverter includes a third inverter INV4a, a fourth inverter INV4b, a sixth transistor PM4b, a seventh transistor PM4c, an eighth transistor NM4b, and a ninth transistor NM4c.
The input end of the third inverter INV4a is used as the control end of the gating inverter, the output end of the third inverter INV4a is connected with the input end of the fourth inverter INV4b and the gate of the eighth transistor NM4b, the output end of the fourth inverter INV4b is connected with the gate of the sixth transistor PM4b, the gate of the seventh transistor PM4c is connected with the gate of the ninth transistor NM4c and is used as the input end of the gating inverter, the source of the seventh transistor PM4c is connected with the second power supply voltage, the drain of the seventh transistor PM4c is connected with the source of the sixth transistor PM4b, the drain of the sixth transistor PM4b is connected with the drain of the eighth transistor NM4b and is used as the output end of the gating inverter, the source of the eighth transistor NM4b is connected with the drain of the ninth transistor NM4c, and the source of the ninth transistor NM4c is grounded.
In a preferred embodiment, the sixth and seventh transistors PM4b and PM4c are PMOS transistors, and the eighth and ninth transistors NM4b and NM4c are NMOS transistors.
In the application, the gate-controlled inverter only adopts four transistors and two inverters, so that the circuit is simple and easy to realize.
While the foregoing description illustrates and describes the preferred embodiments of the present invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as limited to other embodiments, and is capable of numerous other combinations, modifications and environments and is capable of changes or modifications within the scope of the inventive concept as described herein, either as a result of the foregoing teachings or as a result of the knowledge or technology in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (9)
1. The voltage level conversion circuit is characterized by comprising an automatic signal edge detection module and a voltage level conversion circuit module;
The voltage level conversion circuit module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic signal edge detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end;
The automatic signal edge detection module comprises a first transistor NM1a, a second transistor NM1b, a third transistor NM2a, a fourth transistor NM2b, a fifth transistor NM3, a first resistor R1a, a second resistor R1b, a third resistor R2a and a fourth resistor R2b;
The first resistor R1a and the first end of the third resistor R2a are connected to the first power supply voltage VDD, the second end of the first resistor R1a is connected to the first end of the second resistor R1b and the gate of the fourth transistor NM2b, and is used as a first judgment signal output end of the automatic signal edge detection module, a first judgment signal AQ is generated, the second end of the second resistor R1b is connected to the drain of the first transistor NM1a, the gate of the first transistor NM1a is used as a first detection end of the automatic signal edge detection module, the source of the first transistor NM1a is connected to the drain of the second transistor NM1b, the gate of the second transistor NM1b is connected to the second end of the third resistor R2a and the first end of the fourth resistor R2b, and is used as a second judgment signal output end of the automatic signal edge detection module, a second judgment signal BQ is generated, the source of the second transistor NM1b is connected to the source of the fourth transistor NM2b and the drain of the fifth transistor NM3, the gate of the fifth transistor NM3 is connected to the drain of the automatic signal edge detection module, and the source of the third transistor NM2b is connected to the drain of the third transistor NM2 a;
The automatic signal edge detection module works, the enable control signal EN controls the fifth transistor NM3 to be conducted, when the first signal A is input, the first signal A is changed from low level to high level, the automatic signal edge detection module detects that the voltage level of the first signal end is changed first, the first transistor NM1a is conducted, the second signal B is low level at the moment, the third transistor NM2a is turned off, the second judgment signal BQ is connected with the first power supply voltage VDD through the third resistor R2a, the second judgment signal BQ is high level, meanwhile, the second transistor NM1B is controlled to be conducted, the first judgment signal AQ is low level, the fourth transistor NM2B is controlled to be turned off, and the second judgment signal BQ is locked and kept to be high level;
When the second signal B is input, the second signal B changes from low level to high level, the automatic signal edge detection module detects that the voltage level of the second signal terminal changes first, the third transistor NM2a is turned on, the first signal a is at low level, the first transistor NM1a is turned off, the first judgment signal AQ is connected to the first power supply voltage VDD through the first resistor R1a, the first judgment signal AQ is at high level, and meanwhile, the fourth transistor NM2B is controlled to be turned on, the second judgment signal BQ is at low level, the second transistor NM1B is controlled to be turned off, and the first judgment signal AQ is locked and kept at high level.
2. The voltage level converting circuit according to claim 1, wherein the automatic signal edge detecting module automatically detects a voltage level change of the first signal terminal or the second signal terminal, determines a transmission direction of the voltage level converting circuit module, and controls the transmission direction of the voltage level converting circuit module.
3. The voltage level shifting circuit of claim 2, wherein the automatic signal edge detection module detects a voltage level rising edge of the first signal terminal or the second signal terminal.
4. The voltage level conversion circuit according to claim 1, wherein when the first judgment signal AQ is at a low level and the second judgment signal BQ is at a high level, the voltage level conversion circuit module is controlled to be in a first transmission direction, and signals are transmitted from the first signal terminal to the second signal terminal; when the first judgment signal AQ is at a high level and the second judgment signal BQ is at a low level, the voltage level conversion circuit module is controlled to be at a second transmission direction, and signals are transmitted from the second signal end to the first signal end.
5. The voltage level conversion circuit according to claim 1, wherein the first transistor NM1a, the second transistor NM1b, the third transistor NM2a, the fourth transistor NM2b, and the fifth transistor NM3 are NMOS transistors.
6. The voltage level conversion circuit according to claim 1, wherein the voltage level conversion circuit module specifically includes a first inverter INV0, a first gate inverter INV1, a second inverter INV3, and a second gate inverter INV2;
The input end of the first inverter INV0 is used as a second signal end of the voltage level conversion circuit module, the output end of the first inverter INV0 is connected with the input end of the first gating inverter INV1, the output end of the first gating inverter INV1 is connected with the first signal end, and the control end of the first gating inverter INV1 is used as a second control end of the voltage level conversion circuit module and receives a second judging signal BQ; the input end of the second inverter INV3 is used as the first signal end of the voltage level conversion circuit module, the output end of the second inverter INV3 is connected with the input end of the second gating inverter INV2, the output end of the second gating inverter INV2 is connected with the second signal end, the control end of the first gating inverter INV1 is used as the first control end of the voltage level conversion circuit module, the first judgment signal AQ is received, and the first control end and the second control end of the voltage level conversion circuit module jointly form the control end of the voltage level conversion circuit module.
7. The voltage level converting circuit according to claim 6, wherein when the first judging signal AQ is at a low level and the second judging signal BQ is at a high level, the first gating inverter INV1 is controlled to be inactive and the second gating inverter INV2 is controlled to be active, the voltage level converting circuit module is controlled to be in a first transmission direction, and the signal is transmitted from the first signal terminal to the second signal terminal; when the first judgment signal AQ is at a high level and the second judgment signal BQ is at a low level, the first gating inverter INV1 is controlled to operate, the second gating inverter INV2 is controlled to be not operated, the voltage level conversion circuit module is controlled to be at a second transmission direction, and signals are transmitted from the second signal end to the first signal end.
8. The voltage level conversion circuit according to claim 6 or 7, wherein the first and second gate inverters INV1, INV2 include a third inverter INV4a, a fourth inverter INV4b, a sixth transistor PM4b, a seventh transistor PM4c, an eighth transistor NM4b, a ninth transistor NM4c, respectively;
The input end of the third inverter INV4a is used as the control end of the gating inverter, the output end of the third inverter INV4a is connected with the input end of the fourth inverter INV4b and the gate of the eighth transistor NM4b, the output end of the fourth inverter INV4b is connected with the gate of the sixth transistor PM4b, the gate of the seventh transistor PM4c is connected with the gate of the ninth transistor NM4c and is used as the input end of the gating inverter, the source of the seventh transistor PM4c is connected with the second power supply voltage, the drain of the seventh transistor PM4c is connected with the source of the sixth transistor PM4b, the drain of the sixth transistor PM4b is connected with the drain of the eighth transistor NM4b and is used as the output end of the gating inverter, the source of the eighth transistor NM4b is connected with the drain of the ninth transistor NM4c, and the source of the ninth transistor NM4c is grounded.
9. The voltage level conversion circuit according to claim 8, wherein the sixth transistor PM4b and the seventh transistor PM4c are PMOS transistors, and the eighth transistor NM4b and the ninth transistor NM4c are NMOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410550999.0A CN118138037B (en) | 2024-05-07 | 2024-05-07 | Voltage level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410550999.0A CN118138037B (en) | 2024-05-07 | 2024-05-07 | Voltage level conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118138037A CN118138037A (en) | 2024-06-04 |
| CN118138037B true CN118138037B (en) | 2024-08-02 |
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| CN202410550999.0A Active CN118138037B (en) | 2024-05-07 | 2024-05-07 | Voltage level conversion circuit |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0017656D0 (en) * | 1996-01-03 | 2000-09-06 | Motorola Inc | Bidirectional voltage translator |
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| JPH0535668A (en) * | 1991-07-30 | 1993-02-12 | Toshiba Corp | Signal processor |
| KR100420086B1 (en) * | 1997-04-09 | 2004-04-17 | 삼성전자주식회사 | Voltage conversion circuit of semiconductor device |
| US7061274B2 (en) * | 2003-09-24 | 2006-06-13 | Stmicroelectronics, Inc. | Self-programmable bidirectional buffer circuit and method |
| CN101667824B (en) * | 2008-09-03 | 2011-12-28 | 奕力科技股份有限公司 | Voltage Level Shifting Circuit |
| JP5881432B2 (en) * | 2012-01-20 | 2016-03-09 | 新日本無線株式会社 | Level conversion circuit |
| CN209526709U (en) * | 2019-02-14 | 2019-10-22 | 上海艾为电子技术股份有限公司 | A kind of bidirectional level conversion circuit and two-way level converting chip |
| CN111817705B (en) * | 2020-07-27 | 2021-11-09 | 中国电子科技集团公司第五十八研究所 | Self-induction self-acceleration bidirectional level conversion circuit |
| CN116366050A (en) * | 2023-02-16 | 2023-06-30 | 上海帝迪集成电路设计有限公司 | Bidirectional level conversion device for automatically detecting transmission direction |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| GB0017656D0 (en) * | 1996-01-03 | 2000-09-06 | Motorola Inc | Bidirectional voltage translator |
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