CN116131839A - Single power interface level converter and chip - Google Patents

Abstract

The invention discloses a single power interface level converter and a chip, the single power interface level converter comprises: the first conversion circuit, the second conversion circuit and the buffer work on the same power supply and are connected in sequence; the first conversion circuit is used for receiving an input signal, and carrying out phase inversion and level conversion on the input signal to obtain a first conversion signal; the second conversion circuit is used for receiving the input signal and the first conversion signal, and performing level conversion on the input signal and the first conversion signal to obtain a second conversion signal; the buffer is used for outputting a second conversion signal, the amplitude of the input signal is 0-VIN, the second conversion signal is used as an output signal, the amplitude is 0-VDD, and VDD is the voltage value of the power supply. The scheme of the invention can convert an external logic signal with a level range into a signal suitable for an internal power domain of the chip.

Description

Single power interface level converter and chip

Technical Field

The invention relates to the field of integrated circuits, in particular to a single power interface level converter and a chip.

Background

In integrated circuits (Integrated Circuit, ICs), multi-power domain designs have long become a good solution to optimize chip performance and reduce chip power consumption. The level conversion circuit can ensure that the low power domain signal and the high power domain signal are mutually replaced in the multi-power domain system, so that the normal working requirement of the chip is met. For example, some analog circuits or digital modules in the chip operate in a lower power domain in order to save power consumption, while some critical timing circuits or interface circuits have a certain requirement on the reaction speed and may operate in a higher power domain. The design of the interface circuit is critical in order to meet the clock requirements of the chip or the information exchange requirements with an external controller. If the level of the clock or data signal provided by the external controller does not coincide with the level inside the chip, the interface circuit must fulfil the level shifting function while providing sufficient drive.

In the prior art, the level conversion of the interface circuit is realized by adding two different power domains to the common level conversion, and the power of the interface level of the chip is generally provided by a pin access or a voltage generating circuit inside the chip except for the power inside the chip. The former requires a chip to be added with one pin, which can certainly increase the packaging and manufacturing cost of the chip, and requires external equipment to provide a plurality of voltages, which also increases the cost of an external circuit; the latter requires the generation of a suitable interface power supply, such as a low dropout linear regulator (Low Dropout Regulator, LDO) circuit, by an analog circuit within the chip, while also being independent of the bandgap reference circuit, which increases both the circuit design complexity of the chip and the power consumption of the chip. Secondly, if the chip is operated in a wide voltage range and the interface level is located in the operating voltage range of the chip, the difficulty of generating the interface power supply in the chip is greatly increased.

Disclosure of Invention

The embodiment of the invention provides a single power interface level converter and a chip, which can convert an external logic signal in a level range into a signal suitable for an internal power domain of the chip.

Therefore, the embodiment of the invention provides the following technical scheme:

in one aspect, an embodiment of the present invention provides a single power interface level shifter, including: the first conversion circuit, the second conversion circuit and the buffer work on the same power supply and are connected in sequence; the first conversion circuit is used for receiving an input signal, and carrying out phase inversion and level conversion on the input signal to obtain a first conversion signal; the second conversion circuit is used for receiving the input signal and the first conversion signal, and performing level conversion on the input signal and the first conversion signal to obtain a second conversion signal; the buffer is used for outputting the second conversion signal, the amplitude of the input signal is 0-VIN, the second conversion signal is used as an output signal, the amplitude of the output signal is 0-VDD, and VDD is the voltage value of the power supply.

Optionally, the first conversion circuit includes a pull-up unit and a pull-down unit; the pull-up unit is used for pulling up the level of the first conversion signal to VDD when the level of the input signal is 0; the pull-down unit is used for pulling down the level of the first conversion signal to 0 when the level of the input signal is VIN.

Optionally, the pull-up unit includes: the device comprises an intermediate voltage generating circuit, a first PMOS tube and a capacitor, wherein one end of the capacitor is respectively connected with the output end of the intermediate voltage generating circuit and the source electrode of the first PMOS tube, and the other end of the capacitor is grounded; the pull-down unit includes: the source electrode of the first NMOS tube is grounded; the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, receives the input signal, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and outputs the first conversion signal; the intermediate voltage generating circuit is used for transmitting the voltage of the power supply to the source electrode of the first PMOS tube when the level of the input signal is 0; and the capacitor enables the source voltage of the first PMOS tube to be kept in a stable state.

Optionally, the intermediate voltage generating circuit includes one or more current limiting PMOS transistors, the current limiting PMOS transistors are sequentially connected in series, and a gate of the current limiting PMOS transistor is grounded.

Optionally, a resistor is further connected between the gate of the current-limiting PMOS and ground.

Optionally, the second conversion circuit includes: a first input unit and a second input unit; the first input unit includes: the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube receives the input signal, and the source electrode of the second NMOS tube is grounded; the second input unit includes: the source electrode of the third PMOS tube is connected with the power supply, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube inputs the first conversion signal, and the source electrode of the third NMOS tube is grounded; the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube.

Optionally, the buffer includes: a first inverter and a second inverter connected in series.

Optionally, the first inverter includes: a fourth PMOS tube and a fourth NMOS tube; the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube and is used as the input end of the buffer; the source electrode of the fourth PMOS tube is connected with the power supply, and the source electrode of the fourth NMOS tube is grounded; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and is used as the output end of the first inverter.

Optionally, the second inverter includes: a fifth PMOS tube and a fifth NMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube and is used as the input end of the second inverter; the source electrode of the fifth PMOS tube is connected with the power supply, and the source electrode of the fifth NMOS tube is grounded; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube and is used as the output end of the buffer.

In another aspect, an embodiment of the present invention further provides a chip including the single power interface level shifter described above.

The single power interface level converter provided by the embodiment of the invention only needs one power supply VDD, performs inversion and level conversion on an input signal through the first conversion circuit to obtain a first conversion signal, inputs the input signal and the first conversion signal into the second conversion circuit respectively, performs level conversion on the input signal and the first conversion signal through the second conversion circuit, and outputs the converted second conversion signal through the buffer to obtain an output signal with the amplitude of VDD, thereby converting an external logic signal (namely, the input signal) with a level range into a signal (namely, the output signal) suitable for a power domain inside a chip. The single power interface level converter provided by the embodiment of the invention can meet the application requirement that the input or output high level is selected within a certain range, and the whole circuit can realize the rapid conversion of logic level under the amplitude of an input power, so that the output signal of the amplitude of an internal power can be effectively turned along with the turning of the input signal.

Drawings

Fig. 1 is a schematic diagram of a prior art circuit for implementing level shifting using two different power domains.

Fig. 2 is a schematic diagram of a single power interface level shifter according to an embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of a first conversion circuit according to an embodiment of the present invention.

Fig. 4 is a schematic circuit diagram of a second conversion circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a buffer according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a single power interface level shifter according to an embodiment of the present invention.

Fig. 7 is a schematic waveform diagram of signals in the single power interface level shifter according to an embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

The circuit for performing level shifting using two different power domains in the prior art will be briefly described.

As shown in FIG. 1, the two power domains are VDD and VDDIN, the input signal in and the inverter work in the VDD power domain, the four MOS transistors M1-M4 work in the VDDIN power domain, wherein M1 and M2 are NMOS transistors, and M3 and M4 are PMOS transistors.

When the input signal in is changed from 0 to VDD, M1 is conducted to pull down the drain terminal to 0; accordingly, M4 turns on precharging the out terminal to VDDIN; when the input signal in changes from VDD to "0", M1 turns off and M2 turns on pulling the out terminal low.

The process finishes the transition from the swing of the input signal in between 0 and VDD to the swing of the output signal out between 0 and VDDIN. The input signal in can be toggled between 0 and VDD, but if the system fails to provide VDD power, the circuit also fails to complete the level shifting.

For this reason, an embodiment of the present invention provides a single power interface level shifter, as shown in fig. 2, which is a schematic structural diagram of the single power interface level shifter.

In this embodiment, the single power interface level shifter includes: the first conversion circuit 21, the second conversion circuit 22, and the buffer 23 are sequentially connected, and the first conversion circuit 21, the second conversion circuit 22, and the buffer 23 operate on the same power source, that is, all three are connected to the same power source.

As shown IN fig. 2, the first conversion circuit 21 receives the input signal IN, and performs inversion and level conversion on the input signal IN to obtain a first converted signal INB, where the amplitude of the first converted signal INB may be smaller, larger or equal to the amplitude of the power supply; the second conversion circuit 22 receives the input signal IN and the first conversion signal INB, and performs level conversion on the input signal IN and the first conversion signal INB to obtain a second conversion signal.

In this embodiment, the second conversion signal is output through the buffer 23, and for convenience of description, the signal output from the buffer is referred to as an output signal OUT.

IN a specific application, the input signal IN may be a square wave signal or other waveform signals, such as a sine wave signal, etc., which is not limited IN this embodiment of the present invention, the level amplitude is recorded as 0-VIN, the level amplitude of the output signal is 0-VDD, and VDD is the voltage value of the above power supply. Also, the output signal OUT can be effectively flipped following the flipping of the input signal IN. It should be noted that VIN may be less than, greater than, or equal to VDD, which is not limited in this embodiment of the present invention.

IN one non-limiting embodiment, the first conversion circuit 21 may include a pull-up unit for pulling up the level of the first conversion signal INB to VDD when the level of the input signal IN is 0; the pull-down unit is used for pulling down the level of the first conversion signal INB to 0 when the level of the input signal IN is VIN.

Fig. 3 is a schematic circuit diagram of a first conversion circuit according to an embodiment of the present invention.

In this embodiment, the pull-up unit in the first conversion circuit 21 includes: the intermediate voltage generating circuit 210, the first PMOS MP1, and the capacitor C have one end connected to the output end of the intermediate voltage generating circuit 210 and the source electrode of the first PMOS MP1, i.e. the ND end in fig. 3, and the other end of the capacitor C is grounded. The pull-down unit in the first conversion circuit 21 includes: the source electrode of the first NMOS tube MN1 is grounded; the grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the first NMOS tube MN1, and receives an input signal IN, the drain electrode of the first PMOS tube MP1 is connected with the drain electrode of the first NMOS tube MN1, and outputs a first conversion signal INB.

The intermediate voltage generating circuit 210 is configured to transmit the voltage of the power supply to the source, i.e., the ND end, of the first PMOS MP1 when the input signal IN is 0; the capacitor C keeps the source voltage of the first PMOS tube MP1 in a stable state.

Further, in a specific application, the intermediate voltage generating circuit 210 may include one or more current-limiting PMOS transistors, where there are multiple current-limiting PMOS transistors, the multiple current-limiting PMOS transistors are sequentially connected in series, and the gate of the current-limiting PMOS transistor is grounded. As shown in fig. 3, in this embodiment, four PMOS transistors are connected in series, where the four PMOS transistors are respectively: MP11, MP12, MP13, MP14. It should be noted that, the number of PMOS transistors may be determined according to needs, which is not limited in this embodiment of the present invention.

Further, a resistor R can be connected between the grid electrode of the current-limiting PMOS tube and the ground, so that the current-limiting effect can be achieved, and the ground potential jitter is prevented from breaking down the MOS tube.

Fig. 4 is a schematic circuit diagram of a second conversion circuit according to an embodiment of the present invention.

In this embodiment, the second conversion circuit 22 includes a first input unit and a second input unit. Wherein the first input unit includes: the source electrode of the second PMOS tube MP2 is connected with the power supply VDD, the drain electrode of the second PMOS tube MP2 is connected with the drain electrode of the second NMOS tube MN2, the grid electrode of the second NMOS tube MN2 receives the input signal IN, and the source electrode of the second NMOS tube MN2 is grounded. Wherein the second input unit includes: the third PMOS tube MP3 and the third NMOS tube MN3, the source electrode of the third PMOS tube MP3 is connected with the power supply VDD, the drain electrode of the third PMOS tube MP3 is connected with the drain electrode of the third NMOS tube MN3, the grid electrode of the third NMOS tube MN3 inputs the first conversion signal INB, and the source electrode of the third NMOS tube MN3 is grounded.

In addition, the gate of the second PMOS transistor MP2 is connected to the drain of the third PMOS transistor MP3, i.e. the X terminal in fig. 4, and the gate of the third PMOS transistor MP3 is connected to the drain of the second PMOS transistor MP2, i.e. the Y terminal in fig. 4, and the Y terminal is used as the output terminal of the second conversion circuit 22, and outputs the second conversion signal to the buffer.

Fig. 5 is a schematic circuit diagram of a buffer according to an embodiment of the present invention.

In this embodiment, the buffer includes: a first inverter and a second inverter connected in series. Wherein the first inverter includes: a fourth PMOS tube MP4 and a fourth NMOS tube MN4; the gate of the fourth PMOS MP4 is connected to the gate of the fourth NMOS MN4, and is used as the input end of the buffer, i.e. the end in fig. 5; the source electrode of the fourth PMOS tube MP4 is connected with the power supply VDD, and the source electrode of the fourth NMOS tube MN4 is grounded; the drain electrode of the fourth PMOS tube MP4 is connected with the drain electrode of the fourth NMOS tube MN4 and is used as the output end of the first inverter. Wherein the second inverter includes: a fifth PMOS tube MP5 and a fifth NMOS tube MN5; the grid electrode of the fifth PMOS tube MP5 is connected with the grid electrode of the fifth NMOS tube MN5 and is used as the input end of the second inverter; the source electrode of the fifth PMOS tube MP5 is connected with the power supply VDD, and the source electrode of the fifth NMOS tube MN5 is grounded; the drain electrode of the fifth PMOS MP5 is connected to the drain electrode of the fifth NMOS MN5, and is used as the output end of the buffer, i.e. the Z end in fig. 5.

Referring to fig. 6, a specific circuit schematic of a single power interface level shifter according to an embodiment of the present invention is shown. The operation of the single power interface level shifter according to the embodiment of the present invention will be described in detail with reference to fig. 6.

Firstly, it should be noted that in the single power interface level converter, all PMOS transistors are transistors of the same type, and all NMOS transistors are transistors of the same type. In the invention, VDD is the power supply voltage and corresponds to the logic high level of the output signal; GND is ground, defaulting to 0V, corresponding to the logic low level of the input and output signals. VIN is the high level of the input logic signal IN.

The level converter of the single power interface of the embodiment of the invention has the level amplitude of the input signal of 0-VIN and the level amplitude of the output signal of 0-VDD. Wherein VIN < VDD. The converter power supply has and only VDD and can implement level shifting from input to output.

When the input IN signal is low, the first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, and the power supply VDD is transmitted to the INB terminal through MP 11-MP 14. Under the condition that the high level VIN of the IN signal of the input end is slightly larger than the threshold value of the first NMOS tube MN1, the VIN voltage can be ensured to be pulled to 0V by designing the width-to-length ratio of the first NPMOS tube MN1, namely the first NMOS tube MN1 has strong enough pull-down capability, and the level conversion circuit at the back can be ensured to distinguish the high level and the low level of the INB end. The second NMOS transistor MN2 and the third NMOS transistor MN3 are designed similarly, and it is required to ensure that the X terminal and the Y terminal can be pulled down to 0V. The width-to-length ratio of MP 11-MP 14 can be designed smaller and all work in a linear region, and can effectively reduce the circuit power consumption by being used as a limiting tube, wherein a certain voltage drop exists at the source-drain end of each PMOS tube, so that the level of the ND point is at a certain potential between 0 and VDD, and the voltage of the ND point is maintained in a stable state by the capacitor C. Even if the first PMOS transistor MP1 has an obvious body effect (i.e., the larger the source voltage is, the larger the threshold voltage is), resulting IN the larger threshold voltage, when the input signal IN is 0, the first PMOS transistor MP1 is turned on, the ND point voltage is transferred to the INB terminal, and is used as a high level to control the conduction of the third NMOS transistor MN3, and the output terminal is pulled down to 0V.

When the input signal is at the high level VIN, the first NMOS transistor MN1 is turned on, the pull-down capability of the first NMOS transistor MN1 enables the INB terminal to be pulled down to 0V, at this time, the second NMOS transistor MN2 is turned on, and the third NMOS transistor MN3 is turned off. Correspondingly, the second PMOS transistor MP2 is turned off, and the third PMOS transistor MP3 is turned on, so that the voltage VDD is transferred to the output terminal OUT through the buffer 23. This completes the level shift under the condition of only one power supply.

It should be noted that, according to the application requirement, the frequency of the input logic signal IN may be selected within a certain range, the sizes of MP11 to MP14 have a certain constraint on the frequency of the input logic signal IN, the power consumption may be controlled by reducing the aspect ratio, and the reaction speed may be improved by increasing the aspect ratio. In a specific application, the size of each MOS transistor in the single power interface level converter according to the embodiment of the present invention may be adjusted according to actual requirements, so as to ensure that the first NMOS transistor MN1 and the second NMOS transistor MN2 can be turned on and pulled down strongly when the input signal is at the high level VIN. In addition, the power supply voltage range is not larger than the withstand voltage value of the selected MOS tube.

Taking a square wave signal with an input signal IN of 500kHz, the input signal has a high level VIN of 1V and vdd of 5V as an example, the single power interface level shifter according to the embodiment of the present invention can obtain the waveform diagram shown IN fig. 7.

Referring to fig. 7, when the input terminal IN is 0V, the first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, the capacitor C slowly raises the ND terminal voltage, and the ND terminal voltage average value is about 3V and is transferred to the INB terminal; when the input end level is 1V, the first NMOS transistor MN1 is turned on, and the pull-down capability of the first NMOS transistor MN1 is stronger than the pull-up capability of the first PMOS transistor MP1, and the INB end is pulled down to 0V.

Therefore, IN the case where the level range of the input terminal IN is 0 to 1V, the level range of the INB terminal is about 0 to 3V. Correspondingly, when the level of the input end IN is 0V, the INB end is 3V, the second NMOS transistor MN2 is turned off, the third NMOS transistor MN3 is turned on, the Y end is pulled down to GND, and the 0V voltage is output as 0V through the buffer 23; when the level of the input end IN is 1V, the INB end is 0V, at this time, the second NMOS MN2 is turned on and the pull-down capability is strong, the third NMOS MN3 is turned off, the X end is pulled down to turn on the third PMOS MP3, the power voltage is transferred to the Y end and outputted to VDD through the buffer, and thus the level conversion from 1V to 5V is completed.

The single power interface level converter provided by the embodiment of the invention can convert an input signal with one amplitude into an output with another amplitude, and only one power supply VDD is needed. The converter can meet the requirement that the level of input or output is selected in a certain range, the whole circuit can realize the quick conversion of logic level under the amplitude of an input power supply, so that an output signal with the amplitude of an internal power supply can be effectively turned over along with the turning of the input signal, thereby effectively solving the application scenario that the input signal level in an interface circuit is different from an internal power supply and has no power supply with the same level as the input signal level, improving the input-output voltage range and effectively controlling the power consumption.

The single power interface level converter provided by the embodiment of the invention realizes the level conversion under the condition that only one internal power supply exists and an input signal cannot provide power supply, and solves the problems of design cost and the like caused by the fact that an intermediate level generating circuit is required to generate an interface power supply in the prior art; moreover, a certain input level range and a larger power supply voltage range can be supported, and the application requirements of realizing rapid level conversion of interface input signals under different frequencies are met.

Correspondingly, the embodiment of the invention also provides a chip comprising the single power interface level converter, which can convert an external logic signal with a level range into a signal with a level range suitable for an internal power domain of the chip.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (10)

1. A single power interface level shifter, comprising: the first conversion circuit, the second conversion circuit and the buffer work on the same power supply and are connected in sequence;

the first conversion circuit is used for receiving an input signal, and carrying out phase inversion and level conversion on the input signal to obtain a first conversion signal;

the second conversion circuit is used for receiving the input signal and the first conversion signal, and performing level conversion on the input signal and the first conversion signal to obtain a second conversion signal;

the buffer is used for outputting the second conversion signal, the amplitude of the input signal is 0-VIN, the second conversion signal is used as an output signal, the amplitude of the output signal is 0-VDD, and VDD is the voltage value of the power supply.

2. The single power interface level shifter of claim 1, wherein the first conversion circuit comprises a pull-up unit and a pull-down unit;

the pull-up unit is used for pulling up the level of the first conversion signal to VDD when the level of the input signal is 0;

the pull-down unit is used for pulling down the level of the first conversion signal to 0 when the level of the input signal is VIN.

3. The single power interface level shifter of claim 2, wherein the pull-up unit comprises: the device comprises an intermediate voltage generating circuit, a first PMOS tube and a capacitor, wherein one end of the capacitor is respectively connected with the output end of the intermediate voltage generating circuit and the source electrode of the first PMOS tube, and the other end of the capacitor is grounded; the pull-down unit includes: the source electrode of the first NMOS tube is grounded; the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube, receives the input signal, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube and outputs the first conversion signal;

the intermediate voltage generating circuit is used for transmitting the voltage of the power supply to the source electrode of the first PMOS tube when the level of the input signal is 0; and the capacitor enables the source voltage of the first PMOS tube to be kept in a stable state.

4. The single power interface level shifter of claim 3, wherein the intermediate voltage generation circuit comprises one or more current limiting PMOS transistors connected in series in sequence, and wherein the gates of the current limiting PMOS transistors are grounded.

5. The single power interface level shifter of claim 4, wherein a resistor is further connected between the gate of the current limiting PMOS transistor and ground.

6. The single power interface level shifter of any one of claims 1-5, wherein the second conversion circuit comprises: a first input unit and a second input unit;

the first input unit includes: the source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube receives the input signal, and the source electrode of the second NMOS tube is grounded;

the second input unit includes: the source electrode of the third PMOS tube is connected with the power supply, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube inputs the first conversion signal, and the source electrode of the third NMOS tube is grounded;

the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube.

7. The single power interface level shifter of claim 6, wherein the buffer comprises: a first inverter and a second inverter connected in series.

8. The single power interface level shifter of claim 7, wherein the first inverter comprises: a fourth PMOS tube and a fourth NMOS tube; the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube and is used as the input end of the buffer; the source electrode of the fourth PMOS tube is connected with the power supply, and the source electrode of the fourth NMOS tube is grounded; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube and is used as the output end of the first inverter.

9. The single power interface level shifter of claim 7, wherein the second inverter comprises: a fifth PMOS tube and a fifth NMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fifth NMOS tube and is used as the input end of the second inverter; the source electrode of the fifth PMOS tube is connected with the power supply, and the source electrode of the fifth NMOS tube is grounded; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fifth NMOS tube and is used as the output end of the buffer.

10. A chip comprising a single power interface level shifter as claimed in any one of claims 1 to 9.

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