[go: up one dir, main page]

CN118085870A - Etching solution, etching method and preparation method of array substrate - Google Patents

Etching solution, etching method and preparation method of array substrate Download PDF

Info

Publication number
CN118085870A
CN118085870A CN202410067272.7A CN202410067272A CN118085870A CN 118085870 A CN118085870 A CN 118085870A CN 202410067272 A CN202410067272 A CN 202410067272A CN 118085870 A CN118085870 A CN 118085870A
Authority
CN
China
Prior art keywords
etching
layer
metal layer
weight
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410067272.7A
Other languages
Chinese (zh)
Inventor
宋智辉
袁海江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Changsha HKC Optoelectronics Co Ltd
Original Assignee
HKC Co Ltd
Changsha HKC Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Changsha HKC Optoelectronics Co Ltd filed Critical HKC Co Ltd
Priority to CN202410067272.7A priority Critical patent/CN118085870A/en
Publication of CN118085870A publication Critical patent/CN118085870A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/08—Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Weting (AREA)

Abstract

The application relates to the technical field of semiconductor metal wiring, in particular to an etching solution, an etching method and a preparation method of an array substrate, and provides the etching solution, which comprises 8-15 parts by weight of an oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of a chelating agent, 2-5 parts by weight of organic base, less than or equal to 2 parts by weight of azole compounds, less than or equal to 3 parts by weight of an anti-potential etching agent and 60-85 parts by weight of a solvent. The metal layer and the semiconductor layer in the array substrate are etched by the etching liquid by one wet etching and one dry etching, so that the problem of tailing of amorphous silicon layer etching is successfully solved, and two wet etching and two dry etching are reduced to one wet etching and one dry etching, so that the production yield and the production efficiency of the array substrate are increased, the consumption of the etching liquid is reduced, and the production cost is reduced.

Description

Etching solution, etching method and preparation method of array substrate
Technical Field
The application relates to the technical field of semiconductor metal wiring, in particular to etching solution, an etching method and a preparation method of an array substrate.
Background
In the LCD panel manufacturing technology, in the process of forming the second metal layer, because the amorphous silicon layer, the metal line and the trench of the second metal layer are etched, two wet etching and two dry etching are required, and if the productivity is required to be increased, the two wet etching and the two dry etching can be reduced to one wet etching and one dry etching.
The first wet etching and the first dry etching are performed by removing the second metal layer at the peripheral portion, and then removing the second metal layer at the middle portion of the corresponding channel layer and removing a part of the amorphous silicon layer corresponding to the channel layer and a part of the amorphous silicon layer at the periphery. However, the method has high requirement on one dry etching step, and the peripheral amorphous silicon layer is easy to be removed completely, so that serious tailing of the amorphous silicon layer is formed. The existence of the amorphous silicon layer tailing is equivalent to widening of the source-drain wiring, so that parasitic capacitance between the source-drain and the pixel is increased, and the pixel voltage is reduced. In addition, because the peripheral amorphous silicon layer cannot be completely etched and removed, the risk of short circuit is high, and the defect rate is high in the later period.
Therefore, an etching solution and an etching method are needed to solve the above technical problems.
Disclosure of Invention
In view of the above, the present application mainly solves the technical problem of providing an etching solution, an etching method and a preparation method of an array substrate, which can improve the technical problem of high defective rate of a display panel caused by tailing of an amorphous silicon layer during etching.
In order to solve the technical problems, the application adopts a technical scheme that:
Provided is an etching liquid, which comprises: 8-15 parts by weight of oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of chelating agent, 2-5 parts by weight of organic base, less than or equal to 2 parts by weight of azole compound, less than or equal to 3 parts by weight of anti-potential etching agent and 60-85 parts by weight of solvent.
Further, the etching solution comprises the following components in percentage by weight: 8-15wt% of oxidant, 500-6000 ppm of fluoride, 3-6wt% of chelating agent, 2-5wt% of organic base, 0-2wt% of azole compound, 0-3wt% of anti-potential etching agent and the balance of solvent.
Further, the weight percentage of the oxidizing agent is 14wt% or less.
Further, the fluoride content is 3000ppm to 6000ppm.
Further, the pH value of the etching solution is 3-6.
The application also comprises a second technical scheme, an etching method, which comprises the following steps:
Forming a semiconductor layer on a substrate;
forming a metal layer on one side of the semiconductor layer away from the substrate;
forming a patterned photoresist layer on one side of the metal layer away from the substrate; the patterned photoresist layer comprises a first sub-photoresist layer and a second sub-photoresist layer;
And performing one-time wet etching on the metal layer and the semiconductor layer by using the patterned photoresist layer as a mask, and removing the metal layer and the semiconductor layer which are not covered by the photoresist layer.
Further, the semiconductor layer is an amorphous silicon layer; and/or
The metal layer comprises a single-layer metal layer made of Al, mo, cu, ti, ni or Nb, or a composite metal layer made of Mo/Al/Mo, mo/Cu/Mo or Mo/Cu; and/or
The temperature range of the one-time wet etching is 28-33 ℃; and/or
The time of one-time wet etching is 60-160 seconds.
The application also comprises a third technical scheme, and a preparation method of the array substrate comprises the following steps:
forming a first metal layer on a substrate; the first metal layer includes a gate line and a gate electrode;
Covering a first insulating layer on one side of the first metal layer far away from the substrate;
forming a semiconductor layer on one side of the first insulating layer away from the substrate;
forming a second metal layer on one side of the semiconductor layer away from the substrate;
Forming a patterned photoresist layer on one side of the second metal layer away from the substrate; the patterned photoresist layer comprises a first sub-photoresist layer and a second sub-photoresist layer; the thickness of the first sub-photoresist layer is larger than that of the second sub-photoresist layer;
Performing one-time wet etching on the second metal layer and the semiconductor layer by using the patterned photoresist layer as a mask, removing the second metal layer and the semiconductor layer which are not covered by the photoresist layer, and reserving the second metal layer covered by the photoresist layer;
Removing the second metal layer covered by the second sub-photoresist layer by dry etching to form an opening, so that the semiconductor layer covered by the second sub-photoresist layer is exposed; the second metal layer comprises a data line, a source electrode and a drain electrode;
The exposed semiconductor layer is etched using dry etching.
Further, the semiconductor layer is an amorphous silicon layer; and/or
The metal layer comprises a single-layer metal layer made of Al, mo, cu, ti, ni or Nb, or a composite metal layer made of Mo/Al/Mo, mo/Cu/Mo or Mo/Cu; and/or
The temperature range of the one-time wet etching is 28-33 ℃; and/or
The time of one-time wet etching is 60-160 seconds.
Further, removing the second metal layer covered by the second sub-photoresist layer by dry etching to form an opening and etching the exposed semiconductor layer by dry etching to perform dry etching for the same time by using the same etching machine; wherein,
In the step of removing the second metal layer covered by the second sub-photoresist layer to form an opening by dry etching, etching gas is adopted to comprise one or more of SF6、NF3、SiCl4、Cl2、Br2、HBr、BCl3、Ar、N2、CHF3、C2H4, the etching time is 120-300 seconds, and the etching power is PS (PS) 7-12k and PB (poly (PB)) 5-10k;
In the step of etching the exposed semiconductor layer by dry etching, the etching gas comprises one or more of SF6、NF3、BCl2、SiCl4、Cl2、Br2、HBr、BCl3、O2、Ar, the etching time is 10-30 seconds, and the etching power is PS 7-12k and PB 5-10k.
The beneficial effects of the application are as follows: compared with the prior art, the application provides an etching solution which comprises 8-15 parts by weight of oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of chelating agent, 2-5 parts by weight of organic base, less than or equal to 2 parts by weight of azole compound, less than or equal to 3 parts by weight of anti-potential etching agent and 60-85 parts by weight of solvent. The etching solution provided by the application can be applied to one-time wet etching of the metal layer and the semiconductor layer which are stacked by taking the patterned photoresist layer as a mask, and the metal layer and the semiconductor layer which are not covered by the photoresist layer are removed by one-time wet etching through the synergistic effect of the components, the oxidizing agent reacts with the metal layer, and the fluoride reacts with the semiconductor layer, so that the etching effect of the etching solution is enhanced; moreover, the fluoride content is high, so that the fluoride reacts with the semiconductor layer sufficiently, and the problem of tailing of the semiconductor layer can be solved. The etching solution provided by the application is applied to the preparation process of the array substrate of the display panel, so that the production yield of the display panel can be increased.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is evident that the figures in the following description are only some embodiments of the application, from which other figures can be obtained without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a flow chart of an etching method according to an embodiment of the application;
FIG. 2 is a process flow diagram of an etching method according to one embodiment of the present application;
FIG. 3 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the application;
FIG. 4 is a process flow diagram of a method for manufacturing an array substrate according to an embodiment of the present application;
FIG. 5 is a scanning electron microscope photograph of a semiconductor channel formed after etching by one wet etching and one dry etching processes using an etching liquid composition according to an embodiment of the present application;
FIG. 6 is a scanning electron microscope photograph of an edge of a metal line formed after etching by one wet etching and one dry etching processes using an etchant composition according to an embodiment of the present application;
Fig. 7 is a partial enlarged view of fig. 6.
Reference numerals illustrate:
120-metal layer; 100-a substrate; 110-a semiconductor layer; 130-a photoresist layer; 120 a-a first metal layer; 120 b-a second metal layer; 140-a first insulating layer; 131-a first sub-photoresist layer; 132-a second sub-photoresist layer;
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.
The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The embodiment of the application provides an etching solution, which is shown in a table A, and comprises 8-15 parts by weight of an oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of a chelating agent, 2-5 parts by weight of an organic base, 2 parts by weight or less of an azole compound, 3 parts by weight or less of an anti-potential etching agent and 60-85 parts by weight of a solvent.
In one embodiment of the application, the etching solution comprises, by weight, 8-15% of an oxidant, 500-6000 ppm of fluoride, 3-6% of a chelating agent, 2-5% of an organic base, 0-2% of an azole compound, 0-3% of an anti-potential etching agent, and the balance of a solvent.
With continued reference to Table A, in one embodiment of the application, the oxidizer is hydrogen peroxide. The oxidizing agent acts to react with the metal layer to etch the metal layer.
Preferably, the parts by weight of the oxidizing agent is less than 15 parts, for example, 8-14wt% of the oxidizing agent. Because the weight percentage of the oxidant is less than or equal to 14wt%, the reaction speed of the oxidant and the metal layer is not too high, and metal ions (such as copper ions) generated by the reaction can be timely chelated with the chelating agent to form a stable compound, so that the phenomenon of unstable etching caused by the fact that the content of the metal ions (such as copper ions) in the solution is too high is reduced. If the weight percentage of the oxidizing agent is more than or equal to 15wt%, the reaction speed of the oxidizing agent and the metal layer is too high, a-Si remains after the metal layer is etched to a specified line width, and if the reaction time is increased continuously, the etching of a-Si can cause overetching of the metal.
In one embodiment of the present application, the fluoride is one or more of sodium fluoride, potassium fluoride, aluminum fluoride, boric acid, ammonium fluoride, ammonium bifluoride, sodium bifluoride, potassium bifluoride, ammonium fluoroborate and hafnium fluoride. The fluoride is used for reacting with the oxide on the surface of the metal layer to remove the oxide on the surface of the metal layer, so that the oxidant can react with the metal layer, and on the other hand, the fluoride reacts with the semiconductor layer to etch the semiconductor layer.
Preferably, the fluoride content is higher than 1000ppm, for example, the fluoride content is 1000ppm to 6000ppm. More preferably, the fluoride content is higher than 2000ppm, and by increasing the fluoride content to 2000ppm or higher, the semiconductor layer can be removed more cleanly, and the effect is more remarkable particularly for an amorphous silicon semiconductor layer. If the fluoride content is higher than 6000ppm, an endo-etching phenomenon of the a-Si layer occurs, and at the same time, damage to the glass substrate increases, mura problems occur, and chipping risks occur.
In one embodiment of the application, the chelating agent is an organic acid. In the application, the organic acid can be chelated with the metal ions to form a stable compound, so that the copper ions in the metal layer 120 are more stably etched in the solution, the concentration of the copper ions in the solvent is reduced, the stable etching period of the etching solution is prolonged, and the etching effect of the etching solution is enhanced.
Preferably, the mass fraction of chelating agent is greater than 3 parts, for example, the weight percentage of chelating agent is 3-6wt%. Because the weight percentage of the chelating agent is more than 3wt%, metal ions (such as copper ions) generated by the reaction can be chelated with the chelating agent in time to form stable compounds, the phenomenon of unstable etching caused by the fact that the content of the metal ions (such as copper ions) in a solution is too high is reduced, in addition, the cost is increased when the additive is more, and the etching morphology is influenced. More preferably, the chelating agent is less than or equal to 5wt% in part by weight, so that the cost can be reduced without affecting the etching morphology.
In one embodiment of the application, the chelating agent is an amino acid.
In one embodiment of the present application, the chelating agent comprises one or more of alanine, malonic acid, malic acid, iminodiacetic acid, nitrilotriacetic acid, glutamic acid.
In one embodiment of the present application, the organic base comprises one or more of diethanolamine, triethanolamine, propanolamine. In the application, the organic alkali helps the metal substances formed after oxidation to fall off from the metal surface, and the organic alkali can adjust the pH of the etching solution.
Preferably, the mass fraction of organic base is greater than 2 parts, for example, the weight percentage of organic base is 2-5wt%. More preferably, the weight percentage of organic base is greater than 3wt%. Because the weight percentage of the organic alkali is more than 3wt%, the metal substances formed by oxidizing the oxidizing agent rapidly fall off from the surface of the metal layer, and the problem that the metal substances formed by oxidizing cannot fall off in time to block the etching of the metal layer below is avoided. The present patent can have a faster etching rate before maintaining the etching stability by 3wt% or more of the chelating agent and 2wt% or more of the organic base.
In an embodiment of the present application, the mass fraction of the azole compound in the etching solution is preferably greater than 0, for example, the weight percentage of the azole compound is 0.01-2wt%. The azole compound comprises one or more of benzotriazole, aminotetrazole, 1, 2, 4-triazole and the like. In the application, the azole compound has the function of adjusting the shape of the etched metal section so as to flatten the etched metal section.
In an embodiment of the present application, the mass fraction of the anti-potential etchant in the etching solution is preferably greater than 0, for example, the weight percentage of the anti-potential etchant is 0.01-3wt%. The anti-potential etchant comprises one or more of phosphoric acid and phosphate. In the application, the problem of large potential difference in the etching solution of the metal layer 120 is regulated by the anti-potential etchant, so that the etching angle is improved, etching defects are reduced, the profile of the metal layer 120 after etching is smooth, and the defect problems such as inscribed chamfering and the like are improved.
In one embodiment of the present application, the solvent is deionized water.
Table A Components of etching solution
In one embodiment of the present application, the pH of the etching solution is 3-6.
The etching solution provided by the application comprises 8-15 parts by weight of oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of chelating agent, 2-5 parts by weight of organic base, less than or equal to 2 parts by weight of azole compound, less than or equal to 3 parts by weight of anti-potential etching agent and 60-85 parts by weight of solvent. The etching solution provided by the application can be applied to the one-time wet etching of the metal layer 120 and the semiconductor layer 110 which are stacked by taking the patterned photoresist layer 130 as a mask, and the metal layer is reacted with the oxidant and the semiconductor layer by the synergistic effect of the components, so that the metal layer 120 and the semiconductor layer 110 which are not covered by the photoresist layer 130 are removed by the one-time wet etching, and the etching effect of the etching solution is enhanced; further, since the fluoride content is high, the reaction with the semiconductor layer is sufficient, and the problem of tailing of the semiconductor layer 110 can be improved. The etching solution provided by the application is applied to the preparation process of the array substrate of the display panel, so that the production yield of the display panel can be increased. The following examples are illustrative.
As shown in fig. 1 and 2, the present application further provides an etching method, which includes the following steps:
s11: forming a semiconductor layer 110 on a substrate 100;
s12: forming a metal layer 120 on a side of the semiconductor layer 110 away from the substrate 100;
S13: forming a patterned photoresist layer 130 on a side of the metal layer 120 away from the substrate 100;
S14: the metal layer 120 and the semiconductor layer 110 are subjected to one-time wet etching by using the patterned photoresist layer 130 as a mask, and the metal layer 120 and the semiconductor layer 110 which are not covered by the photoresist layer 130 are removed.
In step S11, the semiconductor layer 110 is an amorphous silicon layer, and the thickness may be 50nm to 200nm. The material of the semiconductor layer 110 is not limited, and a metal oxide semiconductor may be used.
In step S12, the metal layer 120 includes a single metal layer of Al, mo, cu, ti, ni, or Nb, and in other embodiments, the metal layer 120 includes a composite metal layer of Mo/Al/Mo, mo/Cu/Mo, or Mo/Cu. The thickness of the metal layer 120 may be 300nm-800nm.
In the step S14, the temperature range of the one-time wet etching is 28-33 ℃; the time of one-time wet etching is 60-160 seconds.
As shown in fig. 3 and 4, the present application further provides a method for preparing an array substrate, including the following steps:
S21, forming a first metal layer 120a on the substrate 100; the first metal layer 120a includes a gate line and a gate electrode;
s22, covering the first insulating layer 140 on the side of the first metal layer 120a away from the substrate 100;
s23, forming a semiconductor layer 110 on a side of the first insulating layer 140 away from the substrate 100;
s24, forming a second metal layer 120b on a side of the semiconductor layer 110 away from the substrate 100;
S25, forming a patterned photoresist layer 130 on the side of the second metal layer 120b away from the substrate 100; the patterned photoresist layer 130 includes a first sub-photoresist layer 131 and a second sub-photoresist layer 132; the thickness of the first sub-photoresist layer 131 is greater than the thickness of the second sub-photoresist layer 132;
S26, using the patterned photoresist layer 130 as a mask, performing one-time wet etching on the second metal layer 120b and the semiconductor layer 110 by adopting the etching solution, removing the second metal layer 120b and the semiconductor layer 110 which are not covered by the photoresist layer 130, and retaining the second metal layer 120b covered by the photoresist layer 130;
S27, removing the second metal layer 120b covered by the second sub-photoresist layer 132 by dry etching to form an opening, so that the semiconductor layer 110 covered by the second sub-photoresist layer 132 is exposed; wherein the second metal layer 120b includes a data line, a source electrode, and a drain electrode;
and S28, etching the exposed semiconductor layer 110 by adopting dry etching.
The array substrate of the application can be an array substrate of a liquid crystal display panel, or an array substrate of other display panels such as an LED or an OLED. The application will be described by taking an array substrate of a liquid crystal display panel as an example. The array substrate of the liquid crystal display panel can be arranged opposite to the opposite substrate to prepare the liquid crystal display panel.
In step S21, the substrate 100 is a glass substrate. The first metal layer 120a may comprise a single layer metal layer of material Al, mo, cu, ti, ni, or Nb, in other embodiments, the first metal layer 120a comprises a composite metal layer of material Mo/Al/Mo, mo/Cu/Mo, or Mo/Cu. The thickness of the first metal layer 120a may be 300nm to 800nm.
In step S22, the first insulating layer 140 may include one or more of a silicon oxide layer and a silicon nitride layer.
In step S23, the semiconductor layer 110 is an amorphous silicon layer, and the thickness may be 50nm to 200nm. The material of the semiconductor layer 110 is not limited, and a metal oxide semiconductor may be used.
In step S24, the second metal layer 120b includes a single metal layer of Al, mo, cu, ti, ni a or Nb. In other embodiments, the second metal layer 120b includes a composite metal layer of a material Mo/Al/Mo, mo/Cu/Mo, or Mo/Cu. The thickness of the second metal layer 120b may be 300nm to 800nm.
In step S25, the patterned photoresist layer 130 is formed by exposure. The exposure is performed by adopting a half mask, and the film thickness of a photoresist layer corresponding to the half light transmission position of the half mask is lower than that of other positions, so that the patterned photoresist layer 130 comprises a first sub-photoresist layer 131 and a second sub-photoresist layer 132; the thickness of the first sub-photoresist layer 131 is greater than the thickness of the second sub-photoresist layer 132.
In step S26, the temperature range of the one-time wet etching is 28-33 ℃; the time of one-time wet etching is 60-160 seconds.
In step S27, the second metal layer 120b covered by the second sub-photoresist layer 132 is removed by dry etching to form an opening, which is the same dry etching as the exposed semiconductor layer 110 by dry etching. The dry etching is plasma dry etching. The dry etching is used to remove one or more of NH3、NF3、SF6、SiCl4、Cl2、Br2、HBr、BCl3、Ar、N2、CHF3、C2H4, 120-300 seconds, and the etching power is PS 7-12k and pb 5-10k, which are used to form the opening of the second metal layer 120b covered by the second sub-photoresist layer 132. The exposed semiconductor layer 110 is etched using dry etching using one or more of the etching gases SF6、NF3、BCl2、SiCl4、Cl2、Br2、HBr、BCl3、O2、Ar for 10-30 seconds with a power of PS:7-12k and pb:5-10k. Etching the exposed semiconductor layer 110 by dry etching removes only a portion of the surface of the semiconductor layer 110, ensuring that the second metal layer 120b is completely disconnected at the opening, forming a source electrode and a drain electrode.
It is understood that step S28 is followed by a step of removing the patterned photoresist layer 130, and other steps of preparing the array substrate.
The following are specific examples and comparative examples of the preparation method of the array substrate provided by the present application. The application only gives the relevant parameters of the second metal layer and the semiconductor layer.
Example 1
In embodiment 1, the semiconductor layer 110 is amorphous silicon layer a-Si, with a thickness of 100nm; the second metal layer 120b is made of a Mo/Cu composite layer and has a thickness of 500nm; the etching liquid adopted by the one-time wet etching is the etching liquid, the etching temperature is 30 ℃, and the etching time is 100 seconds; the etching gas adopted in the first dry etching of the second metal layer 120b is a mixed gas of NH3, NF3 and Cl 2、BCl3、Ar、N2、CHF3、C2H4, the etching Power is PS (Power of Source):10k, and the etching time is 200 seconds; the etching gas used for the first dry etching of the semiconductor layer 110 is a mixed gas of Cl 2、O2、SF6、NF3 and Ar, the etching power is PS 10k, and the etching time is 20 seconds. The etching solution used in example 1 consisted of, in weight percent, 12% hydrogen peroxide (oxidizer), 0.4% sodium fluoride (4000 ppm fluoride), 4% alanine (chelating agent), 4% diethanolamine (organic base), 1% benzotriazole (azole compound), 2% phosphoric acid (anti-potential etchant), and the balance deionized water (solvent).
Comparative example 1A
The parameters of comparative example 1A were substantially the same as those of example 1, except that the etching solution used in comparative example 1A did not include fluoride.
Comparative example 1B
The parameters of comparative example 1B were substantially the same as in example 1, except that the etching solution used in comparative example 1B did not include a chelating agent.
Comparative example 1C
The parameters of comparative example 1C were substantially the same as in example 1, except that the etching solution used in comparative example 1C did not include an organic base.
Comparative example 1D
The parameters of comparative example 1D were substantially the same as those of example 1, except that the etching solution used in comparative example 1D had an oxidizer content of 20wt%, a fluoride content of 0.1wt% (i.e., 1000 ppm), a chelating agent content of 4wt% and an organic base content of 2wt%.
The results of the above examples and comparative examples are shown in table 1 below.
TABLE 1
As shown in fig. 5 to 7, in embodiment 1, after one wet etching and one dry etching (1W 1D), the trench of the semiconductor layer 110 is etched completely by the dry etching, and the amorphous silicon layer is etched to a thickness of a portion, wherein the etching thickness of the amorphous silicon layer is less than or equal to 50nm, no metal etching residue is left in the middle of the trench, the surface of the amorphous silicon is relatively flat, the tailing of the amorphous silicon is improved, and no metal residue is left after the metal etching on the outer side.
Example 2
The parameters of example 2 are basically the same as those of example 1, except that the etching solution used in example 2 is different in the content of the oxidizing agent, wherein examples 2-1, 2-2, 2-3 and 2-4 are marked as examples, respectively, according to the content of the oxidizing agent.
Comparative example 2
The parameters of comparative example 2 are substantially the same as those of example 1, except that comparative example 2 employs an etching solution having a different content of an oxidizing agent, wherein comparative examples 2A and 2B are marked as comparative examples 2A and 2B, respectively, depending on the content of the oxidizing agent.
The results of the above examples and comparative examples are shown in table 2 below.
TABLE 2
Example 3
The parameters of example 3 are substantially the same as those of example 1, except that the etching solution used in example 3 is different in fluoride content, wherein examples 3-1, 3-2, 3-3, 3-4, and 3-5 are labeled, respectively, according to the difference in fluoride content.
Comparative example 3
The parameters of comparative example 3 are substantially the same as those of example 1, except that the etching solution used in comparative example 3 is different in the amount of fluoride, wherein comparative examples 3A and 3B are marked, respectively, according to the difference in the amount of fluoride.
The results of the above examples and comparative examples are shown in table 3 below.
TABLE 3 Table 3
Example 4
The parameters of example 4 are substantially the same as those of example 1, except that the etching solution used in example 4 is different in the content of the chelating agent, wherein examples 4-1, 4-2, 4-3, 4-4 and 4-5 are labeled, respectively, according to the content of the chelating agent.
Comparative example 4
The parameters of comparative example 4 are substantially the same as those of example 1, except that the chelating agent content in the etching solution used in comparative example 4 is different, wherein the chelating agent content is different, and the chelating agent content is respectively labeled as comparative example 4A and comparative example 4B.
The results of the above examples and comparative examples are shown in table 4 below.
TABLE 4 Table 4
Example 5 the parameters of example 5 are substantially the same as those of example 1, except that the etching solution used in example 5 is different in the content of organic base, wherein examples 5-1, 5-2, 5-3 and 5-4 are marked as examples according to the content of organic base.
Comparative example 5
The parameters of comparative example 5 are substantially the same as those of example 1, except that the etching solution used in comparative example 5 is different in the content of organic base, wherein comparative examples 5A and 5B are marked as respectively according to the content of organic base.
The results of the above examples and comparative examples are shown in table 5 below.
TABLE 5
The etching solution provided by the application comprises 8-15 parts by weight of oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of chelating agent, 2-5 parts by weight of organic base, less than or equal to 2 parts by weight of azole compound, less than or equal to 3 parts by weight of anti-potential etching agent and 60-85 parts by weight of solvent. The etching solution provided by the application can be applied to the one-time wet etching of the metal layer 120 and the semiconductor layer 110 which are stacked by taking the patterned photoresist layer 130 as a mask, and the metal layer is reacted with the oxidant and the semiconductor layer by the synergistic effect of the components, so that the metal layer 120 and the semiconductor layer 110 which are not covered by the photoresist layer 130 are removed by the one-time wet etching, and the etching effect of the etching solution is enhanced; further, since the fluoride content is high, the reaction with the semiconductor layer is sufficient, and the problem of tailing of the semiconductor layer 110 can be improved. The etching solution provided by the application is applied to the preparation process of the array substrate of the display panel, so that the production yield of the display panel can be increased.
The foregoing is only the embodiments of the present application, and therefore, the patent scope of the application is not limited thereto, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the application.

Claims (10)

1. An etching solution, characterized in that the etching solution comprises: 8-15 parts by weight of oxidant, 0.0005-0.006 part by weight of fluoride, 3-6 parts by weight of chelating agent, 2-5 parts by weight of organic base, less than or equal to 2 parts by weight of azole compound, less than or equal to 3 parts by weight of anti-potential etching agent and 60-85 parts by weight of solvent.
2. The etching solution according to claim 1, wherein the etching solution comprises, in weight percent: 8-15wt% of oxidant, 500-6000 ppm of fluoride, 3-6wt% of chelating agent, 2-5wt% of organic base, 0-2wt% of azole compound, 0-3wt% of anti-potential etching agent and the balance of solvent.
3. The etching solution according to claim 2, wherein the weight percentage of the oxidizing agent is 14wt% or less.
4. The etching solution according to claim 2, wherein the fluoride content is 2000ppm to 6000ppm.
5. The etching solution according to any one of claims 1 to 4, wherein the etching solution has a pH of 3 to 6.
6. An etching method, characterized in that the etching method comprises the following steps:
Forming a semiconductor layer on a substrate;
Forming a metal layer on one side of the semiconductor layer away from the substrate;
Forming a patterned photoresist layer on one side of the metal layer away from the substrate; the patterned photoresist layer comprises a first sub-photoresist layer and a second sub-photoresist layer;
and carrying out one-time wet etching on the metal layer and the semiconductor layer by using the photoresist layer as a mask and adopting the etching solution as claimed in any one of claims 1-5 to remove the metal layer and the semiconductor layer which are not covered by the photoresist layer.
7. The etching method according to claim 6, wherein the semiconductor layer is an amorphous silicon layer; and/or
The metal layer comprises a single-layer metal layer made of Al, mo, cu, ti, ni or Nb, or a composite metal layer made of Mo/Al/Mo, mo/Cu/Mo or Mo/Cu; and/or
The temperature range of the one-time wet etching is 28-33 ℃; and/or
The time of the one-time wet etching is 60-160 seconds.
8. The preparation method of the array substrate is characterized by comprising the following steps of:
forming a first metal layer on a substrate; the first metal layer includes a gate line and a gate electrode;
Covering a first insulating layer on one side of the first metal layer far away from the substrate;
Forming a semiconductor layer on one side of the first insulating layer away from the substrate;
forming a second metal layer on one side of the semiconductor layer away from the substrate;
Forming a patterned photoresist layer on one side of the second metal layer away from the substrate; the patterned photoresist layer comprises a first sub-photoresist layer and a second sub-photoresist layer; the thickness of the first sub-photoresist layer is larger than that of the second sub-photoresist layer;
Performing one-time wet etching on the second metal layer and the semiconductor layer by using the etching solution as claimed in any one of claims 1 to 4 as a mask to remove the second metal layer and the semiconductor layer which are not covered by the photoresist layer, and reserving the second metal layer covered by the photoresist layer;
Removing the second metal layer covered by the second sub-photoresist layer by dry etching to form an opening, so that the semiconductor layer covered by the second sub-photoresist layer is exposed; wherein the second metal layer comprises a data line, a source electrode and a drain electrode;
And etching the exposed semiconductor layer by adopting dry etching.
9. The method for manufacturing an array substrate according to claim 8, wherein the semiconductor layer is an amorphous silicon layer; and/or
The metal layer comprises a single-layer metal layer made of Al, mo, cu, ti, ni or Nb, or a composite metal layer made of Mo/Al/Mo, mo/Cu/Mo or Mo/Cu; and/or
The temperature range of the one-time wet etching is 28-33 ℃; and/or
The time of the one-time wet etching is 60-160 seconds.
10. The method according to claim 8, wherein the dry etching is used to remove the second metal layer forming opening covered by the second sub-photoresist layer and the dry etching is used to etch the exposed semiconductor layer by the same etching machine; wherein,
In the step of removing the opening formed by the second metal layer covered by the second sub-photoresist layer by dry etching, etching gas is adopted to comprise one or more of NH3、NF3、SF6、SiCl4、Cl2、Br2、HBr、BCl3、Ar、H2、N2、CHF3、C2H4, the etching time is 120-300 seconds, and the etching power is PS (PS) 7-12k and PB (poly (p-x) 5-10k;
in the step of etching the exposed semiconductor layer by dry etching, etching gas is adopted to include one or more of SF6、NF3、BCl2、SiCl4、Cl2、Br2、HBr、BCl3、O2、Ar, etching time is 10-30 seconds, and etching power is PS 7-12k and PB 5-10k.
CN202410067272.7A 2024-01-16 2024-01-16 Etching solution, etching method and preparation method of array substrate Pending CN118085870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410067272.7A CN118085870A (en) 2024-01-16 2024-01-16 Etching solution, etching method and preparation method of array substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410067272.7A CN118085870A (en) 2024-01-16 2024-01-16 Etching solution, etching method and preparation method of array substrate

Publications (1)

Publication Number Publication Date
CN118085870A true CN118085870A (en) 2024-05-28

Family

ID=91153951

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410067272.7A Pending CN118085870A (en) 2024-01-16 2024-01-16 Etching solution, etching method and preparation method of array substrate

Country Status (1)

Country Link
CN (1) CN118085870A (en)

Similar Documents

Publication Publication Date Title
KR100505328B1 (en) ETCHING SOLUTIONS AND METHOD TO REMOVE MOLYBDENUM RESIDUE FOR Cu MOLYBDENUM MULTILAYERS
US8262928B2 (en) Etchant and method of manufacturing an array substrate using the same
US7943519B2 (en) Etchant, method for fabricating interconnection line using the etchant, and method for fabricating thin film transistor substrate using the etchant
US7008548B2 (en) Etchant for etching metal wiring layers and method for forming thin film transistor by using the same
KR101299131B1 (en) Etching composition for tft lcd
TWI598467B (en) Thin film transistor channel etching composition and method for preparing thin film transistor channel
KR101391074B1 (en) Manufacturing method of array substrate for liquid crystal display
EP2717315A1 (en) Copper-based metal wiring comprising oxide layer including indium and zinc
KR100456373B1 (en) An etchant to etching Cu or Cu/Ti metal layer
CN101684557A (en) Copper, copper/molybdenum, or copper/molybdenum alloy electrode etching solution for use in liquid crystal display system
KR20120081764A (en) Manufacturing method of an array substrate for liquid crystal display
WO2011051251A1 (en) Etching process for producing a tft matrix
KR20070055259A (en) Etching Solution of Copper Molybdenum Alloy Film and Its Etching Method
KR101391023B1 (en) Manufacturing method of array substrate for liquid crystal display
KR100459271B1 (en) Etching Solutions for Cu Monolayer or Cu Molybdenum Multilayers and Method of Preparing the Same
CN118085870A (en) Etching solution, etching method and preparation method of array substrate
KR101348046B1 (en) Fabrication method of thin film transistor, etching solution composition used the method
KR101346917B1 (en) Fabrication method of thin film transistor, etching solution composition used the method
US20090315183A1 (en) Layer-stacked wiring and semiconductor device using the same
EP4517834A1 (en) Thin film transistor device and manufacturing method therefor, compound etching solution, and array substrate
KR101236133B1 (en) A combinated etchant composition for aluminum(or aluminum alloy) layer and multilayer containing the same, molybdenum(or molybdenum alloy) layer and multilayer containing the same, and indium tin oxides layer
KR101362643B1 (en) Fabrication method of thin film transistor, etching solution composition used the method
JP4485303B2 (en) Method for manufacturing transmissive display device
KR101271349B1 (en) Fabrication method of thin film transistor, etching solution composition used the method
KR20110135841A (en) A combinated etchant composition for aluminum(or aluminum alloy) layer and multilayer containing the same, molybdenum(or molybdenum alloy) layer and multilayer containing the same, and indium tin oxides layer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination