CN118054647A

CN118054647A - Accurate ramp signal generation circuit and generation method

Info

Publication number: CN118054647A
Application number: CN202410226602.2A
Authority: CN
Inventors: 李伊珂; 李涅
Original assignee: Jingyi Semiconductor Co ltd
Current assignee: Jingyi Semiconductor Co ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-05-17
Also published as: CN117498658A; CN117498658B

Abstract

The invention provides an accurate ramp signal generating circuit and an accurate ramp signal generating method. In the ramp signal generating circuit, a first filtering module filters the node voltage signal to generate a filtered signal; the signal sampling module performs valley bottom sampling on the filtered signal to generate a sampling signal; the ramp signal generating module subtracts the filtered signal and the sampling signal to generate a ramp signal. In a switching period, receiving the filtered signal by using a fourth capacitor and keeping the valley value of the filtered signal on the fourth capacitor, and simultaneously disconnecting the fifth capacitor from the filtered signal and taking the voltage on the fifth capacitor as a sampling signal; in the next adjacent switching cycle, the fourth capacitor is disconnected from the filtered signal and the voltage on the fourth capacitor is taken as the sampling signal, while the fifth capacitor is used to receive the filtered signal and hold its valley on the fifth capacitor. By adopting the circuit and the method, the absolute valley bottom of the filtered signal can be sampled, and the transient performance of the system is effectively improved.

Description

Accurate ramp signal generation circuit and generation method

The application relates to a patent division application of 2023, 12, 29, 2023118492029 and entitled "a ramp signal generating circuit and generating method".

Technical Field

The invention relates to the technical field of switching power supplies, in particular to an accurate ramp signal generating circuit and an accurate ramp signal generating method.

Background

With the widespread use of DCDC, some other new control architectures are continuously generated, and in order to make the system have a faster corresponding speed, a current peak control mode is generally not adopted, but a direct voltage control mode is adopted. When directly controlling the voltage, a ramp signal is often required to compensate the voltage in order to ensure stability of the system. In the dual-voltage fixed frequency control circuit for a switching converter as disclosed in the patent application No. 202210692478.X, an alternating current component of a switching node voltage (voltage at a SW point) is acquired as a ramp signal, and the acquired ramp signal is input into control loops of a main switching tube and a freewheel switching tube to generate switching control signals for controlling the main switching tube and the freewheel switching tube. As shown in fig. 1, the specific circuit of the control loop inputs a voltage feedback signal Vfb and a voltage reference signal Vref representing the output voltage of the switching converter into an error amplifier EA for comparison, and amplifies the errors of the voltage feedback signal Vfb and the voltage reference signal Vref to generate an error signal Vea; the sum of the voltage feedback signal and the ramp signal, and the error signal Vea are input into the voltage comparator CA to be compared to generate a comparison signal comp, and a later-stage circuit of the control loop generates a switch control signal according to the comparison signal comp. The ramp signal generator includes a two-stage filter circuit, filters the SW point voltage to obtain a ramp signal ramp, as shown in fig. 2, and a waveform diagram is shown in fig. 3, wherein IL is a current of an output inductor in the switching converter, and a waveform of the ramp signal is in phase with a waveform of an inductor current in the switching converter.

However, as can be seen from fig. 3, at the switching point a of each cycle, a voltage difference Δv exists between the first filtered signal ramp1 and the second filtered signal ramp2, resulting in a voltage difference Δv between the actual voltage feedback signal Vfb and the voltage reference signal Vref. In applications with different input voltages, output voltages and different switching frequencies, the voltage difference Δv will also change, resulting in different output voltages and preset voltages. In the conventional solution, the difference between the output voltage and the preset voltage caused by the voltage difference Δv is often counteracted by increasing the error signal Vea. However, since the voltage difference Δv varies greatly, the error signal Vea needs a wider range, and the error amplifier EA needs a higher level, which affects the transient response of the whole system.

Disclosure of Invention

The present invention aims to solve at least one of the technical problems existing in the prior art.

Therefore, the invention provides an accurate ramp signal generating circuit which is applied to a switching converter, wherein the switching converter comprises a main switching tube, a follow current switching tube and a switching control signal, the switching control signal is used for controlling the main switching tube and the follow current switching tube, and particularly, the ramp signal generating circuit comprises a first filtering module, a signal sampling module and a ramp signal generating module. The input end of the first filtering module receives the node voltage signal and filters the node voltage signal to generate a first filtering signal at the output end of the first filtering module; the node voltage signal represents the voltage on the common node of the main and freewheel switching transistors. The signal sampling module receives the first filtering signal and performs valley bottom sampling on the first filtering signal to generate a sampling signal at the output end of the first filtering signal; the sampled signal characterizes a valley of the first filtered signal; the signal sampling module comprises a fourth capacitor and a fifth capacitor; in a switching cycle of the switching converter, the fourth capacitor is coupled with the output end of the first filtering module to receive the first filtering signal and disconnected with the output end of the signal sampling module, and the fifth capacitor is disconnected with the output end of the first filtering module and coupled with the output end of the signal sampling module to output a sampling signal; in the next adjacent switching cycle, the fourth capacitor is disconnected from the output end of the first filtering module and coupled to the output end of the signal sampling module to output a sampling signal, and the fifth capacitor is coupled to the output end of the first filtering module to receive the first filtering signal and disconnected from the output end of the signal sampling module. The ramp signal generating module receives the first filtered signal and the sampling signal, and subtracts the first filtered signal and the sampling signal to generate a ramp signal.

The invention provides a method for generating an accurate ramp signal, which is applied to a switching converter, wherein the switching converter comprises a main switching tube, a follow current switching tube and a switching control signal, the switching control signal is used for controlling the main switching tube and the follow current switching tube, and concretely, the method for generating the ramp signal comprises the following steps: filtering the node voltage signal to generate a first filtering signal, wherein the node voltage signal represents the voltage on a common node of the main switching tube and the freewheel switching tube; sampling the valley bottom voltage of the first filtering signal to generate a sampling signal; the first filtering signal is received by adopting a fourth capacitor or a fifth capacitor respectively; in one switching cycle of the switching converter, receiving the first filtered signal with the fourth capacitor and holding a valley of the first filtered signal on the fourth capacitor while disconnecting the fifth capacitor from the first filtered signal and taking a voltage on the fifth capacitor as a sampling signal, and in an adjacent next switching cycle, disconnecting the fourth capacitor from the first filtered signal and taking a voltage on the fourth capacitor as a sampling signal while receiving the first filtered signal with the fifth capacitor and holding a valley of the first filtered signal on the fifth capacitor; the first filtered signal and the sampled signal are subtracted to produce a ramp signal.

In summary, due to the adoption of the technical characteristics, the invention has the beneficial effects that: the problem of large voltage difference between the first filtering signal and the second filtering signal in the traditional slope signal generating circuit is solved by the sampling signal generated according to the valley voltage of the sampling first filtering signal and the slope signal generated by the first filtering signal. Therefore, the requirements of the control loop of the switching converter on the error amplifier are effectively reduced, and the transient performance of the system is improved. Additional aspects and advantages of the invention will be set forth in part in the description which follows, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic circuit diagram of a control loop of a main switching tube and a freewheel switching tube in a prior art switching converter;

FIG. 2 is a schematic circuit diagram of a prior art ramp signal generation circuit;

FIG. 3 is a schematic diagram showing waveforms of a first filtered signal, a second filtered signal and an inductor current in a conventional ramp signal generating circuit;

FIG. 4 is a schematic circuit diagram of a ramp signal generating circuit according to one embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of a ramp signal generating circuit according to yet another embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of a ramp signal generating circuit according to yet another embodiment of the present invention;

FIG. 7 is a schematic waveform diagram of a portion of signals in the ramp signal generating circuit according to the embodiment of FIGS. 4-6;

FIG. 8 is a schematic circuit diagram of a ramp signal generating circuit according to yet another embodiment of the present invention;

FIG. 9 is a schematic waveform diagram of a portion of signals in the ramp signal generating circuit according to the embodiment of FIG. 8;

Fig. 10 is a flowchart of a ramp signal generating method according to an embodiment of the present invention.

The correspondence between the reference numerals and the component names in fig. 1 to 8 is:

21. a voltage dividing module; 22. a first filtering module; 23. a signal sampling module; 24. a ramp signal generation module; 25. and the high-resistance state compensation module.

Detailed Description

In order that the above-recited objects, features and advantages of the present application will be more clearly understood, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description. It should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced otherwise than as described herein, and therefore the scope of the present invention is not limited to the specific embodiments disclosed below. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. The verbs "comprise" and "have" are used herein as open limits, which neither exclude nor require that there be unrecited features. Features recited in the dependent claims may be freely combined with each other unless explicitly stated otherwise. The use of an element defined as "one" or "one" (i.e., in the singular) throughout this document does not exclude the possibility of a plurality of such elements. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Unless otherwise indicated, the terms "connected" or "coupled" are used to designate electrical connections between circuit elements that may be direct or may be via one or more other elements. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. When referring to the voltage of a node or terminal, unless indicated otherwise, the voltage is considered to be the voltage between that node and a reference potential (typically ground).

Ramp signal generation circuits and methods provided according to some embodiments of the present invention are described below with reference to fig. 4 to 10. It should be noted that, in the present disclosure, fig. 3, fig. 7, and fig. 9 are waveforms for showing a change of each signal with time, and are used to show a phase relationship between signals, that is, an abscissa thereof is time, and units are seconds(s), and each signal shown in the figures has a corresponding description in the present disclosure, so that there is no misunderstanding.

Fig. 4 provides a circuit schematic of a ramp signal generating circuit according to some embodiments of the present invention.

As shown in fig. 4, the ramp signal generating circuit includes: a first filtering module 22, a signal sampling module 23 and a ramp signal generating module 24. Wherein, the first filtering module 22 performs a first filtering on the node voltage signal Vsw; the signal sampling module 23 receives the first filtered signal ramp1, and performs valley-down sampling on the first filtered signal ramp1 to generate a sampling signal sva; the ramp signal generating module 24 receives the first filtered signal ramp1 and the sampling signal sva, and subtracts the first filtered signal ramp1 and the sampling signal sva to generate a ramp signal ramp.

In one embodiment, the ramp signal generating circuit further includes a voltage dividing module 21, and the node voltage signal Vsw is divided by the voltage dividing module 21 to generate the divided voltage signal VD; the first filtering module 22 filters the split signal VD. Specifically, the voltage dividing module 21 includes a resistor Ra and a resistor Rb, one end of the resistor Ra is coupled to a common node of the main switching tube and the freewheeling switching tube, receives the node voltage signal Vsw, the other end of the resistor Ra is coupled to one end of the resistor Rb, and the other end of the resistor Rb is coupled to the reference ground, wherein the voltage dividing module 21 generates the voltage dividing signal VD at the common end of the resistor Ra and the resistor Rb. It will be appreciated that other voltage dividing means may be used for the voltage dividing module 21. Also, in some embodiments, the voltage dividing module 21 may be omitted according to practical applications.

In the embodiment shown in fig. 4, the first filtering module 22 is illustrated as an RC filter. The first filter module 22 includes a first resistor R1 and a first capacitor C1, wherein a first end of the first resistor R1 is coupled to the voltage dividing module 21, receives the voltage dividing signal VD, a second end of the first resistor R1 is coupled to a first end of the first capacitor C1, and a second end of the first capacitor C1 is coupled to the reference ground. It is understood that other filtering structures can be adopted for the first filtering module 22, so long as filtering the node voltage signal Vsw to generate the first filtered signal ramp1 can be implemented.

With continued reference to fig. 4, the signal sampling module 23 includes a single pulse generator, a first electronic switch M1, a second resistor R2, and a second capacitor C2. The single pulse generator has an input and an output, the input of the single pulse generator receives the switching control signal, and the single pulse generator generates the narrow pulse signal Hs-pls at the active edge time of the switching control signal. The active edge of the switch control signal may include a rising edge or a falling edge, and may be selected according to a specific embodiment, where the active edge corresponds to the valley time of the first filtered signal ramp 1. Specifically, the switch control signals comprise a main switch tube control signal Hs-on and a freewheel switch tube control signal Ls-on, wherein the main switch tube control signal Hs-on and the freewheel switch tube control signal Ls-on are respectively used for controlling the on-off of a main switch tube and a freewheel switch tube, and the freewheel switch tube control signal Ls-on is an inversion signal of the main switch tube control signal Hs-on. The minimum value of the first filter signal ramp1 may be reached at the rising edge of the main switching tube control signal Hs-on or at the falling edge of the freewheel switching tube control signal Ls-on, so that the first filter signal ramp1 may be valley sampled at the rising edge of the main switching tube control signal Hs-on or at the falling edge of the freewheel switching tube control signal Ls-on.

The first electronic switch M1 has a first end, a second end and a control end, the first end of the first electronic switch M1 is coupled to the first end of the first capacitor C1, receives the first filter signal ramp1, and the control end of the first electronic switch M1 is coupled to the output end of the single pulse generator, and receives the narrow pulse signal Hs-pls. The second resistor R2 has a first end and a second end, and the first end of the second resistor R2 is coupled to the second end of the first electronic switch M1; the second capacitor C2 has a first end and a second end, the first end of the second capacitor C2 is coupled to the second end of the second resistor R2, and the second end of the second capacitor C2 is connected to the ground, wherein the first end of the second capacitor C2 outputs the sampling signal sva.

In fig. 4, the ramp signal generating module 24 is illustrated as a subtractor, the positive input end of which receives the first filtered signal ramp1, the negative input end of which receives the sampling signal sva, and the ramp signal ramp is generated by subtracting the first filtered signal ramp1 and the sampling signal sva in the subtractor. In other embodiments, the Ramp signal generating module 24 may also be other suitable components in the control loop of the power system, such as a comparator, in which the non-inverting input terminal of the comparator receives the first filtered signal Ramp1 (or the sampling signal sva) and the inverting input terminal receives the sampling signal sva (or the first filtered signal Ramp 1), so that the Ramp signal Ramp is directly introduced into the comparator.

In a specific embodiment, the input end of the single pulse generator receives the main switch control signal Hs-on, and when the main switch is turned on, that is, at the rising edge time of the main switch control signal Hs-on, the single pulse generator generates a narrow pulse, so as to form a narrow pulse signal Hs-pls, and the first electronic switch M1 is controlled to be turned on and off by using the narrow pulse signal Hs-pls. Specifically, when the narrow pulse signal Hs-pls is logic high, the first electronic switch M1 is turned on, so that the valley voltage of the first filtered signal ramp1 is sampled, that is, the second capacitor C2 is charged by the valley voltage of the first filtered signal ramp1, and when the narrow pulse signal Hs-pls is turned to logic low, the first electronic switch M1 is turned off. Over a number of cycles, the second capacitor C2 completes charging, thereby generating a sampling signal sva that is substantially equal to the valley voltage of the first filtered signal ramp 1.

Fig. 5 is a circuit schematic of a ramp signal generating circuit according to still another embodiment of the present invention. As shown in fig. 5, the signal sampling module 23 includes: the device comprises a first electronic switch M1, a single pulse generator, a charging capacitor C3, a second electronic switch M2 and a second capacitor C2. The first end of the first electronic switch M1 is coupled to the output end of the first filtering module 22, the first end of the first electronic switch M1 and the first end of the second electronic switch M2 are connected in parallel to the first end of the charging capacitor C3, the second end of the charging capacitor C3 is coupled to the reference ground, the second end of the second electronic switch M2 outputs the sampling signal sva, the first end of the second capacitor C2 is coupled to the second end of the second electronic switch M2, and the second end of the second capacitor C2 is connected to the reference ground. The input end of the single pulse generator receives a main switching tube control signal Hs-on, generates a narrow pulse on the rising edge of the main switching tube control signal Hs-on to form a narrow pulse signal Hs-pls, and inputs the narrow pulse signal Hs-pls to the control end of the first electronic switch M1 to control the on-off of the first electronic switch M1; the control end of the second electronic switch M2 receives the inverted signal of the narrow pulse signal Hs-pls, so that the on-off states of the first electronic switch M1 and the second electronic switch M2 are opposite. Specifically, at the rising edge of the main switching tube control signal Hs-on, the first electronic switch M1 is turned on by the narrow pulse signal Hs-pls, the second electronic switch M2 is turned off by the inverted signal of the narrow pulse signal Hs-pls, when the main switching tube control signal Hs-on is turned low, the first electronic switch M1 is turned off by the narrow pulse signal Hs-pls, and the second electronic switch M2 is turned on by the inverted signal of the narrow pulse signal Hs-pls. In this embodiment, the second resistor R2 in the embodiment of fig. 4 may be omitted, and the bottom sampling of the first filtered signal ramp1 may be implemented as well.

In one embodiment, the capacitance of the charging capacitor C3 is much smaller than the capacitance of the second capacitor C2. In one embodiment, the capacitance of the second capacitor C2 is twenty to thirty times the capacitance of the charging capacitor C3.

In some embodiments, the method of obtaining the inverted signal of the narrow pulse signal Hs-pls may be to obtain the inverted signal of the narrow pulse signal Hs-pls by using an inverter, specifically, an input terminal of the inverter is coupled to an output terminal of the single pulse generator, and an output terminal of the inverter is coupled to a control terminal of the second electronic switch M2.

In some embodiments, a resistor may also be connected in series between the first electronic switch M1 and the charging capacitor C3 to flexibly adjust the time constant of the signal sampling module.

In the above embodiments, in some operating conditions, when the switching converter is in a light load condition, the rising edge of the main switching tube control signal Hs-on is not always right, so that the first electronic switch M1 cannot be turned on, which will affect the ramp signal ramp. To solve the above-described problem, fig. 6 shows a schematic diagram of a ramp signal generating circuit provided in another embodiment of the present disclosure. In the circuit diagram shown in fig. 6, the ramp signal generating circuit is provided with a high-impedance compensation module 25 in addition to the first filtering module 22, the signal sampling module 23, and the ramp signal generating module 24. The high-resistance compensation module 25 includes a third resistor R3, and when the off-time of the first electronic switch M1 exceeds a preset time, the high-resistance compensation module 25 is configured to couple the output end of the first filter module 22, i.e. the first end of the first capacitor C1 and the first end of the second capacitor C2, through the third resistor R3. The high-resistance state compensation module 25 receives the main switching tube control signal Hs-on and the freewheel switching tube control signal Ls-on, and generates a state identification signal SIG, where the effective state of the state identification signal SIG is used to characterize that both the main switching tube and the freewheel switching tube are turned off; in one embodiment, the active state of SIG is that the main switch tube control signal Hs-on and the freewheel switch tube control signal Ls-on are in the same logic state, e.g., logic low.

Specifically, when the main switch tube control signal Hs-on and the freewheel switch tube control signal Ls-on are both low, the first electronic switch M1 is not turned on for a long time, the state identification signal SIG turns high, and the high-resistance state compensation module 25 counts the logic high state of the state identification signal SIG at the same time, and when the preset time period is exceeded, the first end of the first capacitor C1 and the first end of the second capacitor C2 are coupled through the third resistor R3, and the second capacitor C2 is charged.

In some embodiments, the high impedance compensation module 25 further includes a logic determination unit, a delay unit, and a third electronic switch M3.

The logic judging unit receives the main switching tube control signal Hs-on and the freewheel switching tube control signal Ls-on, and performs logic operation on the main switching tube control signal Hs-on and the freewheel switching tube control signal Ls-on to generate a state identification signal SIG. Specifically, under the constraint of the logic determination unit, the state identification signal SIG toggles high only when the main switching tube control signal Hs-on and the freewheel switching tube control signal Ls-on are simultaneously low. In a specific embodiment, the logic determination unit is schematically represented as a nor gate, and two input terminals of the nor gate respectively receive the main switching tube control signal Hs-on and the freewheel switching tube control signal Ls-on, and an output terminal of the nor gate outputs the state identification signal SIG.

The delay unit receives the state identification signal SIG, delays the state identification signal SIG for a preset time period, and outputs a delay signal, where the delay signal is used to turn on the third electronic switch M3, that is, when the turn-off time of the first electronic switch is greater than or equal to the preset time period, the third electronic switch M3 is turned on.

The first end of the third electronic switch M3 is coupled to the output end of the first filtering module 22, receives the first filtering signal ramp1, the second end of the third electronic switch M3 is coupled to the first end of the third resistor R3, the control end of the third electronic switch M3 is coupled to the output end of the delay unit, receives the delay signal, and the second end of the third resistor R3 is coupled to the first end of the second capacitor C2. The resistance of the third resistor R3 is greater than the resistance of the second resistor R2, for example, in a specific embodiment, the resistance of the third resistor R3 is 2mΩ, and the resistance of the second resistor R2 is 0.1mΩ. It will be appreciated that in the embodiment shown in fig. 6, the signal sampling module 23 is illustrated as the same circuit as the signal sampling module 23 in fig. 4, and in other embodiments, the signal sampling module 23 may also be the circuit structure of the signal sampling module 23 illustrated in fig. 5.

Any of the electronic switches of the present application may be any suitable controllable switching device, such as metal-semiconductor Field effect transistors (Metal Oxide Semiconductor FIELD EFFECT transistors, MOSFETs), junction Field-effect Transistor (JFETs), insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs), and double diffused metal oxide semiconductors (Double Diffusion Metal Oxide Semiconductor, DMOS), among others.

Fig. 7 is a waveform diagram of a part of signals in the ramp signal generating circuit according to the embodiment of fig. 4 and 5. Waveforms of the main switching tube control signal Hs-on, the narrow pulse signal Hs-pls, the inductor current IL, the first filter signal ramp1 and the sampling signal sva are illustrated in order from top to bottom. As can be seen from the figure, at the switching point a where the main switching transistor is turned on, the voltage difference Δv between the first filtered signal ramp1 and the sampling signal sva is significantly smaller than the voltage difference between the first filtered signal ramp1 and the second filtered signal ramp2 in the conventional ramp signal generating circuit shown in fig. 3. It is understood that the smaller the pulse width of the narrow pulse signal Hs-pls is, the smaller the voltage difference between the valley of the first filtered signal ramp1 and the sampling signal sva is.

Although the above embodiment greatly reduces the voltage difference Δv between the first filtered signal ramp1 and the sampling signal sva by performing the valley-bottom sampling on the first filtered signal ramp1 to generate the sampling signal sva, the finally obtained sampling signal sva is not the absolute valley-bottom voltage of the first filtered signal ramp1 because the narrow pulse signal Hs-pls still has a certain pulse width, so as to improve the accuracy of the valley-bottom value acquisition, the embodiment of fig. 8 is further disclosed in the present invention.

As shown in fig. 8, in this embodiment, the signal sampling module 23 includes a fourth electronic switch M4, a fifth electronic switch M5, a sixth electronic switch M6, a seventh electronic switch M7, a fourth capacitor C4, and a fifth capacitor C5.

The fourth electronic switch M4 has a first end, a second end and a control end, the first end of the fourth electronic switch M4 receives the first filtering signal ramp1, the control end of the fourth electronic switch M4 receives the switching period signal TS1, wherein the period of the switching period signal TS1 is equal to twice the switching period of the switching converter, and the duty cycle of the switching period signal TS1 is 50%. The fourth capacitor C4 has a first end and a second end, the first end of the fourth capacitor C4 is coupled to the second end of the fourth electronic switch M4, and the second end of the fourth capacitor C4 is coupled to the reference ground. The fifth electronic switch M5 has a first end, a second end and a control end, the first end of the fifth electronic switch M5 is coupled to the first end of the fourth capacitor C4, the control end of the fifth electronic switch M5 receives the inverted signal TS2 of the switching period signal TS1, and the second end of the fifth electronic switch M5 outputs the sampling signal sva. The sixth electronic switch M6 has a first end, a second end and a control end, the first end of the sixth electronic switch M6 receives the first filtered signal ramp1, and the control end of the sixth electronic switch M6 receives the inverted signal TS2 of the switching period signal TS 1. A fifth capacitor C5 having a first end and a second end, the first end of the fifth capacitor C5 being coupled to the second end of the sixth electronic switch M6, the second end of the fifth capacitor C5 being coupled to the reference ground. The seventh electronic switch M7 has a first end, a second end and a control end, the first end of the seventh electronic switch M7 is coupled to the first end of the fifth capacitor C5, the control end of the seventh electronic switch M7 receives the switching period signal TS1, and the second end of the seventh electronic switch M7 is coupled to the second end of the fifth electronic switch M5.

In the embodiment shown in fig. 8, the signal sampling module 23 is schematically further comprised of a periodic signal generating circuit for generating the switching periodic signal TS1 and its inverse TS2. In one embodiment, the switching period signal TS1 and its inverse TS2 may be generated by a main switching tube control signal Hs-on. Since the switching period signal TS1 is set to be twice the switching period of the switching converter, i.e. twice the period of the main switching tube control signal Hs-on or the freewheel switching tube control signal, the duty cycle of the switching period signal TS1 is 50%. That is, in the switching cycles of two consecutive switching converters, the switching cycle signal TS1 is active (e.g., logic high) in the first switching cycle, and the inverted signal TS2 of the switching cycle signal TS1 is active (e.g., logic high) in the second switching cycle.

In the embodiment shown in fig. 8, the signal sampling module 23 operates according to the following principle: in the first switching period, the fourth electronic switch M4 and the seventh electronic switch M7 are turned on; in the second switching period, the fifth electronic switch M5 and the sixth electronic switch M6 are turned on. When the fourth electronic switch M4 and the seventh electronic switch M7 are turned on, the voltage on the fifth capacitor C5 is the sampling signal sva; when the fifth electronic switch M5 and the sixth electronic switch M6 are turned on, the voltage on the fourth capacitor C4 is the sampling signal sva. Since the switching points of the fourth electronic switch M4 and the fifth electronic switch M5 and the switching points of the sixth electronic switch M6 and the seventh electronic switch M7 are at the start/end time of each period, the voltages on the fourth capacitor C4 and the fifth capacitor C5 are all the valley value of the first filtering signal ramp1 at this moment. Therefore, the absolute valley bottom of the first filtering signal ramp1 can be sampled, so that the influence of the voltage difference DeltaV can be completely eliminated, and the transient response of the whole system is further improved.

Fig. 9 is a waveform diagram of a part of signals in the ramp signal generating circuit according to the embodiment of fig. 8. Waveforms of the switching period signal TS1, the inverted signal TS2 of the switching period signal TS1, the inductor current IL, the first filtered signal ramp1, and the sampling signal sva are illustrated in order from top to bottom. As can be seen from the figure, at the switching point a where the main switching tube is turned on, the value of the first filter signal ramp1 is equal to the value of the sampling signal sva.

Still further embodiments of the present invention provide a ramp signal generating method applied to a switching converter including a main switching tube, a freewheel switching tube, and a switching control signal for controlling the main switching tube and the freewheel switching tube, and in particular, as shown in fig. 10, the method includes steps S1 to S3.

S1: the node voltage signal Vsw is filtered to generate a first filtered signal ramp1, wherein the node voltage signal Vsw represents a voltage on a common node of the main switching transistor and the freewheel switching transistor.

S2: the valley voltage of the first filtered signal ramp1 is sampled to generate a sampled signal sva. Wherein the sampled signal sva characterizes a valley of the first filtered signal. In one embodiment, during one switching cycle of the switching converter, a fourth capacitor (C4 as shown in fig. 8) is used to receive the first filtered signal ramp1 and hold the valley of the first filtered signal ramp1 on the fourth capacitor while a fifth capacitor (C5 as shown in fig. 8) is disconnected from the first filtered signal ramp1 and the voltage on the fifth capacitor is taken as the sampling signal sva; in the next adjacent switching cycle, the fourth capacitor is disconnected from the first filtered signal ramp1 and the voltage on the fourth capacitor is used as the sampling signal sva, while the fifth capacitor is used to receive the first filtered signal ramp1 and the valley of the first filtered signal ramp1 is maintained on the fifth capacitor.

In particular, as illustrated in the embodiment shown in fig. 8, the fourth capacitor C4 may receive the first filtered signal ramp1 through the fourth electronic switch M4 and output the sampling signal sva through the fifth electronic switch M5; the fifth capacitor C5 receives the first filtered signal ramp1 through the sixth electronic switch M6 and outputs the sampling signal sva through the seventh electronic switch M7. It will be appreciated that the four switches M4, M5, M6 and M7 are only illustrative and not limiting to the method, and that the fourth capacitor C4 and the fifth capacitor C5 may receive and mask the first filtered signal ramp1 in other forms and output the sampling signal sva at intervals.

In one embodiment, in step S2, the switching period signal and the inverted signal of the switching period signal are generated by the switching control signal, wherein the period of the switching period signal is equal to twice the period of the switching control signal, and the duty cycle of the switching period signal is 50%. The switch period signal is used for controlling the fourth electronic switch M4 and the seventh electronic switch M7 to be synchronously turned on and turned off; the inverse signal of the switching period signal is used for controlling the fifth electronic switch M5 and the sixth electronic switch M6 to be synchronously turned on and turned off.

For example, in the embodiment shown in fig. 8, the sampling period signal generating circuit generates the switching period signal TS1 and the inverted signal TS2 of the switching period signal, wherein the period signal generating circuit generates TS1 and TS2 based on the main switching tube control signal Hs-on in the switching control signal.

S3: the first filtered signal ramp1 and the sampling signal sva are subtracted to generate a ramp signal ramp.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An accurate ramp signal generating circuit for a switching converter, the switching converter comprising a main switching tube, a freewheel switching tube and a switch control signal for controlling the main switching tube and the freewheel switching tube, the ramp signal generating circuit comprising:

The input end of the first filtering module receives the node voltage signal and filters the node voltage signal to generate a first filtering signal at the output end of the first filtering module; wherein the node voltage signal represents the voltage on the common node of the main switching tube and the freewheel switching tube;

The signal sampling module is used for receiving the first filtering signal and carrying out valley-bottom sampling on the first filtering signal so as to generate a sampling signal at the output end of the first filtering signal, wherein the sampling signal represents the valley value of the first filtering signal; the signal sampling module comprises a fourth capacitor and a fifth capacitor; in a switching period of the switching converter, the fourth capacitor is coupled with the output end of the first filtering module to receive the first filtering signal and disconnected with the output end of the signal sampling module, and the fifth capacitor is disconnected with the output end of the first filtering module and coupled with the output end of the signal sampling module to output the sampling signal; in the next adjacent switching period, the fourth capacitor is disconnected from the output end of the first filtering module and coupled with the output end of the signal sampling module to output the sampling signal, and the fifth capacitor is coupled with the output end of the first filtering module to receive the first filtering signal and disconnected from the output end of the signal sampling module; and

And the ramp signal generating module is used for receiving the first filtering signal and the sampling signal and generating a ramp signal by subtracting the first filtering signal from the sampling signal.

2. The ramp signal generating circuit according to claim 1, wherein said sampling module further comprises:

The fourth electronic switch is coupled between the output end of the first filtering module and the first end of the fourth capacitor;

the fifth electronic switch is coupled between the first end of the fourth capacitor and the output end of the signal sampling module, and the second end of the fourth capacitor is connected to the reference ground;

the sixth electronic switch is coupled between the output end of the first filtering module and the first end of the fifth capacitor;

the seventh electronic switch is coupled between the first end of the fifth capacitor and the output end of the signal sampling module, and the second end of the fifth capacitor is connected to the reference ground;

In a first switching cycle of the switching converter, the fourth electronic switch and the seventh electronic switch are turned on, and the fifth electronic switch and the sixth electronic switch are turned off; in an adjacent second switching cycle, the fourth and seventh electronic switches are turned off and the fifth and sixth electronic switches are turned on.

3. The ramp signal generating circuit according to claim 2, wherein,

The fourth electronic switch, the fifth electronic switch, the sixth electronic switch and the seventh electronic switch all comprise control ends; the control ends of the fourth electronic switch and the seventh electronic switch receive a switch period signal; the control ends of the fifth electronic switch and the sixth electronic switch receive the inverted signals of the switch periodic signals; the period of the switching period signal is equal to twice the period of the switching control signal, and the duty ratio of the switching period signal is 50%.

4. The ramp signal generating circuit according to claim 3, wherein said signal sampling module further comprises:

And the periodic signal generating circuit is used for receiving the switch control signal and generating the switch periodic signal and an inverted signal of the switch periodic signal according to the switch control signal.

5. The ramp signal generating circuit according to claim 1, further comprising:

the voltage division module receives the node voltage signal and divides the node voltage signal to generate a divided voltage signal;

the first filter module comprises a first resistor and a first capacitor, one end of the first resistor is coupled with the voltage dividing module and receives a voltage dividing signal, the other end of the first resistor is coupled with one end of the first capacitor, and the other end of the first capacitor is coupled to the reference ground.

6. The ramp signal generating circuit according to claim 1, wherein the ramp signal generating module comprises a comparator having a non-inverting input receiving one of the first filtered signal and the sampled signal and an inverting input receiving the remaining one of the first filtered signal and the sampled signal.

7. An accurate ramp signal generation method applied to a switching converter, the switching converter including a main switching tube, a freewheel switching tube, and a switch control signal for controlling the main switching tube and the freewheel switching tube, the ramp signal generation method comprising:

filtering a node voltage signal to generate a first filtering signal, wherein the node voltage signal represents the voltage on a common node of a main switching tube and a freewheeling switching tube;

Sampling the valley bottom voltage of the first filtering signal to generate a sampling signal; the first filtering signal is received by adopting a fourth capacitor or a fifth capacitor respectively; in a first switching period of the switching converter, a fourth capacitor is adopted to receive a first filtering signal, the valley value of the first filtering signal is kept on the fourth capacitor, meanwhile, a fifth capacitor is disconnected from the first filtering signal, and the voltage on the fifth capacitor is used as the sampling signal; disconnecting the fourth capacitor from the first filtered signal in the next adjacent switching cycle, taking the voltage on the fourth capacitor as the sampling signal, receiving the first filtered signal by adopting the fifth capacitor, and keeping the valley value of the first filtered signal on the fifth capacitor;

the first filtered signal and the sampled signal are subtracted to produce a ramp signal.

8. The ramp signal generating method according to claim 7, wherein,

The fourth capacitor receives the first filtering signal through a fourth electronic switch and outputs a sampling signal through a fifth electronic switch;

the fifth capacitor receives the first filtered signal through the sixth electronic switch and outputs a sampling signal through the seventh electronic switch.

9. The ramp signal generating method according to claim 8, wherein the step of sampling the valley voltage of the first filtered signal to generate the sampled signal further comprises:

Generating a switching period signal and an inverted signal of the switching period signal by a switching control signal, wherein the period of the switching period signal is equal to twice the period of the switching control signal, and the duty ratio of the switching period signal is 50%; wherein,

The switch periodic signal is used for controlling the fourth electronic switch and the seventh electronic switch to be synchronously turned on and turned off; and the inverse signal of the switch periodic signal is used for controlling the fifth electronic switch and the sixth electronic switch to be synchronously turned on and off.

10. The ramp signal generating method according to claim 7, wherein the step of subtracting the first filtered signal and the sampling signal to generate the ramp signal comprises: the first filtered signal and the sampled signal are fed to the non-inverting input and the inverting input of the comparator, respectively.