CN118016684A - Semiconductor structure and preparation method thereof, wafer cutting method - Google Patents

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a wafer cutting method. The method provided by the invention is characterized in that at least two deep trenches are arranged between the protection ring of each chip and the corresponding cutting channel, and one deep trench is close to the outer side edge of the protection ring and is arranged along the periphery of the protection ring. Based on the above, the deep trench arranged near the outer side edge of the protection ring is used as a safety barrier of the chip, so that the wafer cutting stress diffusion is effectively blocked. And the deep groove far away from the protection ring is used for buffering stress in the stress diffusion process and weakening stress energy, so that multiple barriers to stress diffusion are realized, and the device yield is effectively improved. Compared with the prior art, the method provided by the invention has the advantages that the stress blocking effect can be improved, the opening size of the deep groove can be reduced, the space proportion of the deep groove occupying the buffer area is reduced, the size of the buffer area can be reduced, the occupancy rate of chips on a wafer is improved, and the device preparation cost is reduced.

Description

Semiconductor structure and preparation method thereof, wafer cutting method

Technical Field

The present invention relates to the technical field of semiconductor preparation, and in particular to a semiconductor structure and a preparation method thereof, and a wafer cutting method.

Background technique

Stacked CMOS Image Sensor (Stacked CIS) is an improved structure based on the back-illuminated CMOS image sensor. It divides the logic circuit and pixel area on two wafers and uses stacking technology to connect them, thereby further improving the photosensitivity and readout speed of the image sensor and reducing the horizontal size of the sensor, which meets the development needs of ultra-large-scale integration technology.

Please refer to FIG. 1. In the existing Stacked CIS preparation process, multiple image sensor chips are formed simultaneously on the same wafer 10, and a protective ring (SealingRing) 101 is set around the device area 100 of each image sensor chip to prevent the device area 100 from being disturbed or physically damaged by the external environment. In addition, there is a cutting path 102 between adjacent image sensor chips, and part or all of the wafer 10 is cut along the cutting path 102 by mechanical contact diamond wheel cutting or laser invisible cutting, and after film expansion and splitting, multiple independent image sensor chips are formed. However, as shown in FIG. 2, since the photosensitive surface of the Stacked CIS is located on the back of the pixel wafer after flipping, it will first contact the single crystal silicon layer 103 on the surface of the pixel wafer during cutting. And the single crystal silicon material has the characteristics of high hardness and low toughness, and it is very easy to crack or break under the action of external force, which seriously affects the yield of the cut device. Therefore, in order to alleviate the adverse effects caused by stress intrusion during the cutting process of the wafer 10, the existing process sets a buffer area 104 between the protective ring 101 and the cutting path 102 to alleviate the impact of stress intrusion on the image sensor chip. In addition, a deep groove 105 is also set on the upper surface of the protective ring 101 to further alleviate the stress intrusion problem and improve the device yield. However, in order to effectively alleviate the influence of stress, in the actual process, the area of the buffer area 104 and the size of the deep groove 105 need to reach a larger range to prevent a certain amount of stress intrusion. Therefore, the existing method of alleviating stress intrusion not only has a limited buffering effect, but also restricts the effective use area of the wafer, affects the yield of the wafer, and increases the preparation cost.

Therefore, a new process method for alleviating stress intrusion is urgently needed to improve device yield and reduce costs.

Summary of the invention

The object of the present invention is to provide a semiconductor structure and a preparation method thereof, and a wafer cutting method, so as to at least solve the problem of how to alleviate the influence of stress intrusion on device yield during wafer cutting.

In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor structure, comprising:

A wafer is provided, on which a plurality of chips are formed, wherein the chip at least comprises a device region and a protection ring surrounding the device region, and a dicing path is provided between adjacent chips;

At least two deep grooves are arranged between the protection ring of each chip and the corresponding dicing road, and one of the deep grooves is close to the outer edge of the protection ring and arranged along the outer periphery of the protection ring.

Optionally, in the method for preparing the semiconductor structure, a buffer zone is further provided between the cutting path and the guard ring, and the deep groove away from the outer edge of the guard ring is provided in the buffer zone.

Optionally, in the method for preparing the semiconductor structure, the deep trench is ring-shaped, and the morphology of the deep trench is compatible with the morphology of the guard ring.

Optionally, in the method for preparing the semiconductor structure, the at least two deep trenches are nested in sequence and arranged around the periphery of the guard ring.

Optionally, in the method for preparing the semiconductor structure, the at least two deep trenches are arranged at intervals, and the horizontal spacing between each part of the deep trench and each part corresponding to the guard ring is equal.

Optionally, in the method for preparing the semiconductor structure, the opening sizes of the deep trenches are the same, or the opening sizes of some of the deep trenches are different.

Optionally, in the method for preparing the semiconductor structure, the process of forming the deep trench includes:

forming a hard mask layer, wherein the hard mask layer covers the chip, the dicing road, and an area between the chip and the dicing road;

forming a patterned photoresist layer, wherein the patterned photoresist layer covers the hard mask layer;

Using the patterned photoresist layer as a barrier, etching the hard mask layer and exposing a portion of the area between the guard ring and the cutting path;

removing the patterned photoresist layer;

The hard mask layer is used as a barrier to etch the partial area between the protection ring and the cutting path to form the at least two deep trenches.

Optionally, in the method for preparing the semiconductor structure, after forming the at least two deep trenches, the hard mask layer is removed and the semiconductor structure is cleaned.

Based on the same inventive concept, the present invention also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method as described above.

Based on the same inventive concept, the present invention also provides a wafer cutting method, comprising:

forming the semiconductor structure;

The semiconductor structure is cut along the cutting paths to separate a plurality of chips.

In summary, the present invention provides a semiconductor structure and a method for preparing the same, as well as a wafer cutting method. Compared with the prior art, the method provided by the present invention sets at least two deep grooves between the protection ring of each chip and the corresponding cutting path, and one of the deep grooves is close to the outer edge of the protection ring of the chip and is set along the outer periphery of the protection ring. Based on this, the deep grooves set close to the outer edge of the protection ring are used as a safety barrier for the device area of the chip to effectively block the diffusion of wafer cutting stress. The deep grooves away from the protection ring are used to buffer stress during the stress diffusion process and weaken stress energy, thereby achieving multi-channel blocking of stress diffusion and effectively improving device yield. Moreover, compared with the prior art of forming a deep groove with a larger opening on the protection ring, the method provided by the present invention can not only improve the stress blocking effect, but also reduce the opening size of the deep groove, reduce the spatial proportion of the deep groove occupying the buffer area, and also help to reduce the size of the buffer area, improve the effective occupancy rate of the chip on the wafer, and reduce the device preparation cost.

BRIEF DESCRIPTION OF THE DRAWINGS

Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

FIG. 1 is a schematic diagram of the structure of a wafer and a chip in the prior art.

Fig. 2 is a schematic cross-sectional view of A-A' in Fig. 1 in the prior art.

FIG. 3 is a flow chart of a method for preparing a semiconductor structure according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of the structure of a wafer and a chip in an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view of B-B' in Fig. 4 in an embodiment of the present invention.

FIG. 6 is a schematic diagram of the position of the deep trench in an embodiment of the present invention.

Fig. 7 is a schematic diagram of the C-C' section in Fig. 6 in an embodiment of the present invention.

FIG. 8 is a schematic structural diagram of a hard mask layer and a patterned photoresist layer in an embodiment of the present invention.

FIG. 9 is a schematic diagram of the structure of etching a hard mask layer in an embodiment of the present invention.

FIG. 10 is a schematic diagram of the structure of etching a single crystal silicon layer in an embodiment of the present invention.

FIG. 11 is a schematic diagram of a structure in which deep trenches are evenly distributed relative to a guard ring in an embodiment of the present invention.

FIG. 12 is a schematic diagram of the structure of two deep trenches with different opening sizes in an embodiment of the present invention.

And, in the attached drawings:

10-wafer; 100-device area; 101-guard ring; 102-cutting road; 103-single crystal silicon layer; 104-buffer zone; 105-deep trench;

200 - wafer; 201 - device area; 202 - guard ring; 203 - cutting road; 204 - buffer zone; 205 - deep trench; 206 - single crystal silicon layer; 207 - hard mask layer; 208 - patterned photoresist layer.

Detailed ways

In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is usually used to include the meaning of "and/or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element is arranged on another element, which usually only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements can be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element can be in any orientation such as inside, outside, above, below or one side of another element, unless the content clearly indicates otherwise. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the X-axis direction, Y-axis direction and Z-axis direction referred to in the specification and drawings of this application are three directions perpendicular to each other in three-dimensional space, and the vertical direction refers to the Z-axis direction, and the horizontal direction refers to the direction of the X-Y plane.

Referring to FIG. 3 , this embodiment provides a method for preparing a semiconductor structure, including:

Step 1 S10: providing a wafer, on which a plurality of chips are formed, wherein the chip at least includes a device region and a protection ring surrounding the device region, and there are dicing lanes between adjacent chips;

Step 2 S20: at least two deep grooves are arranged between the guard ring of each chip and the corresponding dicing street, and one of the deep grooves is close to the outer edge of the guard ring and arranged along the outer periphery of the guard ring.

Based on this, the preparation method of the semiconductor structure provided in this embodiment is provided with at least two deep grooves, and the deep grooves provided near the outer edge of the protection ring of the chip are used as a safety barrier for the device area to achieve effective blocking of the diffusion of wafer cutting stress. The deep grooves far away from the protection ring are used to buffer stress during the stress diffusion process and weaken stress energy, thereby achieving multi-channel blocking of stress diffusion and effectively improving the device yield. Compared with the prior art of forming a deep groove with a larger opening on the protection ring, the method provided in this embodiment can not only improve the stress blocking effect, but also reduce the opening size of the deep groove, reduce the spatial proportion of the deep groove occupied by the buffer area, and also help to reduce the size of the buffer area, improve the effective occupancy rate of the chip on the wafer, and reduce the device preparation cost.

The method for preparing the semiconductor structure provided in this embodiment is described in detail below with reference to FIGS. 3 to 12 .

Specifically, the method for preparing the semiconductor structure includes:

Step 1 S10: Referring to FIG. 4 and FIG. 5 , a wafer 200 is provided. A plurality of chips are formed on the wafer 200 . The chip at least includes a device region 201 and a protection ring 202 surrounding the device region 201 , and a cutting path 203 is provided between adjacent chips.

It should be noted that the wafer 200 referred to in this embodiment is any substrate for carrying semiconductor integrated circuit components that is well known to those skilled in the art. For example: gallium nitride film, silicon-on-insulator (SOI) substrate, bulk silicon substrate, germanium substrate, germanium silicon substrate, indium phosphide (InP) substrate, gallium arsenide (GaAs) substrate or germanium-on-insulator substrate, etc. The chip is a circuit structure integrated with semiconductor components. Among them, this embodiment does not specifically limit the model of the wafer 200 and the chip. Exemplarily, the wafer 200 is a silicon substrate, and the chip is a stacked CMOS image sensor chip.

Further, each of the chips is distributed in an array on the wafer 200, and a cutting road 203 is provided between adjacent chips. Among them, the chip includes a device area 201 and a protection ring 202. A device structure is provided in the device area 201, which is not illustrated in detail in this embodiment. The protection ring 202 surrounds the device area 201, and the protection ring 202 is generally composed of a plurality of metal layers, metal connection holes, and oxide layers, etc., which are superimposed and combined according to certain rules to form a ring structure, which is used to protect the device area 201 to prevent it from being disturbed by the external environment, and to prevent any external force such as cracks from invading the device area 201, causing damage to the chip. In particular, during the wafer 200 cutting process, the protection ring 202 can have a certain blocking effect on the impact of mechanical force. And, a buffer zone 204 is also provided between the cutting road 203 and the protection ring 202. The buffer zone 204 extends a set distance from the edge of the cutting road 203 toward the protection ring 202, which is used to achieve stress buffering during the wafer 200 cutting process. Specifically, the stress energy generated during the wafer 200 cutting process is released in the form of crack diffusion. Therefore, the reserved buffer area 204 is used as a sacrificial area to accommodate the diffused cracks and prevent the cracks from further spreading to the guard ring 202 and the device area 201 in the chip as much as possible.

It should be noted that the cross-sectional views in the drawings of this specification only illustrate the general structure of such a chip and highlight the structure of the patent claims for easy understanding. Due to different designs, the detailed structure is also different, and no detailed illustration is given here.

Step 2 S20: Please refer to Figures 6 to 12. At least two deep grooves 205 are set between the protection ring 202 of each chip and the corresponding cutting road 203, and one of the deep grooves 205 is close to the outer edge of the protection ring 202 and is set along the outer periphery of the protection ring 202.

As can be seen from the above, during the cutting process of the wafer 200, the cutting stress will inevitably form cracks on the wafer 200, and gradually release energy by extending and diffusing. Therefore, the buffer zone 204 is reserved between the protective ring 202 and the cutting path 203 as a sacrificial area for crack diffusion. However, it is difficult to effectively block stress intrusion by relying solely on the buffer zone 204 to absorb the influence of stress, and the risk of the chip being damaged by stress is still very high. Therefore, the method provided in this embodiment further buffers the release of cutting stress by setting the deep groove 205 on the outside of the buffer zone 204 and the protective ring 202, which can not only improve the blocking effect on stress intrusion, but also reduce the area of the buffer zone 204, so as to increase the effective occupancy rate of the device area 201 in the chip to the wafer 200 and reduce the preparation cost.

Please refer to Figures 6 and 7. The deep groove 205 provided in this embodiment is annular and is arranged around the outer periphery of the protection ring 202, and is similar to the horizontal morphology of the protection ring 202. That is, the deep groove 205 surrounds the protection ring 202 on all sides, and is used to evenly and fully block the cutting stress around the protection ring 202 during the wafer cutting process. Preferably, the number of the deep grooves 205 is greater than or equal to 2, and each of the deep grooves 205 is nested in sequence and arranged around the outer periphery of the protection ring 202. Among them, at least one of the deep grooves 205 is close to the outer edge of the protection ring 202 and is arranged around the outer edge of the protection ring 202, and the remaining deep grooves 205 are arranged in the buffer zone 204. It should be noted that the stacked CMOS image sensor chip is formed by bonding at least two wafers, and the top surface of the wafer located above has a single crystal silicon layer 206, that is, the epitaxial layer of the pixel wafer. Monocrystalline silicon is an inorganic substance with the characteristics of high hardness and low toughness. When subjected to cutting stress, it will diffuse stress in the form of cracks and affect the yield of the chip. Therefore, in this embodiment, at least two deep grooves 205 are arranged on the monocrystalline silicon layer 206, so that in the process of the cutting stress being transmitted toward the chip, its energy is greatly reduced each time it passes through a deep groove 205, thereby effectively blocking the diffusion of stress, reducing the risk of chip damage, and improving the yield of the device. And, preferably, in this embodiment, a deep groove 205 is arranged near the outer edge of the guard ring 202 as the last insurance barrier to block the diffusion of stress, ensuring that the stress invasion can be completely blocked to achieve effective protection of the device area 201.

Furthermore, the specific process of forming the deep trench 205 in this embodiment is as follows: as shown in FIG8 , first, a hard mask layer 207 and a patterned photoresist layer 208 are sequentially formed on the surface of the single crystal silicon layer 206. The hard mask layer 207 covers the chip, the cutting road 203, and the area between the chip and the cutting road 203. The patterned photoresist layer 208 covers the hard mask layer 207 and exposes part of the hard mask layer 207. Then, as shown in FIG9 , the hard mask layer 207 is etched with the patterned photoresist layer 208 as a barrier, and a partial area between the chip and the cutting road 203 is exposed. That is, the exposed partial area corresponds to the opening position of the deep trench 205. Secondly, as shown in FIG10 , the exposed partial area between the chip and the cutting road 203 is etched with the hard mask layer 207 as a barrier to form the at least two deep trenches 205. Finally, the hard mask layer 207 is removed and the semiconductor structure is cleaned to form the semiconductor structure shown in Figures 6 and 7. The present embodiment does not limit the specific material and thickness of the hard mask layer 207, nor does it limit the specific etching process and cleaning process.

Further, the present embodiment does not limit the specific morphology, size, quantity and specific distribution of the deep grooves 205. Preferably, each of the deep grooves 205 is evenly distributed between the protection ring 202 and the corresponding cutting path 203. That is, the horizontal spacing between each part of each deep groove 205 and the corresponding parts of the protection ring 202 is equal, and the opening width and groove depth of each area in each deep groove 205 are equal. Exemplarily, as shown in FIG11, the protection ring 202 is rectangular, and the morphology of each deep groove 205 is adapted to the morphology of the protection ring 202 and is also rectangular. The side of each deep groove 205 is parallel to the side corresponding to the protection ring 202 to ensure the uniformity of the stress blocking effect on the same side of the chip, and avoid the inclination of the setting direction of the deep groove 205, which causes the stress energy of some areas on the same X-axis coordinate or the same Y-axis coordinate to be strong or the stress energy of some areas to be weak, affecting the stress blocking effect. Furthermore, the opening widths of the two deep grooves 205 are constant in a circle around the chip, and the spacings between the four groove edges of the deep groove 205 far from the protection ring 202 and the corresponding side edges of the protection ring 202 in the directions of the X-axis coordinate and the Y-axis coordinate are all D. Similarly, the horizontal spacings between the four groove edges of the deep groove 205 close to the protection ring 202 and the corresponding side edges of the protection ring 202 are also equal, in order to ensure that the stress diffusion in all directions is evenly blocked during the wafer 200 cutting process.

Preferably, the opening sizes of the deep grooves 205 are the same, or the opening sizes of some of the deep grooves 205 are different. Exemplarily, as shown in FIG12 , two deep grooves 205 are arranged on the periphery of the protection ring 202, and the opening width of the deep groove 205 close to the cutting road 203 is larger than the opening width of the deep groove 205 close to the protection ring 202, so as to block as much stress as possible in the initial diffusion period and relieve the pressure of subsequent stress blocking.

Based on the same inventive concept, this embodiment further provides a semiconductor structure. Please refer to Figures 6 to 12, the semiconductor structure is prepared by the above-mentioned method for preparing a semiconductor structure.

Based on the same inventive concept, this embodiment also provides a wafer cutting method, which includes: first forming the semiconductor structure described above; then cutting the semiconductor structure along the cutting path 203 by mechanical contact diamond wheel cutting or laser invisible cutting to separate the plurality of chips.

In summary, the semiconductor structure and its preparation method and wafer cutting method provided in this embodiment are to set at least two deep grooves 205 between the outer side of the protection ring 202 and the cutting road 203, and one of the deep grooves 205 is set close to the outer edge of the protection ring 202. Among them, the deep groove 205 set close to the outer edge of the protection ring 202 is used as a safety barrier for the chip to effectively block the stress diffusion. The deep groove 205 far away from the protection ring 202 is used to buffer the stress during the stress diffusion process and weaken the stress energy, thereby achieving multi-channel blocking of stress diffusion and effectively improving the device yield. In addition, compared with forming a deep groove with a larger opening on the protection ring 202, the method provided in this embodiment can not only improve the stress blocking effect, but also reduce the opening size of the deep groove 205, reduce the spatial proportion of the deep groove 205 occupying the buffer zone 204, and also help to reduce the size of the buffer zone 204, improve the effective occupancy rate of the chip area on the wafer 200, and reduce the device preparation cost.

In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims (10)

1. A method for preparing a semiconductor structure, comprising: A wafer is provided, on which a plurality of chips are formed, wherein the chip at least comprises a device region and a protection ring surrounding the device region, and a dicing path is provided between adjacent chips; At least two deep grooves are arranged between the protection ring of each chip and the corresponding dicing road, and one of the deep grooves is close to the outer edge of the protection ring and arranged along the outer periphery of the protection ring. 2 . The method for preparing a semiconductor structure according to claim 1 , wherein a buffer zone is provided between the cutting street and the guard ring, and the deep trench away from the outer edge of the guard ring is provided in the buffer zone. 3 . The method for preparing a semiconductor structure according to claim 1 , wherein the deep trench is ring-shaped, and the morphology of the deep trench is compatible with the morphology of the guard ring. 4 . The method for preparing a semiconductor structure according to claim 3 , wherein the at least two deep trenches are nested in sequence and arranged around the periphery of the guard ring. 5 . 5 . The method for preparing a semiconductor structure according to claim 1 , wherein the at least two deep trenches are arranged at intervals, and horizontal spacings between respective portions of the deep trenches and respective portions corresponding to the guard rings are equal. 6 . The method for preparing a semiconductor structure according to claim 1 , wherein the opening sizes of the deep trenches are the same, or the opening sizes of some of the deep trenches are different. 7. The method for preparing a semiconductor structure according to claim 1, wherein the process of forming the deep trench comprises: forming a hard mask layer, wherein the hard mask layer covers the chip, the dicing road, and an area between the chip and the dicing road; forming a patterned photoresist layer, wherein the patterned photoresist layer covers the hard mask layer; Using the patterned photoresist layer as a barrier, etching the hard mask layer and exposing a portion of the area between the guard ring and the cutting path; removing the patterned photoresist layer; The hard mask layer is used as a barrier to etch the partial area between the protection ring and the cutting path to form the at least two deep trenches. 8 . The method for preparing a semiconductor structure according to claim 7 , wherein after forming the at least two deep trenches, the hard mask layer is removed and the semiconductor structure is cleaned. 9. A semiconductor structure, characterized in that it is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 8. 10. A wafer cutting method, comprising: Forming the semiconductor structure as claimed in claim 9; The semiconductor structure is cut along the cutting paths to separate a plurality of chips.