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JP2008192762A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Method of manufacturing semiconductor device, and semiconductor device Download PDF

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JP2008192762A
JP2008192762A JP2007024616A JP2007024616A JP2008192762A JP 2008192762 A JP2008192762 A JP 2008192762A JP 2007024616 A JP2007024616 A JP 2007024616A JP 2007024616 A JP2007024616 A JP 2007024616A JP 2008192762 A JP2008192762 A JP 2008192762A
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semiconductor device
wafer
manufacturing
dicing
penetrating
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Kazuaki Kojima
一哲 小島
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Olympus Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10156Shape being other than a cuboid at the periphery

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Abstract

<P>PROBLEM TO BE SOLVED: To reduce a manufacturing cost of a semiconductor device by shortening the processing time and improving the workability. <P>SOLUTION: A wafer 1 is formed with a plurality of element portions 3 demarcated by scribe lines 2 in an ordinary wafer process (a semiconductor manufacturing process). Then, in a through portion formation process, through portions 5 which penetrate the wafer 1 from the front to rear face are formed in regions including intersecting points P between the scribe lines 2 except for the plurality of element portions 3 using chemical machining and physical machining. Thereafter, in a dicing process, the wafer 1 is diced along the scribe lines 2 into individual semiconductor devices 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、円形、若しくは、多角形形状の半導体装置を形成する、所謂、チップサイズパッケージ(Chip Size Package:CSP)タイプの半導体装置の製造方法、及び、半導体装置に関する。   The present invention relates to a manufacturing method of a so-called chip size package (CSP) type semiconductor device for forming a circular or polygonal semiconductor device, and the semiconductor device.

従来の半導体装置は、ダイシングにより四角形に個片化され、リードフレームにマウントされてパッケージングされている。しかし、近年、携帯電話のカメラモジュールのようにセンサやIC等の半導体装置は、小型・薄型化が望まれており、半導体装置の形状そのものがパッケージサイズとなるCSPタイプの半導体装置が主流になりつつある。また、内視鏡分野等のニーズは、薄型化よりも上面から見た投影面積の小さい半導体装置が望まれている。これは、円筒形の管内に半導体装置を搭載する際に、円形若しくは多角形形状にすることで、径方向の投影面積を有効に利用できるためである。   A conventional semiconductor device is divided into quadrilateral pieces by dicing, mounted on a lead frame, and packaged. However, in recent years, semiconductor devices such as sensors and ICs such as camera modules of mobile phones have been desired to be small and thin, and CSP type semiconductor devices in which the shape of the semiconductor device itself is the package size have become mainstream. It's getting on. Further, needs in the field of endoscope and the like are demanded for a semiconductor device having a small projected area as viewed from the top rather than being made thinner. This is because, when a semiconductor device is mounted in a cylindrical tube, the projected area in the radial direction can be effectively used by making it circular or polygonal.

多角形形状の半導体装置とその製造方法に関する技術として、例えば、特開2004−79667号公報では、モールド成型工程において応力集中による半導体装置の角部の破損等を防止するために、半導体装置の角部を面取りすることで応力を緩和した技術が開示されている。具体的には、個片化された四角形の半導体装置を、更に物理的加工で面取りする方法、或いは、ウエハからレーザ照射やエッチングにより多角形形状若しくは円形状に半導体装置を個片化する方法が開示されている。
特開2004−79667号公報
As a technique related to a polygonal semiconductor device and a manufacturing method thereof, for example, in Japanese Patent Application Laid-Open No. 2004-79667, a corner of a semiconductor device is prevented in order to prevent damage to a corner of the semiconductor device due to stress concentration in a molding process. A technique is disclosed in which stress is relieved by chamfering a portion. Specifically, there are a method of chamfering an individual rectangular semiconductor device by physical processing, or a method of dividing a semiconductor device into a polygonal shape or a circular shape by laser irradiation or etching from a wafer. It is disclosed.
JP 2004-79667 A

しかしながら、上述の特許文献1に開示される物理的加工で面取りする方法では、物理的な追加工を行うことになるため、加工時間が長くなるという問題がある。更に、この追加工は、半導体装置の形状を維持するために加工精度が要求され、複雑な加工設備等を準備しなければならない虞もある。また、上述の特許文献1に開示されるレーザ照射により半導体装置を個片化する方法では、レーザ光で半導体装置の分離領域を全て切断する必要があり、これもやはり加工時間が長くなるという問題がある。また、このレーザ照射により半導体装置を個片化する方法では、ウエハの結晶の方向によっては切断が困難な場合が生じる。更に、上述の特許文献1に開示されるエッチングにより半導体装置を個片化する方法では、エッチングにより個片化した際に半導体装置がばらばらになるため、作業性が悪くなるという課題がある。   However, the method of chamfering by physical processing disclosed in Patent Document 1 described above has a problem that processing time becomes long because physical additional processing is performed. Furthermore, this additional processing requires processing accuracy in order to maintain the shape of the semiconductor device, and there is a possibility that complicated processing equipment or the like must be prepared. Further, in the method of separating a semiconductor device by laser irradiation disclosed in Patent Document 1 described above, it is necessary to cut all the isolation regions of the semiconductor device with laser light, which also increases the processing time. There is. Further, in this method of dividing a semiconductor device by laser irradiation, it may be difficult to cut depending on the crystal direction of the wafer. Furthermore, the method disclosed in Patent Document 1 described above that separates a semiconductor device by etching has a problem in that workability deteriorates because the semiconductor device is separated when the semiconductor device is separated by etching.

本発明は上記事情に鑑みてなされたもので、半導体装置の加工時間の短縮化、作業性の向上を図り、製造コストのダウンを図ることができる半導体装置の製造方法、及び、半導体装置を提供することを目的としている。   The present invention has been made in view of the above circumstances, and provides a semiconductor device manufacturing method and a semiconductor device capable of shortening the processing time of the semiconductor device, improving workability, and reducing the manufacturing cost. The purpose is to do.

本発明による半導体装置の製造方法は、スクライブラインで区画して素子部を形成したウエハの、該素子部以外の上記スクライブライン同士の交点を含む領域に、上記ウエハを貫通する貫通部を形成する貫通部形成工程と、上記貫通部を形成したウエハをダイシングして個々の半導体装置に個片化するダイシング工程とを備えたことを特徴とし、本発明による半導体装置は、この製造方法により製造される。   In the method of manufacturing a semiconductor device according to the present invention, a penetrating portion penetrating the wafer is formed in a region including an intersection of the scribe lines other than the element portion of a wafer that is partitioned by a scribe line to form an element portion. A semiconductor device according to the present invention is manufactured by this manufacturing method, comprising: a through portion forming step; and a dicing step of dicing the wafer on which the through portion is formed into individual semiconductor devices. The

本発明による半導体装置の製造方法、及び、半導体装置によれば、半導体装置の加工時間の短縮化、作業性の向上を図り、製造コストのダウンを図ることが可能となる。   According to the method for manufacturing a semiconductor device and the semiconductor device according to the present invention, it is possible to shorten the processing time of the semiconductor device, improve the workability, and reduce the manufacturing cost.

以下、図面に基づいて本発明の実施の形態を説明する。
図1〜図4は本発明の実施の第1形態を示し、図1は素子部を形成したウエハの正面図、図2は貫通部を形成したウエハの正面図、図3は貫通部の拡大説明図、図4はスクライブラインによりダイシングした半導体装置の説明図である。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 4 show a first embodiment of the present invention, FIG. 1 is a front view of a wafer on which an element portion is formed, FIG. 2 is a front view of a wafer on which a through portion is formed, and FIG. 3 is an enlarged view of the through portion. FIG. 4 is an explanatory view of a semiconductor device diced by a scribe line.

図1において、符号1は、通常のウエハプロセス(半導体製造工程)にてスクライブライン2で区画された複数の素子部3を形成したウエハを示し、このウエハ1から、後述する貫通部形成工程とダイシング工程を経て、図4中に示す、多角形(本第1形態では八角形を例とする)の平面構造を有する複数の半導体装置4が得られるようになっている。   In FIG. 1, reference numeral 1 denotes a wafer on which a plurality of element parts 3 partitioned by a scribe line 2 are formed in a normal wafer process (semiconductor manufacturing process). Through the dicing process, a plurality of semiconductor devices 4 having a polygonal planar structure (in the first embodiment, an octagon is taken as an example) shown in FIG. 4 are obtained.

まず、貫通部形成工程について説明する。
この貫通部形成工程は、図2、図3に示すように、上記ウエハ1に対し、上記複数の素子部3以外の各スクライブライン2同士の交点Pを含む領域に、上記ウエハ1を表面から裏面まで貫通する貫通部5を形成する工程となっている。
First, a penetration part formation process is demonstrated.
As shown in FIG. 2 and FIG. 3, the through-hole forming process is performed by placing the wafer 1 from the surface in a region including the intersection P between the scribe lines 2 other than the plurality of element portions 3 with respect to the wafer 1. This is a process of forming the penetrating part 5 penetrating to the back surface.

貫通部5は、ウェットエッチングやドライエッチング等の化学的加工や、サンドブラストやレーザ或いはウォータジェット等の物理的加工を用いて形成される。   The through portion 5 is formed using chemical processing such as wet etching or dry etching, or physical processing such as sand blasting, laser, or water jet.

具体的には、貫通部5以外の表面に、フィルムやレジスト或いはSi02薄膜などの保護膜を形成し、エッチング等の加工を実施する。   Specifically, a protective film such as a film, a resist, or a Si02 thin film is formed on the surface other than the penetrating part 5, and processing such as etching is performed.

貫通部5の形成に、水酸化カリウム(KOH)や水酸化テトラメチルアンモニウム(TMAH)溶液等のエッチングレートの遅い結晶面の〈111〉面が露出するウェット異方性エッチングを用いる場合、表面が〈100〉面を持つウエハ1で、且つ、オリエンテーションフラット(Orientation Flat:以下オリフラOFと略称)方向が〈110〉のウエハ1を用いる場合は、図2(a)に示すような、各貫通部5の四辺がオリフラOFに対して45度傾いているレイアウトに貫通部5が形成できる。   When wet anisotropic etching that exposes the <111> plane of a crystal plane with a slow etching rate, such as a potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) solution, is used to form the penetrating part 5. When the wafer 1 having a <100> plane and the orientation flat (hereinafter abbreviated as orientation flat OF) direction <110> is used, each penetrating portion as shown in FIG. The penetrating part 5 can be formed in a layout in which the four sides of 5 are inclined 45 degrees with respect to the orientation flat OF.

また、表面が〈100〉面を持つウエハ1で、且つ、オリフラOF方向が〈100〉のウエハ1を用いる場合は、ウエハ1上の素子部3の配列等のレイアウトを全体的に45度回転させて形成すれば、図2(b)に示すような、各貫通部5の四辺がオリフラOFに対して垂直或いは平行なレイアウトに貫通部5が形成できる。   Further, when the wafer 1 having the <100> surface and the orientation flat OF direction <100> is used, the layout of the elements 3 on the wafer 1 is rotated by 45 degrees as a whole. If formed, the through portions 5 can be formed in a layout in which the four sides of each through portion 5 are perpendicular or parallel to the orientation flat OF as shown in FIG.

一方、貫通部5を、ドライエッチングによる化学的加工、若しくは、サンドブラストやレーザ等の物理的加工にて形成する場合は、ウエハ1の面方位やオリフラOF方向の如何に拘わらず、貫通部5の形状を円形形状や多角形形状等の任意の形に形成できる。   On the other hand, when the penetrating part 5 is formed by chemical processing by dry etching or physical processing such as sand blasting or laser, the penetrating part 5 is formed regardless of the plane orientation of the wafer 1 or the orientation flat OF direction. The shape can be formed into an arbitrary shape such as a circular shape or a polygonal shape.

本実施の第1形態では、製造する半導体装置を八角形の半導体装置4を例に説明したため、貫通部5は、図3(a)に示すように、素子部3の4隅の部分の、素子部3以外の各スクライブライン2同士の交点Pを含む領域に形成されることになる。そして、貫通部5の各辺は、半導体装置4の外形の一部を構成する。従って、貫通部5の形状は、製造される半導体装置4の外形形状に合わせて、4角形の形状に形成される。   In the first embodiment, since the semiconductor device to be manufactured has been described by taking the octagonal semiconductor device 4 as an example, the through portion 5 is formed at the four corners of the element portion 3 as shown in FIG. It is formed in a region including the intersection P between the scribe lines 2 other than the element portion 3. Each side of the penetrating portion 5 constitutes a part of the outer shape of the semiconductor device 4. Therefore, the shape of the penetrating portion 5 is formed in a quadrangular shape in accordance with the outer shape of the semiconductor device 4 to be manufactured.

また、図3(b)に示すように、製造する半導体装置が円形の半導体装置4の場合も同様に、貫通部5は、素子部3の4隅の部分の、素子部3以外の各スクライブライン2同士の交点Pを含む領域に形成されることになる。そして、貫通部5の各辺は、1/4の部分円の形状に形成されて、各々隣接する半導体装置4の外形の一部を構成する。   In addition, as shown in FIG. 3B, similarly, when the semiconductor device to be manufactured is a circular semiconductor device 4, the penetrating portion 5 has scribes other than the element portion 3 at the four corners of the element portion 3. It is formed in a region including the intersection P between the lines 2. Each side of the penetrating portion 5 is formed in a shape of a ¼ partial circle, and constitutes a part of the outer shape of the adjacent semiconductor device 4.

更に、図3(c)に示すように、製造する半導体装置が6角形の半導体装置4の場合も同様に、貫通部5は、素子部3の4隅の部分の、素子部3以外の各スクライブライン2同士の交点Pを含む領域に形成されることになる。そして、貫通部5の各辺は、半導体装置4の外形の一部を構成する。従って、貫通部5の形状は、製造される半導体装置4の外形形状に合わせて、菱形の形状に形成される。   Further, as shown in FIG. 3C, when the semiconductor device to be manufactured is a hexagonal semiconductor device 4, similarly, the penetrating portion 5 includes each of the four corner portions of the element portion 3 except for the element portion 3. It is formed in a region including the intersection P between the scribe lines 2. Each side of the penetrating portion 5 constitutes a part of the outer shape of the semiconductor device 4. Therefore, the shape of the penetrating portion 5 is formed in a rhombus shape in accordance with the outer shape of the semiconductor device 4 to be manufactured.

尚、上述の、円形、6角形、8角形以外の半導体装置であっても同様にして、貫通部5が形成される。   Note that the penetrating portion 5 is formed in the same manner even in a semiconductor device other than the above-described circular, hexagonal, and octagonal semiconductor devices.

上述の貫通部形成工程の後は、ダイシング工程に移り、図4(a)に示すように、ウエハ1は、スクライブライン2に沿って、ダイシングを行うことで個片化され、各半導体装置4が作成される。   After the above-described through-portion forming step, the process proceeds to a dicing step. As shown in FIG. 4A, the wafer 1 is diced along the scribe line 2 so that each semiconductor device 4 is divided. Is created.

尚、このダイシング工程には、通常のメカニカルなブレードダイシングや、結晶面の劈開により個片化するレーザダイシング装置を用いて各半導体装置4に個片化する。   In this dicing process, each semiconductor device 4 is separated into pieces by using normal mechanical blade dicing or a laser dicing apparatus that separates the crystal faces by cleavage.

また、図4(a)に示す例は、図2(a)に対応したオリフラOF方向が〈110〉のダイシング工程を示すものであるが、図2(b)に対応したオリフラOF方向が〈100〉のウエハ1を用いて素子部3の配列等のレイアウトを全体的に45度回転させている場合は、図4(b)に示すように、ダイシング工程も同様に、45度回転させてから行う。   The example shown in FIG. 4A shows a dicing process in which the orientation flat OF direction corresponding to FIG. 2A is <110>, but the orientation flat OF direction corresponding to FIG. 100>, when the layout of the arrangement of the element portions 3 and the like is rotated by 45 degrees as shown in FIG. 4B, the dicing process is similarly rotated by 45 degrees as shown in FIG. To do.

このように、本発明の実施の第1形態によれば、特に内視鏡装置等のような円筒形状の装置において、径方向に小型化可能な略円形若しくは多角形形状の半導体装置を、作業性良く製造できる。   As described above, according to the first embodiment of the present invention, a substantially circular or polygonal semiconductor device that can be miniaturized in the radial direction, particularly in a cylindrical device such as an endoscope device or the like. Can be manufactured with good performance.

また、本発明の実施の第1形態では、個々の半導体装置毎に略円形若しくは多角形形状に形成するのではなく、個片化する前にウエハプロセスにて一括して形成するため、量産に対応でき、作業性も良く、コストダウンを図ることが可能となる。   In the first embodiment of the present invention, each semiconductor device is not formed into a substantially circular or polygonal shape, but is formed in a lump in a wafer process before being separated into individual pieces. It is possible to cope with it, the workability is good, and the cost can be reduced.

更に、本発明の実施の第1形態では、貫通部形成工程にチッピングの発生しないエッチング等の化学的加工を用いれば、ブレードダイシングによってチッピングの影響がでるダイシング領域も減少し、また、ダイシングブレードもダイシングを開始する部分に対して鈍角な角度で当接していくことが可能となるため信頼性も向上する。   Furthermore, in the first embodiment of the present invention, if chemical processing such as etching that does not cause chipping is used in the through-hole forming step, the dicing area where the influence of chipping is caused by blade dicing is reduced, and the dicing blade is also reduced. Since it becomes possible to abut at an obtuse angle with respect to the portion where dicing is started, reliability is also improved.

尚、本発明のダイシング工程に、結晶面の劈開により個片化するレーザダイシング装置を用い、上述の化学的加工による貫通部形成工程と併用すれば、全ての工程でチッピングの発生しない工程が実現でき、さらに信頼性が向上する。   In addition, if the dicing process of the present invention uses a laser dicing apparatus that divides into pieces by cleavage of the crystal plane and is used in combination with the above-described through-hole forming process by chemical processing, a process in which no chipping occurs is realized in all processes. And reliability is further improved.

次に、図5は本発明の実施の第2形態による貫通部を形成したウエハの断面図である。尚、本実施の第2形態は、貫通部形成工程を表面と裏面の両面から行うことが前記第1形態と異なり、他の構成及び工程は前記第1形態と同様であるので、同じ構成には同じ符号を記し、説明は省略する。   Next, FIG. 5 is a cross-sectional view of a wafer on which a penetrating portion according to a second embodiment of the present invention is formed. The second embodiment differs from the first embodiment in that the penetrating portion forming step is performed from both the front and back surfaces, and the other configurations and processes are the same as the first embodiment. Are denoted by the same reference numerals, and description thereof is omitted.

すなわち、図5に示すように、本実施の第2形態による貫通部形成工程は、例えば、ウェット異方性エッチングによって貫通部5を形成するものであり、ウエハ1の表面1aと裏面1bの両面にウェット異方性エッチングの際の保護膜を形成し、ウエハ1の表面1aと裏面1bの両面から同時にエッチングを実施する。   That is, as shown in FIG. 5, in the penetration portion forming step according to the second embodiment, the penetration portion 5 is formed by wet anisotropic etching, for example, and both surfaces of the front surface 1 a and the back surface 1 b of the wafer 1 are formed. Then, a protective film for wet anisotropic etching is formed, and etching is performed simultaneously from both the front surface 1 a and the back surface 1 b of the wafer 1.

このように、本発明の実施の第2形態によれば、前記第1形態に比べ、貫通部5の形成に要するエッチング時間が半減されるため、コスト低減にさらに寄与することができる。   Thus, according to the second embodiment of the present invention, the etching time required for forming the penetrating portion 5 is halved compared to the first embodiment, which can further contribute to cost reduction.

特に、貫通部5の形成にウェット異方性エッチングを用いた場合は、貫通部5の深さが貫通部5表面の各辺の寸法に比例するため、各辺の寸法は、通常の寸法(図中のL)の1/2にまで縮小することができ、これにより貫通部5の面積も、(1/2)=1/4にまで縮小することができる。このため、貫通部5の寸法は1/2〜1.0倍の間で自由に選択できるので、小さなパッケージタイプの半導体装置に対しても容易に適用でき、半導体装置のレイアウト等、設計上の自由度も向上させることが可能となる。 In particular, when wet anisotropic etching is used to form the penetrating portion 5, the depth of the penetrating portion 5 is proportional to the size of each side of the surface of the penetrating portion 5. It can be reduced to 1/2 of L) in the figure, and thereby the area of the penetrating portion 5 can also be reduced to (1/2) 2 = ¼. For this reason, since the dimension of the penetrating part 5 can be freely selected between 1/2 and 1.0 times, it can be easily applied to a small package type semiconductor device. The degree of freedom can be improved.

次に、図6は本発明の実施の第3形態による貫通部形成工程を説明するウエハの断面図である。尚、本実施の第3形態は、貫通部形成工程をウエハの表面から溝部を形成するトレンチ工程とウエハの裏面から研磨してウエハを薄くするグラインド工程とで構成したことが前記第1形態と異なり、他の構成及び工程は前記第1形態と同様であるので、同じ構成には同じ符号を記し、説明は省略する。   Next, FIG. 6 is a cross-sectional view of the wafer for explaining the through-hole forming step according to the third embodiment of the present invention. In the third embodiment, the through-hole forming step includes a trench step for forming a groove from the front surface of the wafer and a grinding step for polishing the wafer from the back surface to thin the wafer. Unlike other configurations and processes, which are the same as those in the first embodiment, the same components are denoted by the same reference numerals, and description thereof is omitted.

すなわち、図6(a)中の符号1は、通常のウエハプロセス(半導体製造工程)にてスクライブラインで区画された複数の素子部3を形成したウエハを示す。   That is, reference numeral 1 in FIG. 6A indicates a wafer on which a plurality of element portions 3 partitioned by a scribe line are formed in a normal wafer process (semiconductor manufacturing process).

そして、この図6(a)に示すウエハ1に対し、ウエハ1表面の、前記第1形態における貫通部5を形成したのと同様の領域、すなわち、複数の素子部3以外の各スクライブライン同士の交点を含む領域に、まず、図6(b)に示すように、溝部6を形成する。すなわち、この溝部6を形成する工程がトレンチ工程である。   Then, with respect to the wafer 1 shown in FIG. 6 (a), the same area on the surface of the wafer 1 as that in which the penetrating part 5 in the first embodiment is formed, that is, the scribe lines other than the plurality of element parts 3 First, as shown in FIG. 6B, a groove 6 is formed in a region including the intersection of. That is, the process of forming the groove 6 is a trench process.

このトレンチ工程における溝部6の形成は、前記第1形態の貫通部5の形成と同様に、ウェットエッチングやドライエッチング等の化学的加工や、サンドブラスト・レーザ・ウォータジェット等の物理的加工を用いて形成される。   In the trench process, the groove 6 is formed using chemical processing such as wet etching or dry etching, or physical processing such as sand blasting, laser water jet, or the like, similar to the formation of the through portion 5 of the first embodiment. It is formed.

その後、図6(c)に示すように、ウエハ1のウエハ厚を裏面より薄く研磨して、溝部6を貫通部とさせる。すなわち、この工程がグラインド工程である。   Thereafter, as shown in FIG. 6C, the wafer 1 is polished to have a thickness smaller than that of the back surface, so that the groove 6 becomes a through portion. That is, this process is a grinding process.

尚、上述のトレンチ工程とグラインド工程は、その順番が逆であっても良い。そして、この第3形態に対し、前記第2形態を適用して、ウエハ1の両面より、トレンチ工程を行うことも可能であるが、この場合は、先にグラインド工程を行う必要がある。   The order of the trench process and the grinding process described above may be reversed. In addition, it is possible to perform the trench process from both surfaces of the wafer 1 by applying the second form to the third form, but in this case, it is necessary to perform the grinding process first.

このように、本発明の実施の第3形態によれば、一般的にグラインドは、エッチングよりも短時間で行えるため、ウエハ厚を薄くすることで貫通部(溝部)6の形成にかかる時間を短縮でき、コストの低減に寄与することが可能となる。また、ウエハ1が薄くなるため、貫通部形成工程後のダイシング工程に必要な時間も短縮できる。更に、ウエハ1を薄くできるため、ダイシングブレードに対する負荷も軽減され、信頼性の向上、ダイシングブレードの耐久性の向上を図ることも可能となる。   As described above, according to the third embodiment of the present invention, grinding can generally be performed in a shorter time than etching. Therefore, by reducing the wafer thickness, the time required for forming the through portion (groove portion) 6 can be reduced. It can be shortened and can contribute to cost reduction. Moreover, since the wafer 1 is thinned, the time required for the dicing process after the through-hole forming process can be shortened. Furthermore, since the wafer 1 can be made thinner, the load on the dicing blade is also reduced, and it becomes possible to improve the reliability and the durability of the dicing blade.

以上説明したように、本発明によれば、円筒形形状の装置(例えば、内視鏡装置)等に用いる、径方向に小型化可能な略円形若しくは多角形形状の半導体装置を、作業性良く製造できる。また、個々の半導体装置毎に略円形若しくは多角形形状に形成するのではなく、個片化する前にウエハプロセスにて一括で形成するため、量産に対応でき、作業性も良く、コストダウンが実現できる。更に、本発明の貫通部形成工程に、チッピングの発生しないエッチング等の化学的加工を用いれば、ブレードダイシングによってチッピングの影響がでるダイシング領域も減少するため信頼性も向上する。加えて、本発明のダイシング工程に、結晶面の劈開により個片化するレーザダイシング装置等を用いれば、全てチッピングが発生しない半導体装置が実現でき、さらに信頼性を向上させることも可能となる。   As described above, according to the present invention, a substantially circular or polygonal semiconductor device that can be miniaturized in the radial direction, which is used in a cylindrical device (for example, an endoscope device) or the like, is improved in workability. Can be manufactured. In addition, each semiconductor device is not formed into a substantially circular or polygonal shape, but is formed in a lump in a wafer process before being singulated, so that it can be used for mass production, has good workability, and reduces costs. realizable. Furthermore, if chemical processing such as etching that does not cause chipping is used in the through-hole forming process of the present invention, the dicing area that is affected by chipping is reduced by blade dicing, so that the reliability is improved. In addition, if a laser dicing apparatus or the like that is separated into pieces by cleavage of crystal planes is used in the dicing process of the present invention, a semiconductor device that does not generate chipping can be realized, and the reliability can be further improved.

本発明の実施の第1形態による、素子部を形成したウエハの正面図The front view of the wafer in which the element part was formed by 1st Embodiment of this invention 同上、貫通部を形成したウエハの正面図Same as above, front view of wafer with through hole 同上、貫通部の拡大説明図Same as above, enlarged illustration of penetration 同上、スクライブラインによりダイシングした半導体装置の説明図As above, an explanatory diagram of a semiconductor device diced by a scribe line 本発明の実施の第2形態による、貫通部を形成したウエハの断面図Sectional drawing of the wafer in which the penetration part was formed by the 2nd Embodiment of this invention 本発明の実施の第3形態による、貫通部形成工程を説明するウエハの断面図Sectional drawing of the wafer explaining a penetration part formation process by a 3rd embodiment of the present invention

符号の説明Explanation of symbols

1 ウエハ
2 スクライブライン
3 素子部
4 半導体装置
5 貫通部
6 溝部(貫通部)
DESCRIPTION OF SYMBOLS 1 Wafer 2 Scribe line 3 Element part 4 Semiconductor device 5 Penetration part 6 Groove part (penetration part)

Claims (8)

スクライブラインで区画して素子部を形成したウエハの、該素子部以外の上記スクライブライン同士の交点を含む領域に、上記ウエハを貫通する貫通部を形成する貫通部形成工程と、
上記貫通部を形成したウエハをダイシングして個々の半導体装置に個片化するダイシング工程と、
を備えたことを特徴とする半導体装置の製造方法。
A penetration part forming step of forming a penetration part penetrating the wafer in a region including an intersection of the scribe lines other than the element part of the wafer partitioned by the scribe line to form the element part;
A dicing step of dicing the wafer having the penetrating portion into individual semiconductor devices;
A method for manufacturing a semiconductor device, comprising:
上記貫通部形成工程で形成する上記貫通部は、上記半導体装置の外形の一部であることを特徴とする請求項1記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 1, wherein the through portion formed in the through portion forming step is a part of an outer shape of the semiconductor device. 上記貫通部形成工程は、化学的加工と機械的加工の少なくとも一方の加工により行うことを特徴とする請求項1又は請求項2記載の半導体装置の製造方法。   3. The method of manufacturing a semiconductor device according to claim 1, wherein the penetrating portion forming step is performed by at least one of chemical processing and mechanical processing. 上記貫通部形成工程は、上記ウエハの両面から行うことを特徴とする請求項1乃至請求項3の何れか一つに記載の半導体装置の製造方法。   4. The method for manufacturing a semiconductor device according to claim 1, wherein the through-hole forming step is performed from both surfaces of the wafer. 上記貫通部形成工程は、上記ウエハの表面から溝部を形成するトレンチ工程と、
上記ウエハの裏面から研磨して上記ウエハを薄くするグラインド工程と、
を有することを特徴とする請求項1乃至請求項4の何れか一つに記載の半導体装置の製造方法。
The penetrating portion forming step includes a trench step of forming a groove portion from the surface of the wafer,
A grinding step of thinning the wafer by polishing from the back surface of the wafer;
5. The method of manufacturing a semiconductor device according to claim 1, comprising:
上記貫通部形成工程は、上記トレンチ工程の後、上記グラインド工程を実行することを特徴とする請求項5記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein the through-hole forming step executes the grinding step after the trench step. 上記貫通部形成工程は、上記グラインド工程の後、上記トレンチ工程を実行することを特徴とする請求項5記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein the through-hole forming step executes the trench step after the grinding step. 上記請求項1乃至請求項7の何れか一つに記載の半導体装置の製造方法により製造したことを特徴とする半導体装置。   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.
JP2007024616A 2007-02-02 2007-02-02 Method of manufacturing semiconductor device, and semiconductor device Withdrawn JP2008192762A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146717A (en) * 2010-01-18 2011-07-28 Semiconductor Components Industries Llc Method of forming semiconductor die
JP2012059859A (en) * 2010-09-08 2012-03-22 Disco Abrasive Syst Ltd Semiconductor device
JP2017163063A (en) * 2016-03-11 2017-09-14 三菱電機株式会社 Semiconductor wafer and manufacturing method for the same
JP2019096656A (en) * 2017-11-20 2019-06-20 株式会社沖データ Semiconductor element, light emitting substrate, optical print head, image forming apparatus, and method for manufacturing semiconductor element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011146717A (en) * 2010-01-18 2011-07-28 Semiconductor Components Industries Llc Method of forming semiconductor die
JP2012059859A (en) * 2010-09-08 2012-03-22 Disco Abrasive Syst Ltd Semiconductor device
JP2017163063A (en) * 2016-03-11 2017-09-14 三菱電機株式会社 Semiconductor wafer and manufacturing method for the same
JP2019096656A (en) * 2017-11-20 2019-06-20 株式会社沖データ Semiconductor element, light emitting substrate, optical print head, image forming apparatus, and method for manufacturing semiconductor element

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