CN118016676A - Array substrate and display panel - Google Patents

Abstract

The present application discloses an array substrate and a display panel, which can solve the problem of connection failure or impedance increase between upper and lower wiring. The array substrate includes: a substrate; a first metal layer, including a first wiring; a first insulating layer, including a first via; a second metal layer, including a connecting wiring; a second insulating layer, including a second via; a third metal layer, including a second wiring; wherein, in a direction perpendicular to the plane where the substrate is located, the first via is overlapped with the first wiring, the connecting wiring is connected to the first wiring through the first via, the second via is overlapped with the connecting wiring, and the second wiring is connected to the connecting wiring through the second via; wherein, the second metal layer includes a material with higher corrosion resistance than the third metal layer.

Description

Array substrate and display panel

Technical Field

The present application relates to the field of display technology, and in particular to an array substrate and a display panel.

Background technique

Currently, TFT-LCD (Thin Film Transistor-Liquid Crystal Display) has been widely used in display screens of mobile phones, televisions, notebook computers, etc. In a liquid crystal display panel or array substrate, the wiring in the upper metal layer is connected to the wiring in the lower metal layer through vias in the insulating layer.

However, the wiring in the upper metal layer and the wiring in the lower metal layer are easily corroded by water vapor at the via connection portion, resulting in failure of the via connection, thereby causing failure of the connection between the wiring in the upper metal layer and the wiring in the lower metal layer or increased impedance.

Summary of the invention

The embodiments of the present application provide an array substrate and a display panel, which can solve the problem in the prior art that the via connection parts are easily corroded by water vapor, etc., resulting in failure of the via connection, thereby causing the connection between the wiring in the upper metal layer and the wiring in the lower metal layer to fail or increase impedance.

According to a first aspect of an embodiment of the present application, an array substrate is provided, comprising:

substrate;

A first metal layer is disposed on one side of the substrate, wherein the first metal layer includes at least one first trace;

A first insulating layer, disposed on a side of the first metal layer away from the substrate, the first insulating layer comprising at least one first via hole;

A second metal layer is disposed on a side of the first insulating layer away from the substrate, the second metal layer comprising at least one connecting trace;

A second insulating layer, disposed on a side of the second metal layer away from the substrate, the second insulating layer comprising at least one second via hole;

A third metal layer is disposed on a side of the second insulating layer away from the substrate, and the third metal layer includes at least one second trace;

Wherein, in a direction perpendicular to the plane where the substrate is located, the first via hole and the first routing line are arranged to overlap, and the connecting routing line is connected to the first routing line through the first via hole;

Wherein, in a direction perpendicular to the plane where the substrate is located, the second via hole and the connecting wire are arranged to overlap, and the second wire is connected to the connecting wire through the second via hole;

The second metal layer includes a material having higher corrosion resistance than that of the third metal layer.

In some embodiments, the second metal layer includes at least two metal sub-layers, and at least one of the metal sub-layers of the second metal layer has higher corrosion resistance than that of the third metal layer.

In some embodiments, the material of the second metal layer includes at least one of titanium, chromium, and nickel.

In some embodiments, the material of the third metal layer includes at least one of transparent conductive metal oxide, copper, and aluminum.

In some embodiments, the first insulating layer includes a plurality of the first via holes, and the second insulating layer includes a plurality of the second via holes;

Wherein, in a direction perpendicular to the plane where the substrate is located, at least part of the second via holes is arranged overlapping with the corresponding first via holes; or/and

At least part of the second via holes is staggered with the first via holes.

In some embodiments, the number of the first vias is the same as the number of the second vias;

In a direction perpendicular to the plane where the substrate is located, the plurality of second via holes and the plurality of first via holes are all staggered or overlapped.

In some embodiments, the number of the first vias is less than the number of the second vias;

In a direction perpendicular to the plane where the substrate is located, the first via holes are all overlapped with the corresponding second via holes, and some of the second via holes are staggered with the first via holes.

In some embodiments, the number of the first vias is greater than the number of the second vias;

In a direction perpendicular to the plane where the substrate is located, the second via holes are all overlapped with the corresponding first via holes, and some of the first via holes are staggered with the second via holes.

In some embodiments, the array substrate includes a plurality of thin film transistors, and at least one of a pixel electrode and a common electrode;

The first metal layer also includes a gate of the thin film transistor;

The first insulating layer is a gate insulating layer;

The second metal layer also includes a source and a drain of the thin film transistor;

The third metal layer further includes the pixel electrode or the common electrode.

In some embodiments, the array substrate includes a display area and a non-display area located around the display area, and the first wiring, the connecting wiring, and the second wiring are all located in the non-display area.

According to a second aspect of the embodiments of the present application, a display panel is provided, comprising any one of the array substrates described above.

In the array substrate and display panel provided by the embodiments of the present application, in the present application, a connecting line is additionally provided, the second line is connected to the connecting line through the second via hole, and the connecting line is connected to the first line through the first via hole, so that the second line is connected to the first line through the connecting line, the second via hole and the first via hole. On the first hand, not only the total resistance of the first line and the second line before the corrosion failure is reduced, but also the total resistance of the first line and the second line after the corrosion failure is reduced. On the second hand, since the second metal layer includes a material with higher corrosion resistance than the third metal layer, the second metal layer can prevent the corrosion from further extending to the first line, thereby ensuring the normal connection of multiple first via holes. On the third hand, when a second via hole is corroded, the electrical signal is transmitted through the second via hole other than the corroded second via hole and multiple first via holes, which further ensures that the total resistance of the first line and the second line after the corrosion failure can be reduced. Fourthly, in the related art, the third metal layer or the second routing itself does not have time to corrode, but water vapor and the like pass through the second routing to reach the first routing, causing corrosion of the first routing. Therefore, the second metal layer or connecting routing in the embodiment of the present application blocks the path for water vapor to reach the first routing, ensuring that the first routing will not be corroded.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a partial top view schematic diagram of a portion of film layers of an array substrate in the related art provided by an embodiment of the present application;

FIG2 is a schematic cross-sectional view of the C-C dashed line in FIG1 provided in an embodiment of the present application;

FIG3 is a schematic cross-sectional view of the dashed line D-D in FIG1 provided in an embodiment of the present application;

FIG4 is a schematic diagram of an equivalent circuit of the array substrate in FIG2 provided in an embodiment of the present application;

FIG5 is a schematic diagram of partial via failure in the equivalent circuit of FIG4 provided in an embodiment of the present application;

FIG6 is a partial top view schematic diagram of a portion of a film layer of an array substrate provided in an embodiment of the present application;

FIG7 is a schematic cross-sectional view of a first array substrate provided in an embodiment of the present application, taken along a C-C dashed line or in a direction;

FIG8 is a schematic diagram of a cross section at the D-D dashed line in FIG6 provided in an embodiment of the present application;

FIG9 is a schematic diagram of an equivalent circuit of a first array substrate provided in an embodiment of the present application;

FIG10 is a schematic diagram of partial via failure in an equivalent circuit of a first array substrate provided in an embodiment of the present application;

FIG11 is a schematic cross-sectional view of a second array substrate provided in an embodiment of the present application, taken along a C-C dotted line or in a direction;

FIG12 is a schematic diagram of partial via failure in an equivalent circuit of a second array substrate provided in an embodiment of the present application;

FIG13 is a schematic cross-sectional view of a third array substrate provided in an embodiment of the present application, taken along a C-C dotted line or in a direction;

FIG14 is a schematic diagram of partial via failure in an equivalent circuit of a third array substrate provided in an embodiment of the present application;

FIG15 is a schematic cross-sectional view of a fourth array substrate provided in an embodiment of the present application, taken along a C-C dotted line or in a direction thereof;

FIG. 16 is a schematic diagram of partial via failure in an equivalent circuit of the fourth array substrate provided in an embodiment of the present application.

Detailed ways

In order to better understand the technical solutions provided by the embodiments of this specification, the technical solutions of the embodiments of this specification are described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

In this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. The term "more than two" includes two or more than two situations.

Please refer to Figures 1 to 5, Figure 1 is a partial top view schematic diagram of part of the film layer of the array substrate in the related technology provided in an embodiment of the present application; Figure 2 is a cross-sectional schematic diagram at the C-C dotted line in Figure 1 provided in an embodiment of the present application; Figure 3 is a cross-sectional schematic diagram at the D-D dotted line in Figure 1 provided in an embodiment of the present application; Figure 4 is an equivalent circuit schematic diagram of the array substrate in Figure 2 provided in an embodiment of the present application; Figure 5 is a schematic diagram of the failure of part of the vias in the equivalent circuit in Figure 4 provided in an embodiment of the present application; Figure 1 illustrates part of the film layer of the array substrate.

In the related art, the array substrate or display panel includes a first metal layer 12, at least one of a first insulating layer 13 and a second insulating layer 15, and a third metal layer 16. The first metal layer 12 includes a first wiring 121, the third metal layer 16 includes a second wiring 161, the first insulating layer 13 or/the second insulating layer 15 includes a large through hole 1351, and the second wiring 161 is connected to the first wiring 121 through the large through hole 1351 to achieve electrical connection between the first wiring 121 and the second wiring 161. However, corrosion is easily caused at the connection part of the large through hole 1351, for example, corrosion by water vapor, oxygen, etc., resulting in failure of the second wiring 161 to connect to the first wiring 121 through the large through hole 1351, as shown in FIG. 5, so that the connection between the second wiring 161 and the first wiring 121 fails or the impedance increases. The cross ("X") in FIG. 5 indicates that the connection at the large through hole 1351 is corroded and fails. After diligent analysis, the inventors discovered that, especially in narrow-frame products, when the first wiring 121, the second wiring 161, and the large through hole 1351 are located in the non-display area, the connection parts are more easily corroded by water vapor, etc., resulting in failure of the connection between the second wiring 161 and the first wiring 121 or worsening impedance increase.

In view of this, the present application provides an array substrate and a display panel, which can solve the above problems.

The present application provides an array substrate, comprising: a substrate; a first metal layer, arranged on one side of the substrate, the first metal layer comprising at least one first routing line; a first insulating layer, arranged on a side of the first metal layer away from the substrate, the first insulating layer comprising at least one first via hole; a second metal layer, arranged on a side of the first insulating layer away from the substrate, the second metal layer comprising at least one connecting routing line; a second insulating layer, arranged on a side of the second metal layer away from the substrate, the second insulating layer comprising at least one second via hole; a third metal layer, arranged on a side of the second insulating layer away from the substrate, the third metal layer comprising at least one second routing line; wherein, in a direction perpendicular to the plane where the substrate is located, the first via hole is arranged to overlap with the first routing line, and the connecting routing line is connected to the first routing line through the first via hole; wherein, in a direction perpendicular to the plane where the substrate is located, the second via hole is arranged to overlap with the connecting routing line, and the second routing line is connected to the connecting routing line through the second via hole; wherein, the second metal layer comprises a material having higher corrosion resistance than that of the third metal layer.

The present application also provides a display panel including the above array substrate.

The present application also provides a display device including the above array substrate and/or the above display panel.

Please refer to Figures 6 to 9, Figure 6 is a partial top view schematic diagram of a part of the film layer of an array substrate provided in an embodiment of the present application; Figure 7 is a cross-sectional schematic diagram at or in the direction of the C-C dotted line of the first array substrate provided in an embodiment of the present application; Figure 8 is a cross-sectional schematic diagram at the D-D dotted line in Figure 6 provided in an embodiment of the present application; Figure 9 is a schematic diagram of an equivalent circuit of the first array substrate provided in an embodiment of the present application; Figure 10 is a schematic diagram of the failure of some vias in the equivalent circuit of the first array substrate provided in an embodiment of the present application.

The present application provides an array substrate 100, which includes a substrate 11, a first metal layer 12, a first insulating layer 13, a second metal layer 14, a second insulating layer 15, and a third metal layer 16. The first metal layer 12 is disposed on one side of the substrate 11, and the first metal layer 12 includes at least one first trace 121; the first insulating layer 13 is disposed on a side of the first metal layer 12 away from the substrate 11, and the first insulating layer 13 includes at least one first via 131; the second metal layer 14 is disposed on a side of the first insulating layer 13 away from the substrate 11, and the second metal layer 14 includes at least one connecting trace 141; the second insulating layer 15 is disposed on a side of the second metal layer 14 away from the substrate 11, and the second insulating layer 15 includes at least one second via 151; the third metal layer 16 is disposed on the second insulating layer 14 On the side of layer 15 away from the substrate 11, the third metal layer 16 includes at least one second trace 161; wherein, in a direction perpendicular to the plane where the substrate 11 is located, the first via 131 and the first trace 121 are overlapped, and the connecting trace 141 is connected to the first trace 121 through the first via 131; wherein, in a direction perpendicular to the plane where the substrate 11 is located, the second via 151 and the connecting trace 141 are overlapped, and the second trace 161 is connected to the connecting trace 141 through the second via 151; wherein the second metal layer 14 includes a material with higher corrosion resistance than the third metal layer 16.

For example, the material of the substrate 11 may be glass or a flexible substrate, which is not limited here.

For example, as shown in FIG. 7 , the direction perpendicular to the plane where the substrate 11 is located is the first direction Y.

In the present application, a connecting line 141 is additionally provided, and the second line 161 is connected to the connecting line 141 through the second via 151, and the connecting line 141 is connected to the first line 121 through the first via 131, so that the second line 161 is connected to the first line 121 through the connecting line 141, the second via 151 and the first via 131.

As shown in FIG. 4 , taking three large through holes 1351 as an example, in the related art, the total resistance of the first routing line 121 and the second routing line 161 is _Rtotal , the resistance of the line segment of the first routing line 121 between two adjacent large through holes 1351 is R, and the resistance of the line segment of the second routing line 161 between two adjacent large through holes 1351 is also R, then As shown in FIG5 , when one of the connection parts of the three large through holes 1351 is corroded (the cross in FIG5 indicates that the connection part of a large through hole 1351 is corroded and fails), then it satisfies/>

As shown in FIG. 7 , taking three second vias 151 and three first vias 131 as an example, before the connection part fails, As shown in FIG8 , when one of the connection parts of the three second via holes 151 is corroded (the cross in FIG8 indicates that the connection of one of the second via holes 151 is corroded and fails), then the condition is satisfied.

Therefore, before corrosion occurs and fails, the _total R of the related art in FIG4 is 1.5 times that of the example in FIG7, so the embodiment of the present application reduces the total resistance of the first routing 121 and the second routing 161. After corrosion occurs and fails, compared with the related art in FIG5, in the example in FIG8, the electrical signal can also be transmitted through the second via 151 other than the corroded second via 151 and the plurality of first vias 131, so that the total resistance of the first routing 121 and the second routing 161 in the example in FIG8 is also smaller. Therefore, the present application not only reduces the total resistance of the first routing 121 and the second routing 161 before corrosion failure occurs, but also reduces the total resistance of the first routing 121 and the second routing 161 after corrosion failure occurs.

In addition, when corrosion occurs at a certain second via 151 , since the second metal layer 14 includes a material with higher corrosion resistance than the third metal layer 16 , the second metal layer 14 can prevent the corrosion from further extending to the first trace 121 , thereby ensuring normal connection of multiple first vias 131 .

In the present application, a connecting line 141 is added, and the second line 161 is connected to the connecting line 141 through the second via 151, and the connecting line 141 is connected to the first line 121 through the first via 131, so that the second line 161 is connected to the first line 121 through the connecting line 141, the second via 151 and the first via 131. On the first hand, not only the total resistance of the first line 121 and the second line 161 before the corrosion failure is reduced, but also the total resistance of the first line 121 and the second line 161 after the corrosion failure is reduced. On the second hand, since the second metal layer 14 includes a material with higher corrosion resistance than the third metal layer 16, the second metal layer 14 can prevent corrosion from further extending to the first line 121, thereby ensuring the normal connection of multiple first vias 131. On the third aspect, when a second via hole 151 corrodes, the electrical signal is transmitted through the second via holes 151 other than the corroded second via hole 151 and the plurality of first via holes 131, which further ensures that the total resistance of the first routing line 121 and the second routing line 161 after the corrosion failure can be reduced. On the fourth aspect, in the related art, the third metal layer 16 or the second routing line 161 itself does not have time to corrode, but water vapor reaches the first routing line 121 through the second routing line 161, causing the first routing line 121 to corrode. Therefore, in the embodiment of the present application, the second metal layer 14 or the connecting routing line 141 blocks the path of water vapor to the first routing line 121, ensuring that the first routing line 121 will not be corroded.

In some embodiments, the second metal layer 14 includes at least two metal sub-layers, and at least one metal sub-layer of the second metal layer 14 has higher corrosion resistance than the third metal layer 16 .

For example, the second metal layer 14 includes at least two metal sub-layers. As long as one metal sub-layer has higher corrosion resistance than the third metal layer 16, the corrosion can be prevented from further extending to the first trace 121, thereby ensuring the normal connection of the plurality of first vias 131. For example, the second metal layer 14 is a stacked structure of titanium/aluminum/titanium.

In some other embodiments, the second metal layer 14 includes a sub-metal layer of multiple mixed materials. In this case, the second metal layer 14 includes a material or element with higher corrosion resistance than the third metal layer 16, and can also prevent corrosion from further extending to the first trace 121, thereby ensuring the normal connection of the multiple first vias 131.

In some embodiments, the material of the second metal layer 14 includes at least one of titanium, chromium, and nickel.

In some embodiments, the material of the third metal layer 16 includes at least one of transparent conductive metal oxide, copper, and aluminum.

For example, the bright conductive metal oxide may be indium tin oxide (ITO).

On the one hand, transparent conductive metal oxides, copper, and aluminum are prone to corrosion in water vapor environments; on the other hand, transparent conductive metal oxides, copper, and aluminum are not dense enough and have insufficient water and gas isolation capabilities. Water vapor will penetrate the film layers of these materials and corrode the metal film layer under the vias.

Materials such as titanium, chromium, and nickel not only have excellent corrosion resistance, but also water vapor cannot penetrate these materials into the metal film layer below, thus avoiding the occurrence of corrosion problems.

Please refer to Figures 11 to 16, Figure 11 is a cross-sectional schematic diagram of the second array substrate provided in an embodiment of the present application at the C-C dotted line or in the direction; Figure 12 is a schematic diagram of the failure of some vias in the equivalent circuit of the second array substrate provided in an embodiment of the present application; Figure 13 is a cross-sectional schematic diagram of the third array substrate provided in an embodiment of the present application at the C-C dotted line or in the direction; Figure 14 is a schematic diagram of the failure of some vias in the equivalent circuit of the third array substrate provided in an embodiment of the present application; Figure 15 is a cross-sectional schematic diagram of the fourth array substrate provided in an embodiment of the present application at the C-C dotted line or in the direction; Figure 16 is a schematic diagram of the failure of some vias in the equivalent circuit of the fourth array substrate provided in an embodiment of the present application.

It should be noted that Figures 7, 11, 13 and 15 are all cross-sectional schematic diagrams at or in the direction of the C-C dotted line in Figure 6. Although the number of vias in Figures 13 and 15 does not correspond to that in Figure 6, this is because Figure 6 does not illustrate it, or Figures 13 and 15 illustrate multiple vias.

In some embodiments, the first insulating layer 13 includes a plurality of first vias 131, and the second insulating layer 15 includes a plurality of second vias 151; wherein, in a direction perpendicular to the plane of the substrate 11, at least some of the second vias 151 overlap with the corresponding first vias 131, or/and at least some of the second vias 151 are staggered with the first vias 131.

For example, in a direction perpendicular to the plane where the substrate 11 is located, at least a portion of the second via holes 151 is overlapped with the corresponding first via holes 131 .

In some other examples, at least a portion of the second via holes 151 and the first via holes 131 are offset from each other.

In some embodiments, as shown in Figures 7 and 11, the number of first vias 131 is the same as the number of second vias 151. Figures 7 and 11 illustrate that in a direction perpendicular to the plane where the substrate 11 is located, the plurality of second vias 151 and the plurality of first vias 131 are staggered or overlapped.

In the example of FIG. 7 , the number of the first via holes 131 is the same as the number of the second via holes 151; in a direction perpendicular to the plane where the substrate 11 is located, the plurality of second via holes 151 and the plurality of first via holes 131 are overlapped, so that the material thickness of the metal layer or the conductive layer is very large at the second via holes 151 and the first via holes 131, thereby enhancing the ability to resist water vapor penetration and water vapor corrosion.

In the example of FIG11 , the number of the first via holes 131 is the same as the number of the second via holes 151; in a direction perpendicular to the plane of the substrate 11, the plurality of second via holes 151 and the plurality of first via holes 131 are staggered, as shown in FIGS. 11 and 12 . When corrosion occurs at a second via hole 151 , since the first via hole 131 adjacent to the corrosion is covered by the second insulating layer 13 , the second insulating layer 13 has a good water vapor barrier effect, and the second insulating layer 13 protects the first via hole 131 , thereby preventing water vapor from reaching the first via hole 131 .

Furthermore, the second insulating layer 16 is made of inorganic material, which can better block water vapor.

It should be noted that, in the present application, in a direction perpendicular to the plane where the substrate 11 is located, the overlapping arrangement of two structures means that the orthographic projections of the two structures on the substrate 11 at least partially overlap. For example, in a direction perpendicular to the plane where the substrate 11 is located, the second via 151 and the first via 131 are overlapped, which means that the orthographic projection of the second via 151 (which may refer to the area included by the edge of the second via 151) on the substrate 11 at least partially overlaps with the orthographic projection of the first via 131 (which may refer to the area included by the edge of the first via 131) on the substrate 11.

It should be noted that, in the present application, in the direction perpendicular to the plane where the substrate 11 is located, the staggered arrangement of two structures means that the orthographic projections of the two structures on the substrate 11 do not overlap. For example, in the direction perpendicular to the plane where the substrate 11 is located, the second via 151 and the first via 131 are staggered, which means that the orthographic projection of the second via 151 (which may refer to the area included by the edge of the second via 151) on the substrate 11 does not overlap with the orthographic projection of the first via 131 (which may refer to the area included by the edge of the first via 131) on the substrate 11.

In some embodiments, as shown in FIG. 13 , the number of first vias 131 is less than the number of second vias 151 ; in a direction perpendicular to the plane of the substrate 11 , the first vias 131 are overlapped with the corresponding second vias 151 , and some of the second vias 151 are staggered with the first vias 131 .

As shown in Figures 13 and 14, the second via 151 includes the same number of first sub-vias 1511 as the first via 131, and at least one second sub-via 1512. In the first direction Y, the first sub-vias 1511 are overlapped with the corresponding first vias 131, and the second sub-vias 1512 and the first vias 131 are staggered.

As shown in Figures 13 and 14, when a first sub-via 1511 is corroded, the signal can continue to be connected or transmitted through the second sub-via 1512 adjacent thereto, so that the total resistance of the first routing 121 and the second routing 161 after the corrosion failure remains unchanged, or the total resistance of the first routing 121 and the second routing 161 after the corrosion failure increases less.

In some embodiments, as shown in FIG. 15 , the number of first vias 131 is greater than the number of second vias 151 ; in a direction perpendicular to the plane of the substrate 11 , the second vias 151 are overlapped with the corresponding first vias 131 , and some of the first vias 131 and the second vias 151 are staggered.

As shown in Figures 15 and 16, the first via 131 includes the same number of third sub-vias 1311 as the second via 151, and at least one fourth sub-via 1312. In the first direction Y, the third sub-vias 1311 are overlapped with the corresponding second vias 151, and the fourth sub-vias 1312 and the second vias 151 are staggered.

As shown in Figures 15 and 16, when severe corrosion occurs, when a second via 151 and a corresponding third sub-via 1311 are corroded, the signal can continue to be connected or transmitted through the fourth sub-via 1312 adjacent thereto, so that the total resistance of the first routing 121 and the second routing 161 after corrosion failure increases less.

In some embodiments, the extending direction of the connection trace 141 is consistent with the extending direction of the first trace 121 , and one connection trace 141 corresponds to a plurality of first vias 131 .

In some other embodiments, the connection traces 141 are block-shaped or island-shaped, and one connection trace corresponds to at least three first through holes 131 and at least three second through holes 151, so as to prevent corrosion and reduce resistance.

In some embodiments, the array substrate 100 includes a plurality of thin film transistors, and at least one of a pixel electrode and a common electrode;

The first metal layer 12 also includes a gate of the thin film transistor;

The first insulating layer 13 is a gate insulating layer;

The second metal layer 14 also includes the source and drain of the thin film transistor;

The third metal layer 16 also includes a pixel electrode or a common electrode.

For example, the array substrate 100 includes a plurality of thin film transistors, and the pixel electrodes and the common electrodes are used to drive the liquid crystal molecules to rotate and display images. The array substrate 100 includes the pixel electrodes, or the array substrate 100 includes the pixel electrodes and the common electrodes, and the pixel electrodes are electrically connected to the corresponding thin film transistors.

For example, the first metal layer 12 simultaneously forms the first wiring 121 and the gate of the thin film transistor, and the first wiring 121 and the gate of the thin film transistor are arranged in the same layer and the same material. The second metal layer 14 simultaneously forms the connecting wiring 141 and the source and drain of the thin film transistor, and the connecting wiring 141 and the source and drain of the thin film transistor are arranged in the same layer and the same material. The third metal layer 16 simultaneously forms the second wiring 161 and the pixel electrode, and the second wiring 161 and the pixel electrode are arranged in the same layer and the same material, or the third metal layer 16 simultaneously forms the second wiring 161 and the common electrode, and the second wiring 161 and the common electrode are arranged in the same layer and the same material. By arranging the first wiring, the first insulating layer, the connecting wiring 141, the second insulating layer 15 and the second wiring 151 in the same layer with the various functional layers or functional wiring of the array, the manufacturing process steps of the array substrate 100 are reduced, and the first wiring, the connecting wiring 141 and the second wiring 151 can also well provide electrical signals of various functions in the array substrate 100.

In some embodiments, the array substrate 100 includes a display area and a non-display area surrounding the display area, and the first wiring 121 , the connecting wiring 141 , and the second wiring 161 are all located in the non-display area.

For example, in the non-display area, the second wiring 161 and the like are more easily exposed to water vapor, and the corrosion problem in the non-display area is more serious. The above-mentioned embodiment is arranged in the non-display area, which can greatly improve the performance and yield of the display panel.

For example, the first wiring 121 , the connecting wiring 141 , and the second wiring 161 may be used to provide a clock signal of a gate driving circuit, a start signal of a gate driving circuit, a common signal of a common electrode in a display area, and the like.

In the present application, a method for manufacturing an array substrate is also provided. Any of the above array substrates 100 can be manufactured using the method for manufacturing the array substrate. The method for manufacturing the array substrate includes steps: S10, S20, S30, S40, S50 and S60.

S10, providing a substrate 11.

S20 , forming a first metal layer 12 on the substrate 11 , and patterning the first metal layer 12 to form at least one first wiring 121 .

S30 , forming a first insulating layer 13 on the first metal layer 12 , and patterning the first insulating layer 13 to form at least one first via hole 131 .

S40 , forming a second metal layer 14 on the first insulating layer 13 , patterning the second metal layer 14 to form at least one connecting wire 141 , and connecting wire 141 is connected to the corresponding first wire 121 through the first via 131 .

S50 , forming a second insulating layer 15 on the second metal layer 14 , and patterning the second insulating layer 15 to form at least one second via hole 151 .

S60 , forming a third metal layer 16 on the second insulating layer 15 , and patterning the third metal layer 16 to form at least one second wiring 161 , and the second wiring 161 is connected to the corresponding connecting wiring 141 through the second via 151 .

The present application also provides a display panel, which includes the array substrate 100 of any one of the above items.

By way of example, the display panel may be a liquid crystal display panel, but is not limited thereto.

For example, when the display panel is a liquid crystal display panel, the display panel may further include a color filter substrate disposed opposite to the array substrate 100 , and the display panel may further include a liquid crystal layer disposed between the color filter substrate and the array substrate 100 .

It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Although the preferred embodiments of this specification have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of this specification.

Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalents, this specification is also intended to include these modifications and variations.

Claims (11)

1. An array substrate, comprising: substrate; A first metal layer is disposed on one side of the substrate, wherein the first metal layer includes at least one first trace; A first insulating layer, disposed on a side of the first metal layer away from the substrate, the first insulating layer comprising at least one first via hole; A second metal layer is disposed on a side of the first insulating layer away from the substrate, the second metal layer comprising at least one connecting trace; A second insulating layer, disposed on a side of the second metal layer away from the substrate, the second insulating layer comprising at least one second via hole; A third metal layer is disposed on a side of the second insulating layer away from the substrate, and the third metal layer includes at least one second trace; Wherein, in a direction perpendicular to the plane where the substrate is located, the first via hole and the first routing line are arranged to overlap, and the connecting routing line is connected to the first routing line through the first via hole; Wherein, in a direction perpendicular to the plane where the substrate is located, the second via hole and the connecting wire are arranged to overlap, and the second wire is connected to the connecting wire through the second via hole; The second metal layer includes a material having higher corrosion resistance than that of the third metal layer. 2 . The array substrate according to claim 1 , wherein the second metal layer comprises at least two metal sub-layers, and at least one of the metal sub-layers of the second metal layer has higher corrosion resistance than that of the third metal layer. 3 . The array substrate according to claim 1 , wherein a material of the second metal layer comprises at least one of titanium, chromium and nickel. 4 . The array substrate according to claim 1 , wherein a material of the third metal layer comprises at least one of transparent conductive metal oxide, copper and aluminum. 5. The array substrate according to any one of claims 1 to 4, characterized in that the first insulating layer comprises a plurality of the first via holes, and the second insulating layer comprises a plurality of the second via holes; Wherein, in a direction perpendicular to the plane where the substrate is located, at least part of the second via holes is arranged overlapping with the corresponding first via holes; or/and At least part of the second via holes is staggered with the first via holes. 6. The array substrate according to claim 5, characterized in that the number of the first via holes is the same as the number of the second via holes; In a direction perpendicular to the plane where the substrate is located, the plurality of second via holes and the plurality of first via holes are all staggered or overlapped. 7. The array substrate according to claim 5, wherein the number of the first via holes is less than the number of the second via holes; In a direction perpendicular to the plane where the substrate is located, the first via holes are all overlapped with the corresponding second via holes, and some of the second via holes are staggered with the first via holes. 8. The array substrate according to claim 5, wherein the number of the first via holes is greater than the number of the second via holes; In a direction perpendicular to the plane where the substrate is located, the second via holes are all overlapped with the corresponding first via holes, and some of the first via holes are staggered with the second via holes. 9. The array substrate according to any one of claims 1 to 4, characterized in that the array substrate comprises a plurality of thin film transistors, and at least one of a pixel electrode and a common electrode; The first metal layer also includes a gate of the thin film transistor; The first insulating layer is a gate insulating layer; The second metal layer also includes a source and a drain of the thin film transistor; The third metal layer further includes the pixel electrode or the common electrode. 10. The array substrate according to any one of claims 1 to 4, characterized in that the array substrate comprises a display area and a non-display area located around the display area, and the first wiring, the connecting wiring and the second wiring are all located in the non-display area. 11. A display panel, comprising the array substrate according to any one of claims 1 to 10.