CN117973301A - Circuit manufacturing method, device and electronic equipment - Google Patents

Abstract

The present application provides a circuit manufacturing method, device and electronic device, which relate to the field of integrated circuits. When designing a circuit, standard cells are placed in their respective corresponding working areas according to different types to improve resource utilization, rather than dividing a unified sacrificial area for all standard cells, and prohibiting the placement of standard cells in the sacrificial area. The method includes: obtaining the type and position information of the standard cell, the position information includes an angle and a distance, the distance is the distance from the center of the standard cell to the center of the through silicon via TSV, and the angle is the angle between the center of the TSV and the center of the standard cell and the horizontal line of the center of the standard cell. Determine whether the standard cell is located in the working area based on the position information and a pre-set position information table. If it is not in the working area, obtain the position information of the standard cell after the updated position and judge again until the standard cell falls into the working area.

Description

Circuit manufacturing method and device and electronic equipment

Technical Field

The present application relates to the field of integrated circuits, and in particular, to a circuit manufacturing method, a circuit manufacturing device, and an electronic device.

Background

With the continuous progress of the nano-scale manufacturing process of chips, the transistor density of the wafer gradually approaches to the physical limit on the two-dimensional plane, so that the density and performance of the integrated package are more demanded. A three-dimensional packaging method comprises the following steps: the wafers are vertically integrated based on through silicon via (through silicon via, TSV) technology and stacking. Three-dimensional packages can achieve smaller size, higher bandwidth, lower latency, and higher performance. The TSV technology is a novel interconnection technology used in high-density microelectronic packaging, which prepares micro-holes in a silicon wafer by etching, then fills copper in the micro-holes by electroplating, anneals at high temperature, and thins the silicon wafer to form micro-through holes. The chip upper and lower surface electrical connections are combined into the package structure by a rewiring process.

In the above-described processes such as electroplating and annealing, the use of TSV technology tends to create high stresses in electroplated copper materials. In addition, three-dimensional packages based on TSV technology are also required to withstand multiple stress coupling effects such as temperature, humidity, current/voltage, vibration, etc. during their manufacture and use, which affect the mobility and threshold voltage of the surrounding standard cells, thereby failing the flip characteristics of the standard cells. The prior art generally defines a sacrificial region outside the process clearance area of the TSV according to process manufacturing rules. The process clearance area is an area planned according to the process manufacturing rules in which standard cells are prohibited from being set. The sacrificial region is arranged outside the process clearance area and is a region planned according to the principle that the influence of the TSV on the standard unit is reduced along with the increase of the distance. Since the standard cell is disposed outside the sacrificial region, the distance between the TSV and the standard cell increases, so that the influence of the TSV stress can be reduced.

However, since the areas where different standard cells can work or fail are not the same, the same sacrifice area is defined for different standard cells, and the prohibition of setting any standard cell in the sacrifice area causes a problem of waste of design resources.

Disclosure of Invention

The embodiment of the application provides a circuit manufacturing method, a circuit manufacturing device and electronic equipment, which are used for solving the problem of design resource waste caused by the fact that TSV stress delimits a uniform sacrifice area around a TSV.

In order to achieve the above purpose, the application adopts the following technical scheme:

In a first aspect, a method of fabricating a circuit is provided, the method comprising: the method comprises the steps of obtaining type and position information of a standard cell, wherein the position information comprises angles and distances, the distances are distances from the center of the standard cell to the center of a Through Silicon Via (TSV), and the angles are included angles between a center connecting line of the TSV from the center of the TSV to the standard cell and a center horizontal line of the standard cell; according to the type, the distance, the angle and a preset position information table, determining whether the standard unit is in the working area, wherein the position information table stores boundary information of working areas of standard units of different types, the boundary information comprises a first included angle and a first distance, the first included angle is an included angle between a central connecting line of the TSV from the center of the standard unit to the central horizontal line of the standard unit, and the first distance is a minimum working distance from the center of the standard unit corresponding to the first included angle to the center of the TSV. And comparing the angle and the distance of the standard unit with the first included angle and the first distance stored in the position information table corresponding to the standard unit of the type, if the distance of the standard unit is larger than the first distance corresponding to the first included angle matched with the angle, determining that the standard unit is positioned in the working area, and if the standard unit is positioned outside the working area, acquiring the position information of the standard unit after the position is updated until the standard unit is positioned in the working area.

In the scheme provided by the embodiment of the application, the boundary information of the working areas of the standard units of different types is stored in the position information table instead of uniformly defining the sacrifice area for all the standard units, so that whether the standard units are in the working areas or not is determined by acquiring the position information of the standard units and the boundary information of the working areas of the standard units in the position information table, if the standard units are not in the working areas, the position information after the standard units are updated is acquired and judged again until the standard units are in the corresponding working areas, and compared with the traditional scheme of defining the sacrifice areas and prohibiting the placement of any type of standard units in the sacrifice areas, the scheme provided by the embodiment of the application sets the working areas for the standard units of different types respectively, so that when designing a circuit layout, the different standard units are respectively arranged in the respective working areas, thereby realizing the efficient utilization of resources.

In one possible implementation manner, if the standard unit is outside the working area, the method further includes, after obtaining the location information after the standard unit updates the location until the standard unit is inside the working area: determining whether the delay of the standard unit belongs to a set range or not based on a preset standard unit time sequence table according to the position information; and if the time delay is out of the set range, acquiring the position information of the standard unit after updating the position until the time delay is in the set range.

In the embodiment of the application, the working state of the standard unit in the working area meets the design requirement, but the position of the standard unit is changed, the sequence of signal transmission of the metal interconnection line connected with a plurality of standard units is changed according to the different positions, different positions have different delays, whether the position of the standard unit meets the sequence of signal transmission, namely the delay requirement, is determined through the position of the standard unit and a standard unit time sequence table, and if the position of the standard unit does not meet the sequence, the position information after the position of the standard unit is updated is acquired and judged again. Until the time delay of the standard units is within a set range, ensuring that the signal transmission time sequence of each standard unit meets the requirement.

In one possible embodiment, before determining whether the standard cell is within the workspace according to the type, distance, angle, and location information table, the method further comprises: a table of location information is determined. The position information table stores the range of the working area corresponding to different types of standard units, and is established in advance, so that each standard unit can be placed in the working area according to the position information table when the circuit is manufactured.

In one possible implementation, determining the location information table includes: invoking a device model of any type of standard unit representing TSV stress, and establishing a simulation structure of the standard unit with the TSV; the model is used for indicating the corresponding relation between the delay and the turnover characteristic of the transistor in the standard unit and the position information of the standard unit; the position of the standard unit is adjusted, the first distance corresponding to each first included angle of the standard unit is determined, and the first distance corresponding to each first included angle and the first included angle is determined to be the boundary information of the working area of the standard unit; and establishing a position information table according to the type and the boundary information of the working area.

In one possible implementation, adjusting the position of the standard cell, and determining the first distance corresponding to each first included angle of the standard cell includes: setting a first included angle of the standard unit as an initial angle, setting a distance from the center of the TSV as an initial distance, and increasing the distance from the center of the standard unit to the center of the TSV by a set distance step until the minimum working distance that the delay and turnover characteristics meet the preset requirements under the initial angle is determined, wherein the initial distance is the radius of a process clearance area; and adjusting the first included angle of the standard unit by the set angle step length, and determining that the delay and turnover characteristics meet the minimum working distance required by the preset requirement after the first included angle is adjusted until the first included angle of the standard unit is adjusted to a final angle, wherein the sum of the final angle and the initial angle is 2 pi. The boundary of the working area under the angle is determined by a method of increasing the distance according to the step length by fixing the angle, then the angle is changed according to the step length, and the boundary of the working area under the new angle is determined by a method of increasing the distance according to the step length after fixing the angle until the end angle is reached, so that the minimum working distance of the delay and the turnover characteristics of the standard units under each angle meeting the requirements can be determined, namely the boundary information of the working area of the standard units is determined.

In one possible implementation, determining whether the standard cell is in the workspace according to the type, distance, angle, and a predetermined table of location information includes: determining boundary information of a working area corresponding to the type in the position information table according to the type of the standard unit; determining a first distance corresponding to a first included angle matched with the angle in boundary information of the working area according to the angle; if the distance is greater than or equal to the first distance, the standard cell is within the working area. And determining standard units of all types inside the working area according to the judging method. When the circuit layout is manufactured, different standard units are respectively arranged in the respective working areas, so that the efficient utilization of resources can be realized.

In one possible implementation manner, before determining whether the delay of the standard cell is within the set range based on the preset standard cell timing table according to the position information after updating the position, the method further includes: a standard cell timing schedule is determined. Before a circuit is manufactured, the corresponding time delay of the standard units at each position is determined, the standard unit time sequence table is determined, the time sequence of each standard unit can be ensured to meet the requirement according to the standard unit time sequence table when the circuit is designed, and the circuit design efficiency is improved.

In one possible implementation manner, the method for creating the standard time schedule includes: invoking a device model of any type of standard unit representing TSV stress, and establishing a simulation structure of the standard unit with the TSV; the standard unit model is used for indicating the corresponding relation between the time delay of the standard unit of the type and the position information of the standard unit; determining the delay of a standard unit under the influence of TSVs at the current position, and determining the ratio of the delay to the initial delay of the standard unit as an influence factor at the position, wherein the initial delay refers to the delay of the standard unit under the influence of no TSVs; and adjusting the position of the standard unit, determining an influence factor after adjusting the position, and storing the corresponding relation between the position and the influence factor corresponding to the position into a standard unit time sequence table.

In one possible implementation manner, according to the location information after updating the location, determining whether the delay of the standard cell is within the set range based on the preset standard cell timing table includes: determining an influence factor according to the position information and the standard unit time sequence table; multiplying the influence factor by the initial delay of the standard unit to determine the delay of the standard unit under the influence of the TSV; and determining whether the delay of the standard unit under the influence of the TSV belongs to a set range. The set range may be a time sequence range based on a sequence relation of signal flow directions required to be satisfied by a specific function of the digital chip, for example, the delay sizes of different standard units are determined according to the relation of signal flow directions of the different standard units.

In a second aspect, a circuit design apparatus is provided, the apparatus includes an acquisition module and a processing module, the acquisition module is configured to acquire type and position information of a standard cell, the position information includes an angle and a distance, the distance is a distance from a center of the standard cell to a center of a through silicon via TSV, and the angle is an included angle between a center-to-center connection line of the TSV to the standard cell and a center horizontal line of the standard cell. The processing module is used for determining whether the standard unit is positioned in the working area according to the type, the distance, the angle and a preset position information table, wherein the position information table stores boundary information of the working areas of different types of standard units, and the boundary information comprises a first included angle and a first distance of the standard units. The first included angle is: an included angle between a central connecting line from the center of the through silicon via to the standard unit and a central horizontal line of the standard unit; the first distance is the minimum working distance from the center of the standard unit corresponding to the first included angle to the center of the through silicon via; and if the standard unit is positioned outside the working area, the acquisition module is also used for acquiring the position information of the standard unit after the position is updated until the standard unit is positioned in the working area.

In a third aspect, there is provided a computer readable storage medium having stored therein computer instructions which, when executed by a processor, enable the processor to perform a method as provided by any one of the embodiments of the first aspect.

In a fourth aspect, there is provided a chip storing computer instructions which, when executed by a processor, implement a method as provided in any of the embodiments of the first aspect.

In a fifth aspect, there is provided an electronic device comprising a processor and a memory, wherein the processor is configured to execute computer instructions stored in the memory to implement a method as provided by any of the embodiments of the first aspect.

Technical effects concerning the second aspect, the third aspect, the fourth aspect, and the fifth aspect may be referred to the relevant description of the first aspect described above.

Drawings

Fig. 1 is a schematic diagram of a three-dimensional package structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of another three-dimensional package structure according to an embodiment of the present application;

Fig. 3 is a schematic diagram of a correspondence between input and output of a standard cell and time under the influence of TSV according to an embodiment of the present application;

Fig. 4 is a schematic diagram of a standard cell noise margin variation under the influence of a TSV according to an embodiment of the present application;

Fig. 5 is a schematic diagram of a standard cell with TSV according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

Fig. 7 is a schematic flow chart of a circuit manufacturing method according to an embodiment of the application;

FIG. 8 is a schematic diagram of a signal flow according to an embodiment of the present application;

FIG. 9 is a schematic flow chart of another circuit manufacturing method according to an embodiment of the present application;

FIG. 10 is a schematic flow chart of another circuit manufacturing method according to an embodiment of the present application;

FIG. 11 is a schematic flow chart of another circuit manufacturing method according to an embodiment of the present application;

fig. 12a is a schematic diagram showing the effect of TSV stress on transistor mobility inside a standard cell according to an embodiment of the present application;

FIG. 12b is a schematic diagram illustrating the effect of TSV stress on the variation of the threshold voltage of the transistors inside the standard cell according to the embodiment of the present application;

FIG. 13a is a schematic diagram illustrating the effect of TSV stress on the saturation current of transistors in a standard cell according to an embodiment of the present application;

FIG. 13b is a schematic diagram illustrating the effect of TSV stress on the threshold voltage of the transistors inside the standard cell according to the embodiment of the present application;

FIG. 14a is a schematic delay diagram of a standard cell according to an embodiment of the present application;

FIG. 14b is a schematic diagram of flip characteristics of a standard cell according to an embodiment of the present application;

FIG. 15 is a schematic flow chart of another circuit manufacturing method according to an embodiment of the present application;

FIG. 16 is a schematic flow chart of another circuit manufacturing method according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a standard cell layout according to an embodiment of the present application;

FIG. 18 is a schematic diagram of another standard cell layout according to an embodiment of the present application;

FIG. 19 is a schematic diagram of a layout of two standard cells according to an embodiment of the present application;

fig. 20 is a functional block diagram of a circuit design apparatus according to an embodiment of the present application.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature.

Furthermore, in the present application, the terms of orientation such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined with respect to the orientation in which the components in the drawings are schematically disposed, and it should be understood that these directional terms are relative terms, which are used for descriptive and clarity with respect thereto, and which may be correspondingly altered in response to changes in the orientation in which the components in the drawings are disposed.

In the present application, unless explicitly specified and limited otherwise, the term "connected" is to be construed broadly, and for example, "connected" may be either fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium.

Packaging is the mounting of a housing to a chip integrated circuit, which serves several functions, such as securing, sealing, protecting the chip, and enhancing heat dissipation. The package also serves as a bridge for communicating the internal and external circuits of the chip, so that the package is divided into an internal package and an external package. With the continuous progress of the nano-scale process of chip, the transistor density of the wafer on the two-dimensional plane gradually approaches to the physical limit, so that the density and performance of the integrated package are more required, and the three-dimensional package based on the through silicon via (through silicon via, TSV) technology is generated.

TSV technology is formed by etching a via that penetrates longitudinally through the substrate and filling the via with a conductive material (e.g., copper). The TSVs may be used to provide electrical connections to semiconductor circuitry on the back side of a semiconductor substrate to the opposite side of the substrate, or to semiconductor circuitry of stacked chips.

The three-dimensional package based on the TSV technology can stack chips with multiple functions in a single package body, so that the single package body can realize more functions; taking a chip as a memory as an example, a plurality of memory chips can be stacked in a single package body by adopting a three-dimensional package based on TSV technology, so that the multiplication of the storage capacity can be realized.

Fig. 1 shows a back to face (BtF) integration of a three-dimensional package based on TSV technology. Meaning that the front side of the first device wafer 001 is bonded or otherwise connected to the back side of the second device wafer 003. The first device wafer 001 has a first substrate 002 with a back surface, and through silicon vias 005 shown in fig. 1 have one end connected to the front side metal 006 inside the second device wafer 003 and the other end connected to the back side metal 007 above the second substrate 004 of the second device wafer 003.

Fig. 2 shows a face-to-face (FtF) integration of three-dimensional packages based on TSV technology. That is, the front side of the first device wafer 011 is coupled to the front side of the second device wafer 013. The first device wafer 011 has a first substrate 012 on its front surface and the second device wafer 013 has a second substrate 014 on its back surface, and through-silicon vias 015 shown in fig. 2 have one end connected to front side metal 016 inside the second device wafer 013 and the other end connected to back side metal 017 located below the second substrate 014 of the second device wafer 013. The resulting wafer stack does not require a different integration process than a standard wafer, i.e., for the other layers of the multi-layer stack. The main advantage of this process flow is that it does not require the handling of thin wafers.

In theory, three-dimensional packaging based on TSV technology can enable chips to be directly interconnected, signal transmission is faster, and interference is smaller. However, the heat residue caused by the high temperature treatment during the TSV manufacturing process and the multi-stress coupling effect such as temperature, humidity, current, voltage, vibration and the like are required to be born in the use process, which may cause that the standard cells arranged around the TSV may be affected by the TSV and may not work normally. The standard cell (STANDARD CELL, STD cell) is a standard device formed of a transistor, for example, a gate circuit capable of providing a boolean logic function, a device having a memory function, or the like. The standard cell may be a general logic gate such as an AND gate AND, an OR gate OR, an NOT gate NOT, a NAND gate NOR, a NOR gate NOR, etc., OR a flip-flop, a latch, etc.

In an embodiment of the present application, the transistors may be metal-oxide-semiconductor field effect transistors (MOSFETs) including N-type metal-oxide-semiconductor field effect transistors (NMOS) and P-type metal-oxide-semiconductor field effect transistors (PMOS) wherein NMOS is also referred to as N-type transistors and PMOS is also referred to as P-type transistors. The transistor includes a source (source), a drain (drain), and a gate (gate), and can be turned on or off by controlling the level of the gate of the input transistor. When the transistor is turned on, the source electrode and the drain electrode are turned on to generate an on current, and when the grid electrode level of the transistor is different, the magnitude of the on current generated between the source electrode and the drain electrode is also different; when the transistor is turned off, the source electrode and the drain electrode are not turned on, and no current is generated. In addition, the N-type transistor is conducted when the level of the control end is high, the first end and the second end are conducted, and conduction current is generated between the first end and the second end; the N-type transistor is turned off when the level of the control end is low, the first end and the second end are not turned on, and no current is generated. The P-type transistor is conducted when the level of the control end is low, and the first end and the second end are conducted to generate conducting current; the P-type transistor is turned off when the level of the control terminal is high, the first terminal and the second terminal are not turned on, and no current is generated.

Fig. 3 is a schematic diagram showing a correspondence between input and output of a standard cell and time under the influence of TSV, the abscissa is time, the ordinate is input or output (voltage), the upper diagram in fig. 3 is a schematic diagram showing the correspondence between input and time of the standard cell, and the lower diagram is a schematic diagram showing the correspondence between output of the standard cell and time. Taking a standard unit as an NOT gate as an example, in general, a high-level signal is input to the standard unit, and a low-level signal is output by the standard unit correspondingly; the low level signal is input to the standard cell, and the high level signal is output to the standard cell, and the corresponding change relation between the input and the output is called the flip characteristic of the standard cell.

The abscissa shown in fig. 3 is divided into six sections by T ₁、T₂、T₃、T₄、T₅ and T ₆, and the input of the standard cell is high in the section 0 to T ₁, the input of the standard cell is low in the section T ₁～T₄, and the input of the standard cell is high in the section T ₄～T₆. In general, the output of the standard cell should be low in the interval 0 to T ₁, high in the interval T ₁～T₄, and high in the interval T ₄～T₆.

However, since the stress of the TSV may affect the surrounding standard cells, the mobility of the standard cells may fluctuate, and thus the saturation current of the standard cells may be affected, resulting in a delay in the inversion of the standard cells, as shown in the lower graph of fig. 3, at the time T ₂, the input of the standard cells has been changed from high level to low level, and the output of the standard cells is not changed from low level to high level until T ₃. The time period from T ₂ to T ₃ is the time delay of the inversion of the standard cell. The inversion of the output signal has a delay with respect to the variation of the input signal, and when the saturation current of the standard cell becomes small due to the influence of the TSV, the delay of the standard cell increases.

The threshold voltage of the transistor refers to the pinch-off voltage of the depletion transistor or the turn-on voltage of the enhancement transistor, and when the transistor is depletion, the threshold voltage is a negative value and is smaller than the pinch-off voltage of the threshold voltage transistor; when the transistor is enhanced, the threshold voltage is positive and the transistor is turned on, so that the standard cell can only operate if the input voltage is greater than the threshold voltage.

Variations in transistor threshold voltage can affect the noise margin of standard cells. The noise margin refers to the maximum noise amplitude allowed to ensure that the subsequent stage can operate normally in the case where the output quality of the previous stage is the worst. The noise margin can reflect the anti-interference performance of the standard unit, and the larger the noise margin is, the stronger the anti-interference performance is.

Fig. 4 is a diagram showing the variation of the noise margin of the standard cell under the influence of the TSV. Taking high noise as an example, the transistor is high when the output of the previous stage is greater than V ₂, denoted as "1" output, the output range is V ₂～V₁, the input of the next stage is high when the input is greater than V ₅, denoted as "1" input, and V ₅ is the threshold voltage for the transistor.

Under the influence of TSV stress, the noise margin is the difference between the minimum value of the output of the previous stage and the threshold voltage of the transistor of the next stage, which is denoted as V ₃, and then V ₃ is the difference between V ₂ and V ₅. Then for the transistor of the next stage, the "1" input is the difference between the maximum value of the previous stage output and the threshold voltage of the next stage transistor, noted as V ₇, without being affected by TSV stress, then V ₇ is the difference between V ₁ and V ₅.

The threshold voltage of the transistor is raised from V ₅ to V ₆ under the influence of the TSV stress, and in this case, the noise margin is denoted as V ₄,V₄ as the difference between V ₂ and V ₆, and since V ₆ is greater than V ₅, the noise margin is reduced under the influence of the TSV stress. The range of "1" inputs also decreases from V ₇ to V ₈, where V ₈ is the difference between V ₁ and V ₆.

Therefore, compared with the noise margin V ₃ of the standard cell under the influence of the TSV, the noise margin V ₄ of the standard cell under the influence of the TSV is smaller, and the anti-interference capability is poorer.

In order to avoid the abnormal operation of the standard cell caused by the influence of the TSV stress on the standard cell, the embodiment of the application provides a possible implementation manner, and a sacrificial region is arranged outside a process clearance zone (KoZ). As shown in fig. 5, a sacrificial region 008 is defined outside KoZ a 009 according to the process manufacturing rules. The process clearance zone 009 is an area outside the TSV planned according to the process manufacturing rules in which the standard cell 010 is prohibited from being set. The sacrificial region 008 is a region reserved for estimating factors such as the change amplitude of carrier mobility and the like affected by the TSV stress through numerical simulation or experiments, because the influence of the TSV stress on the standard cell 010 is positively correlated with the distance, and the farther the standard cell 010 is from the TSV, the smaller the influence of the stress is. So, the sacrificial region is defined outside KoZ, the standard cell 010 is forbidden to be arranged in the sacrificial region 008, and the standard cell 010 can be arranged outside the sacrificial region 008, so that the influence of the TSV stress on the standard cell is reduced by increasing the distance.

While the placement of the sacrificial region at KoZ may circumvent the effects of TSV stress on standard cell mobility and threshold voltage, this design places all standard cells outside the same sacrificial region, and does not allow any standard cells to be placed within the sacrificial region. In practice, however, the areas in which different standard cells can operate within the sacrificial region are not identical, for example, assuming that there are two different types of standard cells: and the gate and the or gate cannot work normally when the distance TSV is d ₁, but the or gate can work normally when the distance TSV is d ₁, so that the boundary of the area where the gate and the or gate cannot work outside KoZ is different, the area of the circuit is increased due to the fact that all standard units are uniformly arranged outside the same sacrifice area to avoid the influence of the stress of the TSV, and the length of a metal interconnection line connected with the standard units is increased, so that a large amount of resources are wasted.

The circuit manufacturing method provided by the embodiment of the application can be applied to an electronic device, for example, referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device 020 provided by the embodiment of the application, and as shown in fig. 6, the electronic device 020 may include a processor 021, a communication line 022 and a communication interface 023.

The electronic device 020 may also include memory 024, for example. The processor 021, the memory 024 and the communication interface 023 can be connected by a communication line 022. The processor 021 may be a central processing unit (central processing unit, CPU), a general-purpose processor, a digital signal processor (DIGITAL SIGNAL processing, DSP), a microprocessor, a microcontroller, a programmable logic device, or any combination thereof. The processor 021 may also be other means for performing processing functions, such as a circuit, device, or software module.

Communication lines 022 for communicating information between the components of the electronic device 020.

Communication interface 023 for communicating with other devices or communication networks. The communication network may be an ethernet, a radio access network (radio access network, RAN), a wireless local area network (wireless local area networks, WLAN), or the like. Communication interface 023 may be an interface circuit, pin, radio frequency module, transceiver, or any device capable of enabling communication.

Memory 024 for storing instructions. The instructions may be a computer program for executing the circuit making method provided by the embodiment of the present application. The memory 024 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and/or instructions, a random access memory (random access memory, RAM) or other type of dynamic storage device capable of storing information and/or instructions, an electrically erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ-only memory, EEPROM), a compact disc read-only memory (compact cisc read-only memory, CD-ROM) or other optical disc storage, magnetic disc storage medium or other magnetic storage device, optical disc storage including compact disc, laser disc, optical disc, digital versatile disc, or blu-ray disc, etc.

It should be noted that, the memory 024 may exist separately from the processor 021, or may be integrated with the processor 021. Memory 024 may be used to store instructions or program code or some data, etc. The memory 024 may be located inside the electronic device 020 or outside the electronic device 020, and is not limited. A processor 021 for executing instructions stored in the memory 024 to implement the circuit manufacturing method according to the following embodiment of the present application.

In one example, the processor 021 may include one or more CPUs, such as CPU0 and CPU1 in fig. 6.

As an alternative implementation, electronic device 020 includes multiple processors, e.g., processor 027 may be included in addition to processor 021 in fig. 6.

As an alternative implementation, electronic device 020 also includes an output device 025 and an input device 026. By way of example, input device 026 may be a keyboard, mouse, microphone, or joystick, and output device 025 may be a display screen, speaker, or the like. It should be noted that the electronic device 020 may be a desktop computer, a portable computer, a network server, a mobile phone, a tablet computer, a wireless terminal, an embedded device, a chip system, or an electronic device having a similar structure in fig. 6. Further, the constituent structure shown in fig. 6 does not constitute a limitation of the processing apparatus, and the electronic device 020 may include more or less components than those shown in fig. 6, or may combine some components, or may be a different arrangement of components, in addition to those shown in fig. 6.

Based on the electronic device 020 shown in fig. 6, an embodiment of the present application provides a circuit manufacturing method for improving the problem of resource waste caused by the design of the sacrificial area in the prior art. For example, the circuit manufacturing method provided by the embodiment of the application can be applied to a processing device or electronic equipment capable of realizing three-dimensional package design. Specifically, part or all of the workflow of the circuit manufacturing method provided by the embodiment of the application can be implemented through an electronic design automation (electronic design automation, EDA) tool or other layout design and layout simulation tools configured by electronic equipment, and the application is not limited in particular.

The method provided by the embodiment of the application is to confirm the boundary that each standard unit can work, divide different working areas for different standard units, and respectively arrange different standard units in the respective working areas to realize the efficient utilization of resources when designing a circuit layout.

Exemplary, with reference to fig. 7, fig. 7 is a schematic flow chart of a circuit manufacturing method according to an embodiment of the present application, where the circuit manufacturing method according to the embodiment of the present application includes:

s110: and obtaining the type and position information of the standard unit, wherein the position information comprises angles and distances.

The position information comprises a distance and an angle, wherein the distance is the distance from the center of the standard cell to the center of the TSV, and the angle refers to the included angle between the center connecting line of the TSV from the center of the standard cell and the center horizontal line of the standard cell. The standard units are divided into different types according to different internal structures, different standard unit structures of different types are different and affected by TSV stress, so that the areas where different standard units can work are different. Therefore, the working area of each standard cell is required to be determined, the type and the position information of each standard cell are firstly known, and in the practical application process, when a user sets the standard cell at a certain position by using a simulation tool or an EDA tool, parameters such as the type, the distance and the angle of the standard cell can be obtained by analyzing the type parameters of the standard cell and the relative positions of the standard cell and the TSV.

S130: and determining whether the standard unit is in the working area according to the type, the distance, the angle and a preset position information table.

The working area is an area where each standard unit can work normally in the sacrifice area, and in the area, the function of each standard unit meets the design requirement.

The position information table stores boundary information of working areas of different types of standard units, the boundary information comprises a first included angle and a first distance, the first included angle refers to an included angle between a central connecting line from the center of the TSV to the standard unit and a central horizontal line of the standard unit, and the first distance is a minimum working distance from the center of the standard unit corresponding to the first included angle to the center of the TSV. For example, when the angle is a, the minimum working distance that the standard cell can meet the requirement is d, then the point is the boundary corresponding to the angle a, when the angle is a, if the distance from the center of the standard cell to the center of the TSV is greater than d, then the standard cell can work normally, and if the distance is less than d, then the standard cell cannot work normally.

In addition, different types of standard cells have different structures, and the minimum working distances from the center of the corresponding standard cell to the center of the TSV are different. The location information table may store boundary information of the work areas corresponding to different types of standard cells.

After the type, the distance and the angle of the standard unit are determined, whether the standard unit is positioned in the working area or not is determined based on the distance and the angle of the standard unit and the boundary information of the working area corresponding to the standard unit stored in the position information table.

S150: and if the standard unit is positioned outside the working area, acquiring the position information of the standard unit after the position is updated until the standard unit is positioned in the working area.

When the position of the standard cell is outside the working area, for example, the distance from the standard cell to the TSV is relatively short, the standard cell cannot work normally, the designed circuit may not meet the design requirement, so that the position of the standard cell needs to be adjusted, the position of the standard cell is moved, the angle of the standard cell can be changed from the center of the standard cell to the center of the TSV in general, and the angle can be not changed in one case because the angle of the standard cell is positively related to the distance from the center of the standard cell to the center of the TSV due to the influence of the TSV; another way is to adjust the angle without changing the distance, or it is also possible to adjust both the angle and the distance.

After the position of the standard unit is adjusted, position information of the standard unit after the position is updated is obtained, whether the standard unit is positioned in the working area is judged again, if the standard unit is positioned in the working area, the position adjustment is stopped, and if the standard unit is still positioned outside the working area, the position of the standard unit can be adjusted again, and the standard unit is judged again until the standard unit is positioned in the working area.

The working boundary line of the standard unit in the area surrounded by the sacrifice area and KoZ is determined by a method of repeated multiple times and variable control, and the boundary line consists of innumerable minimum distances, and each minimum distance has a corresponding angle. Because standard cells are different in type, there is a working boundary for each type of standard cell. The area of the working boundary line facing the sacrifice area is the inside of the working area, and standard units are arranged in the area, so that the standard units can work normally. Standard cell placement in the working area still meets requirements such as latency and flip characteristics of standard cells relative to methods that prohibit placement of standard cells in the entire sacrificial area. However, the positions of the standard units may be originally divided into sacrifice areas, and the standard units are forbidden to be set, so that the scheme provided by the embodiment of the application can reduce the waste of design resources.

In the above example, whether the standard unit is located in the working area is determined based on the position of the standard unit and the pre-stored position information table, if the position of the standard unit is located outside the working area, the user may be prompted to change the position of the standard unit, and the position information of the standard unit after the position is updated is obtained, and then the standard unit is determined again until the standard unit is located in the working area where the standard unit can work normally. However, the foregoing examples have mentioned that the locations where the standard cells are disposed are different, and are affected by the stress of the TSVs, and the lengths of the metal interconnect lines connected to other standard cells are changed, and the delays of the standard cells are also different, resulting in a change in the timing of the digital chip.

The digital chip is connected by a plurality of standard units through metal connecting wires, has specific functions in design, and needs to ensure the accuracy of the sequence relation of signal flow direction in order to meet the specific requirements. Different standard cells have different delays at different locations, and these delays affect the precedence of the signal flow.

There is a range of timing sequences based on the precedence of signal flow directions that the specific functions of the digital chip need to satisfy. Referring to fig. 8, the digital chip is composed of a standard cell a, a standard cell B, and a standard cell C. The standard unit A is connected with the standard unit C through a metal connecting wire; the standard cell B is connected with the standard cell C through a metal connection line. Signal one is transmitted through a to C and signal two is transmitted through B to C. In order to guarantee the functional implementation of the digital chip, it is necessary to guarantee that C processes signal one first.

Since the transmission time of the first signal and the second signal is almost the same, the timing of the output signal a needs to be earlier than the timing of the output signal B, or the delay of a is smaller than the delay of B, and if the delay of B is 0.2 picoseconds, the delay of a needs to be controlled below 0.2 picoseconds, i.e. the delay range that should be satisfied by the standard cell a. If the delay of A is greater than 0.2 picoseconds, then the delay of A is outside the set delay range. Because different time delays exist in different positions, the position meeting the set time delay range can be found by continuously adjusting the position of the standard unit A.

In order to ensure that the delay of the standard cell meets the set requirement, referring to fig. 9, for example, after determining that the standard cell is in the working area, a circuit manufacturing method provided by an embodiment of the present application further includes:

S170: and determining whether the delay of the standard unit belongs to a set range or not based on a preset standard unit time sequence table according to the position information.

The standard cell timing table stores the type of the standard cell, the position information of the standard cell, and an influence factor corresponding to the position information of the standard cell. The delay of the standard unit under the influence of the TSV stress can be obtained by multiplying the influence factor by the delay of the standard unit under the influence of the TSV. In order to ensure the sequence relation of signal flow directions required by the specific functions of the digital chip, the delay of the standard unit needs to be in a set range. Still taking the above standard cell A, B and C as an example, in order to guarantee the timing requirement that the signal is preferentially transferred from a to C, the delay range of the standard cell a is smaller than the delay range of the standard cell B.

After determining the type, the distance and the angle of the standard unit and the initial delay corresponding to the standard unit, calculating the delay of the standard unit under the influence of the TSV stress based on the distance, the angle and the initial delay of the standard unit and the influence factors corresponding to the standard unit stored in the standard unit time sequence table, and determining whether the delay of the standard unit meets the requirement.

S190: if the time delay of the standard unit is out of the set range, acquiring the position information of the standard unit after updating the position until the time delay is in the set range.

Standard cells within the set delay range meet the timing requirements, and standard cells outside the set timing range do not meet the timing requirements. Taking the above standard units A, B and C as an example, if the delay range of the standard unit a is greater than the delay range of the standard unit B, the priority of signal transmission is changed to be transmitted from the standard unit B to the standard unit C, and there is a delay between the standard unit a and the standard unit C, which results in a change of the timing of the digital chip, thereby affecting the function of the digital chip. At this time, the positions of the standard cells in the working area need to be adjusted so that the time sequence satisfies the set range.

When the position of the standard unit is out of the set range, the delay of the standard unit cannot meet the requirement, the designed circuit may not meet the design requirement, so that the position of the standard unit needs to be adjusted, and the position of the standard unit is moved. The angle of the standard cell and the distance from the center of the standard cell to the center of the TSV may be varied in general cases herein. One case may be to increase the distance without changing the angle; another case is that the distance is not changed, the angle is adjusted, or both the angle and the distance may be adjusted.

After the position of the standard unit is adjusted, acquiring position information of the standard unit after the position is updated, and judging whether the delay corresponding to the position information after the position is updated is in a set range again, stopping adjusting the position if the delay is in the set range, and if the delay is still out of the set range, adjusting the position of the standard unit again, and judging again until the delay of the standard unit is in the set range.

The embodiment of the application determines the setting range of the standard unit meeting the delay requirement by a method of continuously repeating and controlling the variables, wherein the delay of the standard unit meets the requirement in the setting range, and the delay requirement cannot be met outside the setting range. The embodiment of the application utilizes the position information table to determine the working range of the standard units, and any position in the working area meets the functional requirement of the standard units, but the standard units are connected by the metal interconnection lines, the different positions of the standard units can lead to different lengths of the metal interconnection lines, and finally, the time sequence of the digital chip can be possibly unsatisfied or difficult to optimize. And after the standard unit working area is confirmed, the standard unit time sequence table is further used for detection, so that the digital chip time sequence can be ensured to meet the requirement. Compared with the method for prohibiting the standard cell from being set in the whole sacrifice area, the method has the advantages that the standard cell can be set at the position meeting the time sequence in the working area in the sacrifice area, the connection distance of the metal interconnection line is shortened, and the utilization rate of resources is improved better.

But before the position information table is utilized, the position information table and the standard cell timing table need to be established in advance. In an exemplary embodiment, before determining whether the standard cell is in the working area according to the type, distance, angle and location information table, referring to fig. 10, the method further includes:

S101: a table of location information is determined.

And (3) obtaining the relation between the delay of a transistor in the standard unit and the distance of the turning characteristic along with the center of the TSV by calling a device model capable of representing the stress of the TSV in computer software, designing a simulation structure of the standard unit with the TSV, continuously simulating from the KoZ boundary to obtain the position relation between the delay requirement and the turning characteristic set by production and the TSV, and dividing a working area according to the minimum working distance.

Fig. 11 is a flowchart illustrating another circuit manufacturing method according to an embodiment of the present application, referring to fig. 11, S101 includes:

S101-a: invoking a device model of any type of standard unit representing TSV stress, and establishing a simulation structure of the standard unit with the TSV; the model is used for indicating the corresponding relation between the delay and the turning characteristic of the transistor in the standard unit of the type and the position information of the standard unit.

Fig. 12a is a schematic diagram showing the influence of TSV stress on the mobility of transistors inside the standard cell, and fig. 12b is a schematic diagram showing the influence of TSV stress on the threshold voltage variation of transistors inside the standard cell. The abscissa in fig. 12a, 12b represents the center-to-TSV center distance of a standard cell. The ordinate of fig. 12a represents mobility, and it can be seen that the rate of mobility rise is first large and then small as the distance between the transistor and the TSV center increases. The ordinate of fig. 12b indicates the variation amount of the threshold voltage, and the left side of the dotted line represents the process empty region, and since no standard cell is provided in the process empty region, there is no threshold voltage; as the center-to-TSV center distance of the standard cell increases to the right of the dashed line, the amount of change in the threshold voltage of the transistor increases, at a rate from large to small.

Fig. 13a is a schematic diagram showing an influence of TSV stress on a saturation current of a transistor in a standard cell, and fig. 13b is a schematic diagram showing an influence of TSV stress on a threshold voltage of the transistor in the standard cell according to an embodiment of the present application. The abscissa in fig. 13a, 13b represents the center-to-TSV center distance of a standard cell. The ordinate in fig. 13a represents the saturation current, and the left side of the dotted line represents the process empty region, and since no standard cell is provided in the process empty region, there is no saturation current; the saturation current increases with increasing distance to the right of the dashed line, at a rate from large to small. The ordinate of FIG. 13b represents the threshold voltage, the left side of the dashed line represents the process empty region, and since no standard cell is disposed in the process empty region, the threshold voltage is not present; the right side of the dashed line indicates that as distance increases, the threshold voltage of the transistor increases, at a rate from fast to slow.

S101-b: and adjusting the position of the standard unit, and determining the first distance corresponding to each first included angle of the standard unit.

S101-c: and determining the first distance between each first included angle and the corresponding first included angle as the boundary information of the working area of the standard unit.

In one possible implementation, the first included angle of the standard cell is set as a starting angle, the distance from the center of the TSV is set as an initial distance, the distance from the center of the standard cell to the center of the TSV is increased by a set distance step until the minimum working distance is determined, at which the delay and overturn characteristics meet the preset requirements, is determined, and the minimum working distance is determined as the first distance, wherein the initial distance is the radius of the process clearance area.

And then, adjusting a first included angle of the standard unit according to a set angle step length, determining that the delay and overturning characteristics meet the minimum working distance required by the preset requirement after the first included angle is adjusted, until the first included angle of the standard unit is adjusted to a final angle, and determining a first distance corresponding to the final angle, wherein the sum of the final angle and the initial angle is 2 pi. And determining a first distance corresponding to the first included angle of the standard unit as boundary information of the working area. Referring to fig. 14a and fig. 14b, fig. 14a is a schematic delay diagram of a standard cell according to an embodiment of the present application, and fig. 14b is a schematic flip characteristic diagram of a standard cell according to an embodiment of the present application. Fig. 14a reflects the delay of a standard cell versus the center distance to the TSV. Where the abscissa is the distance from the center of the standard cell to the center of the TSV and the ordinate represents the delay of the standard cell. The dashed line L2 is a preset delay threshold, and the delay of the standard cell on the left of the dashed line L2 does not meet the preset requirement, including the dashed line L2 and the delay requirement on the right of the dashed line L2. And a working area meeting the delay requirement of the standard unit is partitioned by taking a delay threshold value represented by a dotted line as a boundary.

Fig. 14b reflects the flip characteristics of the standard cell. The abscissa represents the input voltage and the ordinate represents the output voltage. If there is no influence of the TSV, the inversion characteristic of the standard cell is as indicated by a broken line L3, and the output voltage is changed from a high level to a low level through L3. Under the stress of the TSV, as the distance from the center of the standard cell to the center of the TSV increases, the dotted line L3 is shifted left and right to form a region abcd sandwiched between the two solid lines. In this area abcd, the requirements of the flip characteristics of the standard cells are satisfied, thereby dividing the working area satisfying the flip characteristics of the standard cells. While the need for the flip characteristic is determined by the constraints of the setup time and hold time of the registers.

S101-d: and establishing the position information table according to the type and the boundary information of the working area.

The type of the standard cell and the boundary information corresponding to the standard cell of the type are stored as a position information table. For example, if there are a plurality of different types of standard cells, there may be boundary information of a work area corresponding to the plurality of different types of standard cells.

Illustratively, S130 includes determining whether the standard cell is disposed within the workspace. Illustratively, determining boundary information of a working area corresponding to the type in the position information table according to the type of the standard unit to judge whether the standard unit is positioned in the corresponding working area.

Firstly, determining a first included angle between the boundary information center of the working area corresponding to the standard unit of the type and the angle according to the angle of the standard unit, then comparing the distance of the standard unit with a first distance corresponding to the first included angle, if the distance of the standard unit is greater than or equal to the first distance, determining that the standard unit is positioned in the working area, otherwise, determining that the standard unit is positioned outside the working area.

The timing schedule needs to be pre-established before the standard cell timing schedule is utilized. Before determining whether the delay of the standard cell is within the set range based on the preset standard cell timing chart according to the position information after updating the position, referring to fig. 15, the method provided by the embodiment of the application further includes:

s102, determining a standard cell timing table.

For example, as shown in fig. 15, the determining the standard cell timing table S102 may be performed before the type and the position information of the standard cell are obtained, the position information includes the type distance and the angle S110, or may be performed before determining whether the delay of the standard cell falls within the set range based on the preset standard cell timing table according to the position information after updating the position S170.

Fig. 16 shows a flowchart of another circuit manufacturing method according to an embodiment of the present application, referring to fig. 16, S102 includes:

S102-a: invoking any type of device model characterizing TSV stress; establishing a simulation structure of a standard unit with TSV; the device model is used for indicating the corresponding relation between the time delay of the standard unit of the type and the position information of the standard unit.

S102-b: and determining the delay of the standard unit under the influence of the TSV at the current position, and determining the ratio of the delay to the initial delay of the standard unit as an influence factor at the position, wherein the initial delay refers to the delay of the standard unit under the influence of no TSV.

Determining the delay of a standard unit under the influence of a TSV at the current position, determining the ratio of the delay to the initial delay of the standard unit as an influence factor at the position, wherein the initial delay refers to the delay of the standard unit under the influence of no TSV, and the delay can be directly obtained by any type of device model without the TSV according to simulation.

S102-c: and adjusting the position of the standard unit, determining an influence factor after adjusting the position, and establishing a standard unit time sequence table according to the corresponding relation between the position and the influence factor corresponding to the position.

In one possible implementation, the angle of the standard cell is set as the initial angle, the distance from the center of the TSV is set as the initial distance, and the distance from the center of the standard cell to the center of the TSV is increased by a set distance step until the minimum distance is determined that the delay and flip characteristics meet the preset requirements at the initial angle, wherein the initial distance is the radius of the process clearance area.

And adjusting the angle of the standard unit by the set angle step length, and determining the minimum distance for which the delay and turnover characteristics meet the preset requirements after the angle is adjusted until the angle of the standard unit is adjusted to a termination angle, wherein the sum of the termination angle and the initial angle is 2 pi.

And then simulating according to various process angle models to obtain the time delay of various standard units under the influence of TSV stress at different angles and/or different distances, wherein the ratio of the time delay to the initial time delay is determined as an influence factor at the angle and/or the distance. Each standard cell for position determination has a determined influencing factor. Through the influence factor, the simulation structure of the standard unit with the TSV is not required to be designed according to the device model, and the initial delay can be simulated only by knowing any type of device model without the TSV, so that the delay of the standard unit under the influence of the TSV is obtained. And the delay of the standard units under the superposition of the stress of a plurality of TSVs is more convenient to calculate by using a cumulative initial delay method.

Illustratively, S170 further includes determining whether the standard cell is within a set delay range, and confirming information stored in the location information table consistent with the type of the standard cell according to the type of the standard cell; and confirming the influence factor at the position, and multiplying the influence factor by the initial delay to obtain the delay of the position under the influence of the TSV. There is a range of delays based on the precedence of signal flow that needs to be satisfied by the particular function of the digital chip. From this range it is determined whether the delay of the standard cell is met.

The EDA tool is a design software auxiliary type and a programmable chip auxiliary type, has a strong function, can be generally used for designing and simulating a circuit, can automatically lay out and wire a chip layout, and can output various netlist files and interconnection of a third-party software interface. EDA tool software can be broadly divided into three categories, chip design assistance software, programmable chip assistance design software, system design assistance software, and the like.

For example, when the method for manufacturing a circuit according to the embodiment of the present application is implemented by using an EDA tool, a working area is obtained for each standard cell after the above method, and as shown in fig. 17, the standard cell 330 is disposed in the working area 322.

The establishment of the boundary line is made up of the minimum distance at each preset step angle. Referring to fig. 18, for standard cells, there is a manufacturing risk for placement in the process clearance area 310, so the EDA tool is prohibited from placing standard cells in the process clearance area 310, such as in the d-position shown in fig. 18.

Outside of the process clearance area 310, the conventional sacrificial area 320 is divided into a working area 322 and a failure area 321 for each standard cell, and the delay and flip characteristics of the standard cells in the working area 322 may not meet the design requirements, so that the delay and flip characteristics of the standard cells in the failure area 321 may not meet the design requirements, and thus the standard cells are also prohibited from being placed in the failure area 321, for example, the standard cells are prohibited from being placed in the c position shown in fig. 18.

The standard cell may be prevented from being in the working area 322, such as the a position or the b position shown in fig. 18, but it is also necessary to determine whether the delay of the standard cell satisfies the requirement, for example, if the delay of the standard cell at the a position (R, θ) does not satisfy the requirement, the position of the standard cell is updated until the standard cell stops moving when it moves to the b position (R ', θ') where the timing satisfies the requirement.

Illustratively, the partial code for EDA implementation standard cell workspace boundary determination is shown below:

the partial code for EDA implementation standard cell timing table determination is shown below:

Each standard cell is first set in TechFile of EDA by SPACING R ANGLE theta layer TSV statement according to the setting rule obtained last in the circuit fabrication method. Wherein R and θ represent the minimum distance and the angle of the corresponding minimum distance, respectively. And secondly, acquiring time sequence influence factors of single TSV stress on each different standard unit in a working area through simulation.

The calculation of the influence factors is determined according to the ratio of the simulation structure of the device model design standard unit in the working area to the simulation structure of the TSV-carrying standard unit in the working area meeting the time sequence requirement boundary values, and each determined theta and R corresponds to one determined influence factor.

In one possible implementation, the impact factors of power consumption and noise can also be calculated in the same way and added in the form of a look-up table to the timing statement. The determination of the influence factors is beneficial to directly calculating the influence of the TSVs on time sequence, power consumption and noise. For example, for a plurality of TSVs, the EDA tool multiplies the impact factors to calculate a time sequence, power consumption, and noise that can characterize the stress stack of the plurality of TSVs.

See two circuit designs shown in fig. 19. As shown in the left diagram of fig. 19, in the conventional circuit design scheme, a unified sacrificial region 320 is defined for different standard cells 330 outside the process clearance area 310, and the standard cells 330 can only be disposed outside the sacrificial region 320, which results in waste of design resources, and according to the circuit manufacturing method provided by the embodiment of the application, as shown in the right diagram of fig. 19, the device model for characterizing TSV stress divides the sacrificial region 320 into a working region 322 and a failure region 321 by means of simulation, and the standard cells 330 can be placed in the working region 322, so that the placement rule of each standard cell 330 is formulated, that is, different working regions 322 are divided for different standard cells 330. Different standard cells 330 are disposed within different workspaces 322 thereby increasing the reasonable utilization of resources.

The embodiment of the application also provides a circuit design device, and a circuit design device is shown in fig. 20, and the device 500 comprises an acquisition module 501 and a processing module 502.

The obtaining module 501 is configured to obtain type and position information of a standard cell, where the position information includes an angle and a distance, the distance is a distance from a center of the standard cell to a center of a through silicon via TSV, and the angle is an included angle between a center line of the TSV to the standard cell and a center horizontal line of the standard cell.

The processing module 502 is configured to determine whether the standard unit is located in the working area according to the type, the distance, the angle and a preset location information table, where the location information table stores boundary information of working areas of different types of standard units, the boundary information includes a first included angle and a first distance, the first included angle is an included angle between a center connecting line of the TSV and a center horizontal line of the standard unit, and the first distance is a minimum working distance between a center of the standard unit corresponding to the first included angle and a center of the TSV.

The obtaining module 501 is further configured to obtain, when the standard unit is outside the working area, location information of the standard unit after the location is updated until the standard unit is inside the working area.

Embodiments of the present application also provide a computer-readable storage medium having stored therein computer instructions that, when executed by a computer or processor, enable the computer or processor to perform a method of characterizing TSV technology stress.

The embodiment of the application also provides a chip, wherein the chip stores computer instructions, and when the computer instructions are executed by a processor, the method for representing the TSV technical stress can be executed.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.

Finally, it should be noted that: the foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (13)

1. A method of making a circuit, the method comprising:

The method comprises the steps of obtaining type and position information of a standard cell, wherein the position information comprises an angle and a distance, the distance is from the center of the standard cell to the center of a through silicon via, and the angle is as follows: the included angle between the center of the through silicon via and the center connecting line of the standard unit and the center horizontal line of the standard unit;

Determining whether the standard unit is in a working area or not according to the type, the distance, the angle and a preset position information table; the position information table stores boundary information of working areas of different types of standard units, wherein the boundary information comprises a first included angle and a first distance; the first included angle is as follows: the included angle between the central connecting line from the center of the through silicon via to the standard unit and the central horizontal line of the standard unit; the first distance is the minimum working distance from the center of the standard unit corresponding to the first included angle to the center of the through silicon via;

and if the standard unit is located outside the working area, acquiring the position information of the standard unit after the position is updated until the standard unit is located in the working area.

2. The circuit fabrication method of claim 1, wherein if the standard cell is outside the working area, obtaining location information after the standard cell is updated until the standard cell is inside the working area, the method further comprising:

Determining whether the delay of the standard unit belongs to a set range or not based on a preset standard unit time sequence table according to the position information;

and if the time delay is out of the set range, acquiring the position information of the standard unit after the position is updated until the time delay is in the set range.

3. The circuit fabrication method according to claim 1 or 2, characterized in that before determining whether the standard cell is within a working area according to the type, the distance, the angle and a position information table, the method further comprises:

and determining the position information table.

4. A circuit fabrication method according to claim 3, wherein said determining the location information table comprises:

Calling a device model of any type of standard unit representing the stress of the through silicon via, and establishing a simulation structure of the standard unit with the through silicon via; the model is used for indicating the corresponding relation between the delay and the turnover characteristics of the transistors in the standard unit of the type and the position information of the standard unit;

the position of the standard unit is adjusted, and the first distance corresponding to each first included angle of the standard unit is determined;

Determining the first distance between each first included angle and the corresponding first included angle as boundary information of the working area of the standard unit of the type;

And establishing the position information table according to the type and the boundary information of the working area.

5. The circuit fabrication method of claim 4, wherein said adjusting the position of the standard cell, determining the first distance corresponding to the standard cell at each of the first angles comprises:

Setting a first included angle of the standard unit as an initial angle, setting a distance from the center of the through silicon via as an initial distance, and increasing the distance from the center of the standard unit to the center of the through silicon via by a set distance step length until the minimum working distance that the delay and the turnover characteristic meet preset requirements is determined under the initial angle, wherein the initial distance is the radius of a process clearance area;

And adjusting a first included angle of the standard unit according to a set angle step length, and determining the minimum working distance for which the delay and the turnover characteristic meet preset requirements after adjusting the first included angle until the first included angle of the standard unit is adjusted to a final angle, wherein the sum of the final angle and the initial angle is 2 pi.

6. The circuit fabrication method according to any one of claims 1 to 5, wherein determining whether the standard cell is in a working area according to the type, the distance, the angle, and a predetermined position information table comprises:

determining boundary information of a working area corresponding to the type in the position information table according to the type of the standard unit;

Determining the first distance corresponding to the first included angle matched with the angle in the boundary information of the working area according to the angle;

And if the distance is greater than or equal to the first distance, the standard cell is positioned in the working area.

7. The circuit manufacturing method according to claim 2, wherein before determining whether or not the delay of the standard cell falls within a set range based on a preset standard cell timing table based on the updated position information, the method further comprises:

the standard cell timing schedule is determined.

8. The circuit fabrication method according to claim 2, wherein the method of creating the standard timing table comprises:

invoking a device model of any type of standard unit representing the stress of the through silicon via, and establishing a simulation structure of the standard unit with the through silicon via; the standard unit model is used for indicating the corresponding relation between the time delay of the standard unit of the type and the position information of the standard unit;

Determining the delay of the standard unit under the influence of the through silicon via at the current position, and determining the ratio of the delay to the initial delay of the standard unit as an influence factor of the position, wherein the initial delay refers to the delay of the standard unit under the influence of no through silicon via;

And adjusting the position of the standard unit, determining an influence factor after adjusting the position, and establishing the time sequence table of the standard unit according to the corresponding relation between the position and the influence factor corresponding to the position.

9. The circuit manufacturing method according to any one of claims 1 to 8, wherein the standard cell timing table stores a correspondence relation between position information of a standard cell and an influence factor of delay of the through silicon via on the standard cell, and wherein determining whether the timing of the standard cell falls within a set range based on a preset standard cell timing table according to the position information after updating the position comprises:

determining an influence factor according to the position information and the standard unit time sequence table;

Multiplying the influence factor by the initial delay of the standard unit to determine the delay of the standard unit under the influence of the through silicon via;

and determining whether the delay of the standard unit under the influence of the through silicon via belongs to a set range.

10. A circuit design apparatus, the apparatus comprising:

The device comprises an acquisition module, a reference cell and a reference cell, wherein the acquisition module acquires type and position information of the reference cell, the position information comprises an angle and a distance, the distance is the distance from the center of the reference cell to the center of a through silicon via, and the angle is an included angle between a central connecting line from the center of the through silicon via to the reference cell and a central horizontal line of the reference cell;

The processing module is used for determining whether the standard unit is in a working area or not according to the type, the distance, the angle and a preset position information table, wherein the position information table stores boundary information of working areas of different types of standard units, and the boundary information comprises a first included angle and a first distance; the first included angle is as follows: the included angle between the central connecting line from the center of the through silicon via to the standard unit and the central horizontal line of the standard unit; the first distance is the minimum working distance from the center of the standard unit corresponding to the first included angle to the center of the through silicon via;

And if the standard unit is positioned outside the working area, the acquisition module is also used for acquiring the position information of the standard unit after the position is updated until the standard unit is positioned in the working area.

11. A computer readable storage medium having stored therein computer instructions which, when executed by a processor, enable the processor to perform the method of any one of claims 1 to 9.

12. A chip, characterized in that it stores computer instructions which, when executed by a processor, implement the method of any of claims 1-9.

13. An electronic device, the electronic device comprising:

A processor and a memory;

wherein the processor is configured to execute computer instructions stored in the memory to implement the method of any one of claims 1-9.