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CN117711951A - Chip welding method, chip packaging method and chip packaging structure - Google Patents

Chip welding method, chip packaging method and chip packaging structure Download PDF

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Publication number
CN117711951A
CN117711951A CN202311520592.5A CN202311520592A CN117711951A CN 117711951 A CN117711951 A CN 117711951A CN 202311520592 A CN202311520592 A CN 202311520592A CN 117711951 A CN117711951 A CN 117711951A
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China
Prior art keywords
chip
welding
substrate
preset high
high temperature
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Pending
Application number
CN202311520592.5A
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Chinese (zh)
Inventor
刘在福
郭瑞亮
焦洁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Tongfu Chaowei Semiconductor Co ltd
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Suzhou Tongfu Chaowei Semiconductor Co ltd
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Application filed by Suzhou Tongfu Chaowei Semiconductor Co ltd filed Critical Suzhou Tongfu Chaowei Semiconductor Co ltd
Priority to CN202311520592.5A priority Critical patent/CN117711951A/en
Publication of CN117711951A publication Critical patent/CN117711951A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The embodiment of the disclosure provides a chip welding method, a chip packaging method and a chip packaging structure, wherein the welding method comprises the following steps: flip-chip the chip on the substrate through the conductive bump; placing the chip and the substrate in a welding furnace, and vacuumizing the welding furnace; heating the welding furnace to a first preset high temperature, pressurizing the welding furnace to a preset first high pressure, and maintaining the first preset high temperature and the first preset high pressure to soften and flatten the substrate; continuously maintaining the first preset high temperature, and vacuumizing the welding furnace to discharge part of welding gas; heating the welding furnace to a second preset high temperature, pressurizing the welding furnace to a second preset high pressure, and maintaining the second preset high temperature and the second preset high pressure so as to enable the conductive protrusions to be melted and discharge residual welding gas; and cooling and reducing the pressure of the welding furnace to finish the chip welding. The warping of the substrate can be controlled at high temperature, so that the bridging of the conductive bumps is avoided; and the soldering flux and the gas are discharged during the welding, so that the cold joint is avoided, and the welding quality is improved.

Description

Chip welding method, chip packaging method and chip packaging structure
Technical Field
The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a chip welding method, a chip packaging method and a chip packaging structure.
Background
At present, the flip chip is mainly soldered by adopting a vacuum reflow oven for reflow soldering, and mainly comprises a preheating stage, a high-temperature soldering stage and a cooling stage. In the existing flip chip welding method, the warping of the substrate cannot be controlled at high temperature, so that solder balls can be bridged, and the reliability of the chip is affected; the soldering flux volatilized in the high-temperature heating process and the welding gas volatilized by the soldering flux can not be timely discharged, so that the cold joint is easily caused, and the welding quality is influenced; the existing vacuum reflow oven needs to be provided with a temperature raising, welding and cooling temperature extension machine, so that the size of the vacuum reflow oven reaches about 5 meters, and the occupied space is large; in addition, during the soldering process, the flip chip needs to use a special fixture to control the warpage of the substrate, the used fixture has high cost, and the fixture has little effect of controlling the warpage of the crying face-shaped substrate.
In view of the above, it is necessary to provide a die bonding method, a die packaging method and a die packaging structure which are reasonably designed and effectively solve the above problems.
Disclosure of Invention
The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a chip welding method, a chip packaging method and a chip packaging structure.
An aspect of an embodiment of the present disclosure provides a die bonding method, the method including:
s1, flip-chip mounting a chip on a substrate through conductive bumps;
s2, placing the chip and the substrate which are subjected to the mounting in a welding furnace, and vacuumizing the welding furnace;
step S3, heating the welding furnace to a first preset high temperature, pressurizing the welding furnace to a preset first high pressure, and maintaining the first preset high temperature and the first preset high pressure so as to soften the substrate and flatten the substrate;
step S4, continuously maintaining the first preset high temperature, and vacuumizing the welding furnace to discharge part of welding gas;
step S5, continuously heating the welding furnace to a second preset high temperature, pressurizing the welding furnace to a second preset high pressure, and maintaining the second preset high temperature and the second preset high pressure so as to enable the conductive protrusions to be melted and discharge the residual welding gas, wherein the second preset high pressure is higher than the first preset high pressure;
and S6, cooling and reducing the pressure of the welding furnace so as to weld the chip on the substrate.
Optionally, the step S4 and the step S5 are cyclically and alternately performed.
Optionally, the first preset high temperature is lower than the melting temperature of the conductive bump.
Optionally, the second preset high temperature is higher than the melting temperature of the conductive bump.
Optionally, in step S1, before the flip chip is flip chip mounted on the substrate through the conductive bump, the method further includes: forming a soldering flux on one side of the conductive bump facing the substrate;
the welding gas in the step S4 includes a gas generated by the flux and the melted conductive bump during the welding process.
Optionally, the range of the first preset high pressure is 4kPa to 6kPa.
Optionally, the second preset high pressure ranges from 7kPa to 9kPa.
Optionally, the step S2 further includes:
and filling nitrogen into the welding furnace as protective gas.
Another aspect of an embodiment of the present disclosure provides a chip packaging method, including:
providing a chip, a substrate, a welding metal layer and a heat dissipation cover;
flip-chip the chip on the substrate through the conductive bumps;
soldering the die to the substrate using the die-soldering method described previously;
arranging a welding metal layer on one side of the chip, which is away from the substrate;
the heat dissipation cover is arranged on one side, away from the chip, of the welding metal layer, and the edge area of the heat dissipation cover is fixed on the substrate;
and carrying out reflow soldering on the soldering metal layer to fix the heat dissipation cover on the chip.
Another aspect of the embodiments of the present disclosure provides a chip package structure, which is formed by encapsulating by the encapsulation method described above.
According to the chip welding method, the chip packaging method and the chip packaging structure, the welding furnace is heated to the first preset high temperature through the step S3, meanwhile, the welding furnace is pressurized to the preset first high pressure, the first preset high temperature and the first preset high pressure are maintained, the substrate is softened at the first preset high temperature and is preheated at the high temperature for subsequent welding, the substrate can be flattened and leveled at the first preset high temperature, flatness of the substrate is controlled at the high temperature, solder ball bridging caused by substrate warping is avoided, reliability and stability of the chip are improved, a clamp is not required to be used for controlling the substrate warping in the high temperature welding process, and equipment cost is reduced.
According to the chip welding method disclosed by the embodiment of the disclosure, the first preset high temperature is continuously maintained through the step S4, and the welding furnace is vacuumized, so that part of welding gas can be discharged in the vacuumization process, the cold joint is avoided, and the chip welding quality is improved. And (5) continuously heating the welding furnace to a second preset high temperature, pressurizing the welding furnace to a second preset high pressure, maintaining the second preset high temperature and the second preset high pressure, melting the conductive protrusions at the second preset high temperature, and discharging residual welding gas under the action of the second preset high pressure, so that the cold joint is further avoided, and the welding quality of the chip is further improved.
According to the chip welding method, the welding furnace does not need additional temperature raising, welding and cooling temperature extension equipment, the occupied space is small, and the space and the cost are saved.
Drawings
FIG. 1 is a flow chart of a die bonding method according to an embodiment of the disclosure;
FIG. 2 is a flow chart of a method for packaging a chip according to another embodiment of the disclosure;
fig. 3 to 5 are schematic views illustrating a packaging process of a chip packaging method according to another embodiment of the disclosure.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.
As shown in fig. 1, a first aspect of an embodiment of the present disclosure provides a die bonding method S10, the method S10 including:
and S1, flip-chip mounting the chip on the substrate through the conductive bumps.
Specifically, as shown in fig. 3, a chip 110 and a substrate 120 are provided, wherein a plurality of conductive bumps 130 are provided on a functional surface of the chip 110, and the substrate 120 is provided with a solder layer 121 at the conductive bumps 130 of the corresponding chip 110.
Before the chip 110 is flip-chip mounted on the substrate 120 through the conductive bump 130, the method further includes: a flux is formed on a side of the conductive bump 130 facing the substrate 120.
The chip 110 is flip-chip mounted on the solder layer of the substrate 120 through the conductive bump 130, wherein the soldering flux contacts the solder layer, and the chip mounting is completed. In the present embodiment, the conductive bump 130 is taken as a solder ball for example.
And S2, placing the chip and the substrate which are subjected to the mounting in a welding furnace, and vacuumizing the welding furnace.
Specifically, the mounted chip 110 and substrate 120 are placed in a soldering furnace, the soldering furnace is vacuumized, and nitrogen is filled as a protective gas, so that the oxygen content is reduced, and a soldering environment for soldering the chip is provided. At the same time, the welding furnace is heated and preheated,
wherein the preheating temperature is within the range of 10-50 ℃. In this embodiment, a corresponding soldering environment is provided for solder ball soldering.
And step S3, heating the welding furnace to a first preset high temperature, pressurizing the welding furnace to a preset first high pressure, and maintaining the first preset high temperature and the first preset high pressure so as to soften the substrate and flatten the substrate.
Specifically, the welding furnace is heated to a first preset high temperature, and simultaneously, the welding furnace is pressurized to a preset first high pressure, and the first preset high temperature and the first preset high pressure are maintained for a period of time. At a first preset high temperature, the substrate 120 may be softened and preheated at a high temperature for subsequent soldering. Under the action of the first preset high voltage, the substrate 120 can be flattened, especially for crying face type substrates, the warping of the substrate 120 can be controlled, the flatness of the substrate can be controlled at high temperature, solder ball bridging caused by the warping of the substrate is avoided, the reliability and stability of a chip are improved, in addition, a clamp is not needed to be used for controlling the warping of the substrate in the high-temperature welding process, and the equipment cost is reduced.
Illustratively, in this step S3, the first preset high temperature is lower than the melting temperature of the conductive bump 130, that is, the conductive bump 130 does not melt at the first preset high temperature.
In this embodiment, the conductive bump 130 is a solder ball, and the melting point of the solder ball is 231.9 ℃. In the step S3, the range of the first preset high temperature is 130-160 ℃, and the range of the first preset high pressure is 4-6 kPa. Preferably, in this embodiment, the first preset high temperature is about 144 ℃, and the first preset high pressure is about 5 kPa.
It should be noted that the first preset high temperature and the first preset high pressure may also be adjusted according to specific requirements, and the embodiment is not limited specifically.
In this embodiment, the first preset high temperature ranges from 130 ℃ to 160 ℃, so that the substrate 120 can reach a softened state. The range of the first preset high pressure is 4kPa to 6kPa, and the substrate 120 can be better flattened, so that the flatness of the substrate 120 can be well controlled at a high temperature.
In step S3 of this embodiment, the time range of maintaining the first preset high temperature is 55min to 65min, and the time range of maintaining the first preset high pressure is 80min to 90min. Preferably, the time for maintaining the first preset high temperature is about 60 minutes, and the time for maintaining the first preset high pressure is about 85 minutes.
It should be noted that, the time for maintaining the first preset high temperature and the first preset high pressure may be adjusted according to actual needs, and the embodiment is not specifically limited.
In this embodiment, the substrate can be kept in a softened state by maintaining the first preset high temperature for 55min to 65 min. The time range of the first preset high pressure is maintained to be 80-90 min, so that the substrate can be well flattened, and the warping of the substrate can be well controlled at high temperature.
And S4, continuously maintaining the first preset high temperature, and vacuumizing the welding furnace to discharge part of welding gas.
In this embodiment, the soldering gas includes flux and gas generated by the melted conductive bump 130 during soldering. I.e. the flux and the gas generated by the molten solder balls during the soldering process.
Specifically, the first preset high temperature is continuously maintained, that is, the temperature range of the high temperature furnace is continuously maintained at 130-160 ℃, and the high temperature preheating can be continuously performed for the subsequent welding. And the welding furnace is vacuumized, and part of welding gas is discharged through vacuumization, so that the cold joint is avoided, and the welding quality is improved.
In step S4 of this embodiment, the time range of continuously maintaining the first preset high temperature and the vacuum pumping is 15 min-25 min. Preferably, the first preset high temperature is maintained for about 20 minutes.
It should be noted that, the time for continuously maintaining the first preset high temperature and the vacuum pumping may be adjusted according to the actual needs, and the embodiment is not particularly limited.
In this embodiment, in step S4, the time range of continuously maintaining the first preset high temperature and evacuating is 15 min-25 min, which is more favorable for exhausting part of the welding gas in the evacuating process, thereby avoiding the cold joint and improving the welding quality.
And S5, continuously heating the welding furnace to a second preset high temperature, pressurizing the welding furnace to a second preset high pressure, and maintaining the second preset high temperature and the second preset high pressure so as to enable the conductive protrusions to be melted and discharge the residual welding gas, wherein the second preset high pressure is higher than the first preset high pressure.
Specifically, the welding furnace is continuously heated to a second preset high temperature, and meanwhile pressure is applied to the welding furnace to a second preset high pressure, wherein the second preset high pressure is higher than the first preset high pressure. Under the action of the second preset high temperature, the conductive protrusions 130 are melted, and under the action of the second preset pressure, the residual welding gas can be discharged, so that the cold joint is further avoided, and the welding quality is further improved. Wherein the second preset high temperature is higher than the melting temperature of the conductive bump 130. In this embodiment, the second predetermined high temperature is higher than the melting temperature of the solder balls.
In step S5 of the present embodiment, the second preset high temperature ranges from 240 ℃ to 250 ℃ and the second preset high pressure ranges from 7kPa to 9kPa. Preferably, in this embodiment, the second predetermined high temperature is about 240 ℃ and the second predetermined high pressure is about 8 kPa. The second preset high temperature and the second preset high pressure in the above range can well melt the solder balls and discharge the residual soldering gas.
It should be noted that, the second preset high temperature and the second preset high pressure can be adjusted according to specific requirements, and the embodiment is not limited specifically.
In step S5 of this embodiment, the time range for maintaining the second preset high temperature is 10min to 20min, and the time range for maintaining the second preset high pressure is 20min to 30min. Preferably, in this embodiment, the time for maintaining the second preset high temperature is about 13min, and the time for maintaining the second preset high pressure is about 25min. The time range of maintaining the second preset high temperature and the second preset pressure in the above range can well enable the solder balls to be melted and discharge the residual welding gas.
It should be noted that, the second preset high temperature and the second preset high pressure maintaining time may be adjusted according to actual needs, and the embodiment is not particularly limited.
And S6, cooling and reducing the pressure of the welding furnace so as to weld the chip on the substrate.
Specifically, the soldering furnace is cooled and depressurized to solder the conductive bumps 130 of the chip 110 to the substrate 120, so as to complete the soldering of the chip.
Illustratively, in this embodiment, steps S4 and S5 are cyclically alternated. That is, the process of evacuating and exhausting the welding gas at high temperature and the process of exhausting the welding gas at high temperature and high pressure can be circularly and alternately performed, so that the welding gas can be completely exhausted, and the welding quality of the chip is better ensured.
According to the chip welding method provided by the embodiment of the disclosure, the welding furnace is heated to the first preset high temperature through the step S3, meanwhile, the welding furnace is pressurized to the preset first high pressure, the first preset high temperature and the first preset high pressure are maintained, the substrate is softened at the first preset high temperature and is preheated at the high temperature for subsequent welding, the substrate can be flattened and leveled at the first preset high temperature, the flatness of the substrate is controlled at the high temperature, solder ball bridging caused by substrate warping is avoided, the reliability and stability of the chip are improved, the substrate warping is controlled without using a clamp in the high temperature welding process, and the equipment cost is reduced.
According to the chip welding method disclosed by the embodiment of the disclosure, the first preset high temperature is continuously maintained through the step S4, and the welding furnace is vacuumized, so that part of welding gas can be discharged in the vacuumization process, the cold joint is avoided, and the chip welding quality is improved. And (5) continuously heating the welding furnace to a second preset high temperature, pressurizing the welding furnace to a second preset high pressure, maintaining the second preset high temperature and the second preset high pressure, melting the conductive protrusions at the second preset high temperature, and discharging residual welding gas under the action of the second preset high pressure, so that the cold joint is further avoided, and the welding quality of the chip is further improved.
According to the chip welding method, the welding furnace does not need additional temperature raising, welding and cooling temperature extension equipment, the occupied space is small, and the space and the cost are saved.
As shown in fig. 2, a second aspect of the embodiments of the present disclosure provides a chip packaging method S100, where the method S100 includes:
s110, providing a chip, a substrate, a welding metal layer and a heat dissipation cover.
Specifically, as shown in fig. 3, a chip 110, a substrate 120, a solder metal layer 140, and a heat sink cap 150 are provided. The functional surface of the chip 110 is provided with a plurality of conductive bumps 130, the substrate 120 is provided with a solder layer 121 corresponding to the conductive bumps 130 of the chip 110, and the conductive bumps 130 are formed with a soldering flux.
S120, the chip is flip-chip mounted on the substrate through the conductive bumps.
Specifically, as shown in fig. 3, the chip 110 is flip-chip mounted on the solder layer 121 of the substrate 120 through the conductive bumps 130.
S130, welding the chip to the substrate by adopting the chip welding method of the first aspect.
Specifically, the die 110 is soldered to the substrate 120 using the die-soldering method described above. The specific process of the die bonding method has been described in detail above, and will not be described herein.
And S140, arranging a welding metal layer on one side of the chip, which is away from the substrate.
As shown in fig. 4, a solder metal layer 140 is disposed on the nonfunctional side of the chip 110. The solder metal layer 140 may be an indium sheet, an organic TIM material, a graphene sheet, or the like, and the material of the solder metal layer 140 may be selected according to actual needs, which is not particularly limited in this embodiment.
S150, arranging the heat dissipation cover on one side of the welding metal layer, which is away from the chip, and fixing the edge area of the heat dissipation cover on the substrate.
As shown in fig. 5, a heat dissipation cover 150 is disposed on a side of the solder metal layer 140 facing away from the chip 110, and an edge region of the heat dissipation cover 150 is fixed to the substrate 120.
And S160, carrying out reflow soldering on the soldering metal layer to fix the heat dissipation cover on the chip.
Specifically, the solder metal layer 140 is placed in a vacuum reflow oven for reflow soldering, so that the heat sink cap 150 is fixed to the chip 110, to complete the packaging of the chip.
According to the chip packaging method, the chip is welded on the substrate by adopting the chip welding method, the substrate is softened at the first preset high temperature, the substrate can be flattened at the first preset high temperature, the substrate warpage is controlled at the high temperature, solder ball bridging caused by the substrate warpage is avoided, the reliability and stability of the chip are improved, a clamp is not needed to control the substrate warpage in the high-temperature welding process, and the equipment cost is reduced; welding gas can be well discharged in the welding process, so that cold joint is avoided, the welding quality of the chip is improved, and the quality of the chip packaging structure is further improved.
A third aspect of the embodiments of the present disclosure provides a chip packaging structure formed by the chip packaging method S100 described above. The specific process of the chip packaging method S100 has been described in detail above, and will not be described in detail here.
According to the chip packaging structure disclosed by the embodiment of the disclosure, the substrate has no warpage problem, the chip is tightly connected with the substrate, and the quality and reliability of the chip packaging structure are high.
It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims (10)

1. A method of die bonding, the method comprising:
s1, flip-chip mounting a chip on a substrate through conductive bumps;
s2, placing the chip and the substrate which are subjected to the mounting in a welding furnace, and vacuumizing the welding furnace;
step S3, heating the welding furnace to a first preset high temperature, pressurizing the welding furnace to a preset first high pressure, and maintaining the first preset high temperature and the first preset high pressure so as to soften the substrate and flatten the substrate;
step S4, continuously maintaining the first preset high temperature, and vacuumizing the welding furnace to discharge part of welding gas;
step S5, continuously heating the welding furnace to a second preset high temperature, pressurizing the welding furnace to a second preset high pressure, and maintaining the second preset high temperature and the second preset high pressure so as to enable the conductive protrusions to be melted and discharge the residual welding gas, wherein the second preset high pressure is higher than the first preset high pressure;
and S6, cooling and reducing the pressure of the welding furnace so as to weld the chip on the substrate.
2. The method according to claim 1, wherein said step S4 and said step S5 are cyclically alternated.
3. The method of claim 1, wherein the first predetermined elevated temperature is below a melting temperature of the conductive bump.
4. A method according to any one of claims 1 to 3, wherein the second predetermined elevated temperature is above the melting temperature of the conductive bump.
5. A method according to any one of claims 1 to 3, wherein in step S1, before the flip-chip is mounted on the substrate by the conductive bumps, the method further comprises: forming a soldering flux on one side of the conductive bump facing the substrate;
the welding gas in the step S4 includes a gas generated by the flux and the melted conductive bump during the welding process.
6. A method according to any one of claims 1 to 3, wherein the first preset high pressure is in the range of 4kPa to 6kPa.
7. A method according to any one of claims 1 to 3, wherein the second preset high pressure is in the range of 7kPa to 9kPa.
8. A method according to any one of claims 1 to 3, wherein step S2 further comprises:
and filling nitrogen into the welding furnace as protective gas.
9. A method of packaging a chip, the method comprising:
providing a chip, a substrate, a welding metal layer and a heat dissipation cover;
flip-chip the chip on the substrate through the conductive bumps;
soldering the die to the substrate using the die-soldering method of any one of claims 1 to 8;
arranging a welding metal layer on one side of the chip, which is away from the substrate;
the heat dissipation cover is arranged on one side, away from the chip, of the welding metal layer, and the edge area of the heat dissipation cover is fixed on the substrate;
and carrying out reflow soldering on the soldering metal layer to fix the heat dissipation cover on the chip.
10. A chip packaging structure, wherein the chip packaging structure is formed by the packaging method according to claim 9.
CN202311520592.5A 2023-11-15 2023-11-15 Chip welding method, chip packaging method and chip packaging structure Pending CN117711951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311520592.5A CN117711951A (en) 2023-11-15 2023-11-15 Chip welding method, chip packaging method and chip packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311520592.5A CN117711951A (en) 2023-11-15 2023-11-15 Chip welding method, chip packaging method and chip packaging structure

Publications (1)

Publication Number Publication Date
CN117711951A true CN117711951A (en) 2024-03-15

Family

ID=90148765

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311520592.5A Pending CN117711951A (en) 2023-11-15 2023-11-15 Chip welding method, chip packaging method and chip packaging structure

Country Status (1)

Country Link
CN (1) CN117711951A (en)

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