CN117673082A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first trench and a second trench disposed in a substrate. The first trench extends along a first direction and the second trench extends along a second direction. extending, and the first groove and the second groove are staggered with each other in the first region. The first doping region has impurities of the first conductivity type and is disposed under the bottom surface of the first trench along the first direction in the first region. The second doping region has impurities of the second conductivity type and is located in the first region. The inner portion is disposed under the bottom surface of the second trench along the second direction, and the first doped regions and the second doped regions are staggered with each other. The conductive layer is disposed in the first trench and the second trench in the first region, and the conductive layer is electrically connected to the first doped region and the second doped region.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to semiconductor technology, and in particular to a semiconductor device including a source-base electrical connection structure in a staggered trench and a manufacturing method thereof.

Background technique

Power transistors are usually used in power electronics technology. Power metal-oxide semiconductor field effect transistor (power MOSFET) is the most commonly used component in power conversion systems. It contains a horizontal structure. For example, laterally-diffused metal-oxide semiconductor (LDMOS) field effect transistors, and vertical structures, such as trench-type gate metal-oxide semiconductor field-effect transistors (trench gate MOSFET), among which trench-type Gate MOSFET has the gate placed in the trench.

In recent years, in response to the development of various electronic products, the power and layout density of power MOSFETs have also increased. Trench gate MOSFETs have the advantages of reducing component unit size and reducing parasitic capacitance, so they are widely used in many different applications. In fields such as battery management, power supplies, charging systems, etc., however, it is difficult for existing trench gate MOSFETs to fully meet the needs of electronic products in all aspects, such as reducing chip area and increasing component layout at the same time. Density, increased current and reduced on-state resistance (Ron) and other requirements, and there are still many problems in the structure and manufacturing of trench gate MOSFETs that need to be overcome.

Contents of the invention

The present invention provides a semiconductor device including a source-body electrically connected structure in a staggered trench and a manufacturing method thereof, which uses the opening of the trench to implement a self-aligned ion implantation process. A source-body electrically connected contact structure is formed in the trench, so that the base region of the semiconductor device can be electrically coupled to the ground terminal, thereby stabilizing the threshold voltage (Vt) of the semiconductor device. , and has various advantages such as reducing chip area, increasing component layout density and reducing on-resistance. At the same time, it can also reduce the number of photomasks used in the manufacturing of semiconductor devices, achieving the benefit of saving manufacturing costs.

In one embodiment, the present invention provides a semiconductor device, including a first trench extending along a first direction disposed in a substrate, a second trench extending along a second direction disposed in the substrate, and the first trench extending along a second direction is disposed in the substrate. The trenches and the second trenches are interleaved with each other in the first region, and the first doping region with the impurity of the first conductivity type is disposed under the bottom surface of the first trench along the first direction in the first region, with The second doping region of the second conductive type impurity is disposed under the bottom surface of the second trench along the second direction in the first region, and the first doping region and the second doping region are interleaved with each other, and In the first region, a conductive layer is provided in the first trench and the second trench, and the conductive layer is electrically connected to the first doped region and the second doped region.

In one embodiment, the conductive layer has a cross-shaped plan view profile and directly contacts the top surfaces of the first doped region and the second doped region.

In an embodiment, the semiconductor device further includes: a first gate disposed in the first trench and located in a second region adjacent to the first region; a source contact region having the The first conductivity type is disposed under the bottom surface of the first trench along the first direction in the second region, and the first doped region is electrically connected to the source contact region; a source region having the first conductivity type, disposed in the substrate and adjacent to the bottom surface of the substrate; a first base region having the second conductivity type, disposed in the substrate, The second region is disposed above the first source region along the first direction, and the second doped region is electrically connected to the first base region.

In an embodiment, the semiconductor device further includes: a second gate disposed in the first trench and located in the second region along a depth direction of the first trench, the The first gate and the second gate are separated from each other; a second source region having the first conductivity type is disposed in the substrate and adjacent to the top surface of the substrate; a second base region has The second conductivity type is disposed in the substrate and located below the second source region; and a shared drain region has the first conductivity type, is disposed in the substrate and is located under the between the first base region and the second base region.

In one embodiment, the first gate electrode and the second gate electrode are separated from the conductive layer in the first direction.

In one embodiment, the semiconductor device further includes: a third trench disposed in the substrate and located between the two first regions, the third trench being parallel to the first trench The grooves are interleaved with the second trenches; and a third gate is disposed in the third trench and extends into the second trench along the first direction, wherein the third gate The tri-gate is separated from the conductive layer in a second direction.

In one embodiment, the semiconductor device further includes: a fourth trench disposed in the substrate and located between the two first regions, the fourth trench being parallel to the first trench The grooves are interleaved with the second trench; and a fourth gate is disposed in the fourth trench and extends along the first direction into the second trench; at least the third One of the gate electrode and the fourth gate extends along the second direction in the second trench, so that the third gate electrode and the fourth gate electrode are electrically connected.

In one embodiment, the semiconductor device further includes: another gate disposed in the third trench, and in a depth direction of the third trench, the other gate is connected to the third trench. The three gates are separated from each other, and the other gate extends into the second trench along the first direction, wherein the other gate is separated from the conductive layer in the second direction.

In an embodiment, the semiconductor device further includes: a field plate disposed in the first trench, and along a depth direction of the first trench, the field plate and the first gate separated from each other; and a drain region having the first conductivity type, disposed in the substrate and located above the first body region.

In one embodiment, the semiconductor device further includes a dielectric material filling the first trench and the second trench in the first region and covering the conductive layer.

In one embodiment, the conductive layer is electrically connected to a bottom conductive layer located below the bottom surface of the substrate, and the bottom conductive layer is electrically coupled to a ground.

In one embodiment, the semiconductor device further includes a conductive plug passing through the dielectric material, disposed in the first trench and the second trench in the first region, and electrically connected to the conductive layer.

According to an embodiment, the present invention provides a method for manufacturing a semiconductor device, including the following steps: providing a substrate; forming a first trench and a second trench in the substrate, the first trench extending along a first direction, and the second trench extending along a first direction. The trench extends along the second direction, and the first trench and the second trench intersect with each other in the first area; in the first area, a first conductive type of the first conductive type is performed on the substrate through the first opening of the first trench. A self-aligned ion implantation process is used to form a first doping region located under the bottom surface of the first trench; in the first region, a second self-alignment of the second conductivity type is performed on the substrate through the second opening of the second trench. A quasi-ion implantation process to form a second doping region located under the bottom surface of the second trench; and in the first region, a conductive layer is formed in the first trench and the second trench, and the conductive layer is electrically connected to the second trench. a doped region and a second doped region.

In one embodiment, the first opening and the second opening are staggered with each other, and forming the first opening and the second opening includes filling the first trench and the third opening with a dielectric material. two trenches; and etching to remove the dielectric material filling the first trench and the second trench in the first region to form the first opening and the second Open your mouth.

In one embodiment, the first self-aligned ion implantation process performs ion implantation in the first opening at a first tilt angle and a second tilt angle.

In one embodiment, the second self-aligned ion implantation process performs ion implantation in the second opening at a third tilt angle and a fourth tilt angle.

In one embodiment, the first tilt angle, the second tilt angle, the third tilt angle and the fourth tilt angle are each between angle θa to angle θb, θa=tan ^-1 ( Lcd/Ltr), θb=tan ^-1 (W/2Ltr), where Lcd is the width of the first opening in the second direction, Ltr is the same depth of the first opening and the second opening, W is the length of the second opening in the second direction.

In one embodiment, the manufacturing method of the semiconductor device further includes: forming a first gate and a second gate longitudinally separated from each other in the first trench in a second region adjacent to the first region. pole; in the second region, under the bottom surface of the first trench, a source contact region having the first conductivity type is formed along the first direction; in the substrate, adjacent A first source region with the first conductivity type is formed on the bottom surface of the substrate; a first base body with the second conductivity type is formed in the substrate above the first source region. region; in the substrate, adjacent to the top surface of the substrate, a second source region having the first conductivity type is formed; in the substrate, below the second source region, a second source region having the the second base region of the second conductivity type; and forming a shared drain region of the first conductivity type in the substrate between the first base region and the second base region.

In one embodiment, the manufacturing method of the semiconductor device further includes: forming a field plate and a gate that are longitudinally separated from each other in the first trench in a second region adjacent to the first region; In the second region, a source doping region having the first conductivity type is formed along the first direction under the bottom surface of the first trench; in the substrate, adjacent to the substrate On the bottom surface, a source region having the first conductivity type is formed; in the substrate, above the source region, a base region having the second conductivity type is formed; and in the substrate, above the source region, A drain region having the first conductivity type is formed above the base region.

In one embodiment, the conductive layer is formed using a self-aligned metal suicide process through the first opening and the second opening.

In one embodiment, conductive material is deposited in the first opening and the second opening to form the conductive layer.

Description of drawings

In order to make the following easier to understand, the drawings and their detailed descriptions may be referred to simultaneously when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail, and the working principles of the specific embodiments of the present invention are explained. In addition, features in the drawings may not be drawn to actual scale for the sake of clarity, and therefore the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

1A is a schematic top view of a semiconductor device according to an embodiment of the present invention, in which a frame line indicates a first region and a second region.

1B is a schematic top view of a semiconductor device according to an embodiment of the present invention, in which the frame line marks the first doped region.

1C is a schematic top view of a semiconductor device according to an embodiment of the present invention, in which the frame line marks the second doped region.

FIG. 1D is a schematic top view of a semiconductor device according to an embodiment of the present invention, in which the conductive layer is marked by a frame line.

1E is a schematic top view of a semiconductor device according to an embodiment of the present invention, in which the dotted lines mark the gate conduction paths of the adjacent third trench and the fourth trench.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line C-C’ in FIG. 1A.

3 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line B-B' in FIG. 1A.

4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line A-A’ in FIG. 1A.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line A-A’ in FIG. 1A.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line C-C’ in FIG. 1A.

FIGS. 7 , 8 , 9 , 10 and 11 are schematic cross-sectional views of various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The cross-section is along the cross-sectional tangent line C-C in FIG. 1 ', D-D' and E-E' are obtained.

FIG. 12 is a perspective view and a top view illustrating a first self-aligned ion implantation process and a second self-aligned ion implantation process according to an embodiment of the present invention.

Among them, the reference symbols are explained as follows:

100…semiconductor devices

100-1…The first area

100-2…Second area

101…Base

110…first trench

111…first gate

112…Second gate

113…field board

115…drain area

120…Second trench

130…Third trench

131…Third gate

132…another gate

134…source contact area

135…shared drain region

136…First matrix area

137…Second matrix area

138…first source region

139…Second source region

140…Fourth trench

141…Fourth gate

142…another gate

143…Heavily doped region

200, 200a, 200b, 200c…gate conduction path

210…First doped region

220…Second doping region

230, 231...conductive layer

240…dielectric materials

250…conductive plug

260…bottom conductor layer

270…top conductor layer

300…contact area

301…hard mask

303…Dielectric Liner

305…gate dielectric layer

306…Dielectric Isolation Section

307…conductive materials

309…Dielectric materials

311…first opening

312…Second opening

313…dielectric spacer layer

317…interlayer dielectric layer

319, 321…contacts

410…The first self-aligned ion implantation process

420…The second self-aligned ion implantation process

CA...interleaving area

θ1…first tilt angle

θ2…Second tilt angle

θ3…Third tilt angle

θ4…The fourth tilt angle

Ltr…same depth of first and second openings

Lcd…width of the first opening in the second direction

W…the length of the second opening in the second direction

Steps S101, S103, S105, S107, S109, S111, S113, S115, S117...

A-A’, B-B’, C-C’, D-D’, E-E’… section tangent line

Detailed ways

The invention provides several different embodiments for implementing different features of the invention. For simplicity of explanation, examples of specific components and arrangements are also described herein. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or above the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". There are other features between the features", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.

In addition, the spatially related descriptive words mentioned in the present invention, such as: "under", "low", "lower", "above", "above", "upper", "top" ", "bottom" and similar words are used to describe the relative relationship between one component or feature and another (or multiple) components or features in the diagram for the convenience of description. In addition to the orientations shown in the drawings, these spatially related terms are also used to describe possible orientations of the semiconductor device during use and operation. As the semiconductor device is oriented differently (rotated 90 degrees or at other orientations), the spatially related descriptions used to describe its orientation should be interpreted in a similar manner.

Although the present invention uses terms such as first, second, third, etc. to describe various components, components, regions, layers, and/or sections, it should be understood that these components, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one component, component, region, layer, and/or block from another component, component, region, layer, and/or block, and do not themselves imply or represent the component. There is no previous serial number, nor does it represent the order of one component relative to another, or the order of the manufacturing method. Therefore, a first component, component, region, layer, or block discussed below may also be termed a second component, component, region, layer, or block without departing from the scope of the specific embodiments of the invention. Of.

The terms "about" or "substantially" mentioned in the present invention usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even if "about" or "substantially" is not specifically stated, the meaning of "about" or "substantially" may still be implied.

The terms "coupling", "coupling" and "electrical connection" mentioned in the present invention include any direct and indirect electrical connection means. For example, if a first component is coupled to a second component, that means the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connections.

Although the invention of the present invention is described below through specific embodiments, the inventive principles of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and these omitted details fall within the scope of knowledge of those with ordinary skill in the art.

The present invention relates to a semiconductor device including a trench-type gate MOSFET and a manufacturing method thereof. The semiconductor device includes a source-base electrically connected structure in a staggered trench, and the manufacturing method includes using the opening of the trench to perform self-aligned ion implantation. The process includes forming first doping regions with impurities of the first conductivity type and second doping regions with impurities of the second conductivity type that are interleaved with each other under the bottom surface of the staggered trenches, and electrically connected to the staggered trenches. The conductive layer of the first doped region and the second doped region, wherein the first doped region and the second doped region are electrically connected to the source region (including the source contact region) and the base region of the semiconductor device respectively, and are conductive The layer can be electrically coupled to ground so that the semiconductor device has a stable threshold voltage (Vt). In some embodiments of the present invention, the number of photomasks used in the manufacturing process of the semiconductor device can be reduced to achieve the benefit of saving manufacturing costs, and the manufactured semiconductor device has the advantages of reducing chip area, increasing component layout density and reducing conduction. resistance and other advantages.

1A is a schematic top view of a semiconductor device 100 according to an embodiment of the present invention, in which the first region 100-1 and the second region 100-2 are marked by frame lines. FIG. 1B is a schematic top view of a semiconductor device 100 according to an embodiment of the present invention, in which the first doped region 210 is marked by a frame line. FIG. 1C is a schematic top view of a semiconductor device 100 according to an embodiment of the present invention, in which the frame line indicates the second doped region 220 . Referring to FIGS. 1A and 2 , the semiconductor device 100 includes a first trench 110 extending along a first direction (eg, Y direction) disposed in a substrate 101 , and a second trench 110 extending along a second direction (eg, X direction). The trenches 120 are disposed in the substrate 101, and the first trenches 110 and the second trenches 120 are staggered with each other at least in the first region 100-1. Referring to FIGS. 1B and 1C , within the first region 100 - 1 , the semiconductor device 100 further includes (1) a first doping region 210 having impurities of a first conductivity type (eg, n-type), along a first direction. (for example, the Y direction) is disposed under the bottom surface of the first trench 110, and (2) a second doping region 220 having impurities of a second conductivity type (for example, p-type), along the second direction (for example, the X direction) Disposed under the bottom surface of the second trench 120, the first doped regions 210 and the second doped regions 220 are staggered with each other. FIG. 1D is a schematic top view of a semiconductor device 100 according to an embodiment of the present invention, in which the conductive layer 230 is marked by a frame line. Referring to FIGS. 1A, 1B, 1C and 1D, the semiconductor device 100 also includes a conductive layer 230 disposed in the first trench 110 and the second trench 120 in the first region 100-1, and the conductive layer 230 is electrically connected to the first doped region 210 and the second doped region 220.

In some embodiments, as shown in FIG. 1D , the top view profile of the conductive layer 230 exhibits a cross shape. In other embodiments, the top view outline of the conductive layer 230 may be square, rectangular, circular, elliptical, polygonal or other geometric shapes, and at least a portion of the conductive layer 230 will fill the first region 100-1 in the first region 100-1. The trench 110 and the second trench 120 are disposed above the first doped region 210 and the second doped region 220 to be electrically connected to the first doped region 210 and the second doped region 220 . In some embodiments of the present invention, as shown in FIGS. 2 and 3 , the first doped region 210 is electrically connected to the source contact region 134 of the semiconductor device 100 and then electrically connected to the source region; FIG. 2 As shown in FIG. 4 , the second doped region 220 is electrically connected to the base region 136 of the semiconductor device 100 , so the conductive layer 230 , the first doped region 210 and the second doped region in the first region 100 - 1 220 may also be referred to as a source-base contact structure electrically connected, and the conductive layer 230 may be electrically coupled to the ground to stabilize the critical voltage of the semiconductor device 100 .

Referring to FIG. 1A , in addition to the first trench 110 , the semiconductor device 100 also includes a plurality of trenches extending along a first direction (eg, Y direction), such as a third trench 130 , a fourth trench 140 and others. Unnumbered trenches. In some embodiments of the present invention, between two adjacent first regions 100-1, at least one trench extending along the first direction (eg, Y direction) intersects with the second trench 120. The plurality of grooves extending along the first direction (such as the Y direction) and parallel to each other, such as the first groove 110 , the third groove 130 , and the fourth groove 140 , are marked in FIG. 1A for the convenience of illustrating different positions. Each trench may have the same structure in areas other than the first area 100-1. In addition, the structures in the first trenches 110 and the second trenches 120 that are interlaced with each other in each first region 100-1 may also be the same.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line CC' in FIG. 1A. The cross-sectional tangent line CC' is along the second direction (for example, the X direction). ), and passes through the first trench 110, the third trench 130 and the fourth trench 140 of the second region 100-2. As shown in FIG. 2 , in the first trench 110 , there are a first gate electrode 111 and a second gate electrode 112 separated from each other along the depth direction (for example, Z direction) of the first trench 110 . The dielectric isolation portion 306 is disposed between the first gate 111 and the second gate 112 , and the second gate 112 is located above the first gate 111 . Referring to FIGS. 1A and 2 , the first gate 111 and the second gate 112 in the first trench 110 of the second region 100 - 2 are in contact with the first region 100 - 1 in the first direction (for example, Y direction). The conductive layer 230 is separated. Similarly, in the third trench 130, there are a third gate 131 and another gate 132 separated from each other along the depth direction (eg, Z direction) of the third trench 130, and the dielectric isolation portion 306 is located on the third trench 130. Between the third gate 131 and the other gate 132 , the other gate 132 is located above the third gate 131 . In addition, there is also a structure similar to the third trench 130 in the fourth trench 140, which will not be repeated here.

Continuing to refer to FIG. 2 , the source contact region 134 has a first conductivity type (eg n-type) and is disposed in the first trench 110 , the third trench 130 and the fourth trench 140 along a first direction (eg the Y direction). and formed in the first source region 138 , which is adjacent to the bottom surface of the substrate 101 . The first base region 136 has a second conductivity type (for example, p-type), is disposed above the first source region 138 along a first direction (for example, the Y direction), and is located between the first gate electrode 111 and the third gate electrode 131 both sides. The second base region 137 has a second conductivity type (for example, p-type), is disposed above the first base region 136 , and is located on both sides of the second gate electrode 112 and the other gate electrode 132 . The second source region 139 has a first conductivity type (for example, n-type), is disposed above the second base region 137 , is adjacent to the top surface of the substrate 101 , and is also located on both sides of the second gate 112 and the other gate 132 . The shared drain 135 has a first conductivity type (eg, n-type), is located between the first body region 136 and the second body region 137 , and may be provided by the n-type silicon epitaxial layer of the substrate 101 . In addition, the dielectric material 309 is filled in the first trench 110 and the third trench 130 and covers the second gate electrode 112 and the other gate electrode 132 .

Continuing to refer to FIG. 2 , an interlayer dielectric layer 317 is formed on the top surface of the substrate 101 to cover the first trench 110 , the third trench 130 , the fourth trench 140 and the second source region 139 . The contact 321 is, for example, a conductive plug, which is formed in the interlayer dielectric layer 317 and extends downward through the second source region 139 to the second base region 137 . Directly below the contact 321 , a heavily doped region 143 of a second conductivity type (for example, p-type) is formed in the second base region 137 . The doping concentration of the heavily doped region 143 is higher than that of the second base region 137 . The impurity concentration facilitates the electrical contact between the contact 321 and the second base region 137 . In addition, a top conductive layer 270 is provided on the top surface of the substrate 101 and is electrically connected to the contact 321, and the second source region 139 and the second base region 137 can be electrically connected to the top conductive layer 270 via the contact 321, so that The upper MOS components in each trench can be electrically connected to other components or external circuits through the top conductive layer 270 . In addition, a bottom conductive layer 260 may be provided under the bottom surface of the substrate 101, and the conductive layer 230 of the first region 100-1 (as shown in FIG. 4) is electrically connected to the first base region 136 through the second doped region 220, The first base region 136 and the first source region 138 of the second region 100-2 are electrically connected to the bottom conductive layer 260, so that the lower MOS components in each trench can communicate with other components or external circuits through the bottom conductive layer 260. Electrical connection.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line BB' in FIG. 1A. The cross-sectional tangent line BB' is along the second direction (for example, the X direction). ), and passes through the first trench 110 of the first region 100-1, and the third trench 130 adjacent to the first region 100-1.

As shown in FIG. 3 , corresponding to the first region 100 - 1 , a first doped region 210 , a conductive layer 230 and a dielectric material 240 are formed in the first trench 110 . The first doped region 210 has impurities of a first conductivity type (for example, n-type), is disposed under the bottom surface of the first trench 110 along a first direction (for example, the Y direction), and is formed in the source region 138; The source contact region 134 in the first trench 110 outside the first region 100-1 is electrically connected to the first doped region 210. The conductive layer 230 is formed in the first trench 110 and contacts the top surface of the first doped region 210. The dielectric material 240 is filled in the first trench 110 and covers the conductive layer 230.

As shown in FIG. 3 , outside the first region 100 - 1 , in the third trench 130 , there are a third gate 131 and a third gate electrode 131 separated from each other along the depth direction (for example, Z direction) of the third trench 130 . One gate 132 and the dielectric isolation portion 306 are disposed between the third gate 131 and the other gate 132 , and the other gate 132 is located above the third gate 131 . In addition, a dielectric liner 303 is conformally formed in the third trench 130 on the inner sidewall and bottom surface of the third trench 130, surrounding the third gate 131, the other gate 132 and The dielectric isolation portion 306 and the dielectric material 309 are filled in the third trench 130 and cover the other gate 132 .

In addition, as shown in FIG. 3 , the semiconductor device further includes a source contact region 134 , for example, a heavily doped region of a first conductivity type (eg, n-type), which can be disposed between the third trench 130 and the fourth trench 140 . Under the bottom surface and formed in the first source region 138, the first source region 138 has a first conductivity type (for example, n-type) and may be composed of an n-type silicon substrate of the substrate 101, and the doping of the source contact region 134 The concentration is higher than the doping concentration of the first source region 138 . The first body region 136 has a second conductivity type (for example, p-type), is disposed in the substrate 101, is located above the first source region 138, is adjacent to the third gate electrode 131, and is respectively located on the third gate electrode 131. both sides. The second base region 137 has a second conductivity type (for example, p-type), is disposed in the substrate 101 , is adjacent to the other gate electrode 132 and is located on both sides of the other gate electrode 132 . The second source region 139 has a first conductivity type (for example, n-type), is disposed in the substrate 101, is located above the second body region 137, and is adjacent to the top surface of the substrate 101. The second source regions 139 are also located on another side. both sides of gate 132 . In addition, the shared drain region 135 is disposed between the first body region 136 and the second body region 137 . The shared drain region 135 has a first conductivity type (for example, n-type) and can be provided by the n-type silicon epitaxial layer of the substrate 101 . In addition, an interlayer dielectric layer 317 may be formed on the top surface of the substrate 101 to cover the first trench 110 , the third trench 130 and the second source region 139 , and an interlayer dielectric layer 317 may be formed. Connection structures, such as vias and wire layers, are used to electrically connect each component area.

FIG. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line AA' in FIG. 1A. The cross-sectional tangent line AA' extends along the second trench 120. And sequentially passes through a fourth trench 140, a third trench 130, the first trench 110 in the first region 100-1, another third trench 130 and another fourth trench 140; wherein the The first trench 110, the third trench 130 and the fourth trench 140 all extend along the first direction (for example, the Y direction), so they all intersect with the second trench 120; and the first trench 110, the second trench Grooves 120 , third trenches 130 and fourth trenches 140 are formed in the substrate 101 .

In some embodiments, the substrate 101 may include a semiconductor substrate having a first conductivity type, such as an n-type silicon substrate, and an epitaxial layer having a first conductivity type formed on the semiconductor substrate, such as an n-type silicon epitaxial layer formed on an n-type silicon substrate. On the silicon substrate, the doping concentration of the epitaxial layer may be lower than that of the semiconductor substrate.

Referring to FIG. 1A, FIG. 1B and FIG. 3, in one embodiment, the first doping region 210 having impurities of a first conductivity type (eg, n-type) is in the first region 100-1, along the first The direction (for example, the Y direction) is provided under the bottom surface of the first trench 110 and is formed in the substrate 101, for example, in an n-type silicon substrate, and the doping concentration of the first doped region 210 is higher than that of the n-type silicon substrate. doping concentration.

Referring to FIGS. 1A, 1C and 4, corresponding to the first region 100-1, a second doped region 220, a conductive layer 230 and a dielectric material 240 are formed in the second trench 120. In the first region 100-1, the second doping region 220 has impurities of a second conductivity type (for example, p-type) and is disposed under the bottom surface of the second trench 120 along the second direction (for example, the X direction), and Formed in the substrate 101, for example, formed in an n-type silicon substrate; the first base region 136 and the second doped region 220 on both sides of the first trench 110 outside the first region 100-1 are electrically connected.

In addition, within the first region 100-1, the conductive layer 230 is formed in the first trench 110 and the second trench 120, and within the first trench 110 and the second trench 120 of the first region 100-1 Dielectric material 240 may be filled to cover conductive layer 230. In this embodiment, the conductive layer 230 directly contacts the top surfaces of the first and second doped regions 210 and 220 , so that the conductive layer 230 is electrically connected to the first and second doped regions 210 and 220 . In addition, a bottom conductive layer 260 may be formed under the bottom surface of the substrate 101. The conductive layer 230 may be electrically connected to the bottom conductive layer 260 through an interconnection structure (not shown), such as a via hole, and be electrically coupled through the bottom conductive layer 260. Connect to ground.

Referring to FIGS. 1A and 4 , in the area between the two first areas 100 - 1 , third trenches 130 and fourth trenches may be provided that are interlaced with the second trenches and parallel to the first trenches 110 . slot 140. In some embodiments, in the third trench 130, there are a third gate 131 and another gate 132 separated from each other along the depth direction (eg, Z direction) of the third trench 130, wherein the other gate The electrode 132 is located above the third gate electrode 131 , and the dielectric isolation portion 306 is disposed between the third gate electrode 131 and the other gate electrode 132 .

1E is a schematic top view of a semiconductor device 100 according to an embodiment of the present invention, in which the dotted lines mark the gate conduction paths 200a, 200b and 200c of the adjacent third trench 130 and the fourth trench 140. Please refer to FIG. 1E and FIG. 4 . As shown in the gate conduction path 200 a of FIG. 1E , the third gate 131 and the other gate 132 in the third trench 130 are both along the first direction (for example, the Y direction). Extending into the second trench 120, and as shown in FIG. 4, the third gate 131 and the other gate 132 are both separated from the conductive layer 230 of the first region 100-1 in the second direction (such as the X direction). . In the fourth trench 140, there are also a fourth gate 141 and another gate 142 separated from each other along the depth direction (such as the Z direction) of the fourth trench 140, wherein the other gate 142 is located at the fourth gate. above the electrode 141, and the dielectric isolation portion 306 is disposed between the fourth gate 141 and the other gate 142. As shown in the gate conduction path 200b of FIG. 1E, the fourth gate in the fourth trench 140 Both the electrode 141 and the other gate electrode 142 extend into the second trench 120 along the first direction (eg, Y direction). In addition, please refer to the gate conduction path 200c of FIG. 1E and FIG. 4 , at least one of the third gate 131 and the fourth gate 141 is along the second direction (for example, the X direction) in the second trench 120 Extend so that the third gate 131 and the fourth gate 141 are electrically connected. In addition, at least one of the other gate 132 and the other gate 142 also extends in the second trench 120 along the second direction (for example, the X direction), so that the other gate 132 and the other gate 142 Electrical connection. In other embodiments, the other gate 132 and the other gate 142 may not be provided in the third trench 130 and the fourth trench 140 . In some embodiments, as shown in the gate conduction paths 200a and 200b of FIG. 1E , the third gate 131 in the third trench 130 extends along the first direction (for example, the Y direction), and in the second Trench 120 extends within. Similarly, the fourth gate 141 in the fourth trench 140 extends along the first direction (for example, the Y direction) and extends in the second trench 120 .

In addition, referring to FIG. 4 , a source contact region 134 is provided under the bottom surface of the third trench 130 and the fourth trench 140 , and in the area between the third trench 130 and the fourth trench 140 , A first base region 136 is disposed under the bottom surface of the trench 120, and the first doping region 210, the second doping region 220, the source contact region 134 and the first base region 136 are all disposed in the first source region 138. The first source region 138 may be provided by a first conductive type semiconductor substrate included in the substrate 101 , such as an n-type silicon substrate.

Referring to FIGS. 1A , 2 and 3 , in some embodiments of the present invention, multiple gates are provided along different depths in the first trench 110 (for example, a lower first gate 111 and an upper first gate 111 ). second gate electrode 112), and the plurality of gate electrodes in the first trench 110 are separated from the conductive layer 230 in the first region 100-1 in the first direction (eg, Y direction). In addition, a plurality of gate electrodes (for example, the third gate electrode 131, another gate electrode 132, the fourth gate electrode 141, and the other gate electrode 142) are respectively provided in the third trench 130 and the fourth trench 140. And the gate electrodes in the third trench 130 and the fourth trench 140 both extend into the second trench 120 along the first direction (eg, Y direction).

In addition, please refer to FIG. 1E and FIG. 4 , the gate electrode in the third trench 130 is separated from the conductive layer 230 in the first region 100 - 1 in the second direction (for example, the X direction), and the gate electrode in FIG. 1E is turned on. As shown in path 200c, the gate electrode in the third trench 130 (eg, the third gate electrode 131 and the other gate electrode 132) or the gate electrode in the fourth trench 140 (eg, the fourth gate electrode 141 and the other gate electrode) 142) At least one of them will extend along the second direction (such as the X direction) in the second trench 120, so that the gate electrode in the third trench 130 and the gate electrode in the fourth trench 140 are electrically connected. . As shown in FIG. 1A , in the area other than the first area 100 - 1 , the gate electrodes in the plurality of trenches of the semiconductor device 100 are connected to each other, forming a gate conduction path 200 marked with a dotted line. Therefore, in the first area 100 In areas other than -1, the gate electrodes in each trench can be conductive along the first direction (for example, Y direction), and the gate electrodes in each trench can also be connected in two adjacent first areas 100-1 are conductive along the extension direction of the second trench 120 (for example, the The same electrical signal synchronously turns on or off the channels of the MOS components of the semiconductor device 100 .

As shown in FIG. 1A , a plurality of first regions 100 - 1 are arranged in a plurality of rows apart from each other along a second direction (for example, the X direction):

(1) The first row above includes three first regions 100-1, which cut off the gate electrodes of the 1st, 5th and 9th Y-direction extending trenches respectively, thus maintaining the 2nd to 4th and 6th to 9th trenches. The gates of the eight trenches extending in the Y direction are electrically connected to each other.

(2) The second row below includes two first regions 100-1, which cut off the gates of the third and seventh Y-direction extending trenches respectively, thus maintaining the first to second, fourth to sixth, and third The gates of 8 to 9 trenches extending in the Y direction are electrically connected to each other.

(3) The plurality of first regions 100-1 are arranged separately from each other into the first row above and the second row below, and the Nth first region 100-1 in the upper row and the corresponding Nth first region in the lower row 100-1 are spaced apart from each other by at least one groove extending along the Y direction; for example: the first first region 100-1 in the upper row and the corresponding first first region 100-1 in the lower row are spaced apart from each other by the second Y direction extending trench. This ensures that the gate electrodes of the first to ninth Y-direction extending trenches shown in FIG. 1A are electrically connected to each other.

The second area 100-2 is located between two rows of first areas 100-1. In some embodiments, the area between two adjacent trenches of the second area 100-2 may be the contact point of the MOS component. (contact) Area 300.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line AA' in FIG. 1A. The difference between the embodiment of FIG. 5 and the embodiment of FIG. 4 is that In the embodiment of FIG. 5 , conductive plugs 250 are also disposed in the first trench 110 and the second trench 120 of the first region 100-1, which pass through the dielectric material 240 and are electrically connected to the conductive layer 230. Therefore, the conductive layer 230 can be electrically coupled to the top conductive layer 270 located on the top surface of the substrate 101 via the conductive plug 250, and can be electrically coupled to the ground via the top conductive layer 270. In addition, for components with the same numbers in the embodiment of FIG. 5 and the embodiment of FIG. 4 , please refer to the relevant description of FIG. 4 , which will not be repeated here.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. The cross-section is taken along the cross-sectional tangent line CC' in FIG. 1A. The difference between the embodiment of FIG. 6 and the embodiment of FIG. 2 is that In the embodiment of FIG. 6 , in the first trench 110 , the third trench 130 and the fourth trench 140 , along the depth direction of each trench, the first gate 111 , the third gate 131 and The fourth gates 141 are separated from each other, and above these gates is the field plate 113 . In addition, the gate dielectric layer 305 surrounds the field plate 113 , the dielectric liner 303 surrounds the first gate 111 , the third gate 131 and the fourth gate 141 , and the dielectric material 309 fills the first trench 110 and the fourth gate 113 . Inside the third trench 130 and the fourth trench 140 , and covering the field plate 113 . The source contact region 134 is disposed under the bottom surfaces of the first trench 110 , the third trench 130 and the fourth trench 140 , and is formed in the first source region 138 (also called a source region). The first base region 136 (also called the base region) is disposed above the first source region 138 and is located on both sides of the first gate electrode 111, the third gate electrode 131 and the fourth gate electrode 141, that is, the first The base region 136 is adjacent to the first gate electrode 111 , the third gate electrode 131 and the fourth gate electrode 141 . The drain region 115 has a first conductivity type (for example, n-type), is disposed in the substrate 101, is adjacent to the top surface of the substrate 101, and is located above the first body region 136. In this embodiment, the drain region 115 is adjacent to the field plate. 113. Between the drain region 115 and the first base region 136 is a part of the substrate 101 , such as an n-type silicon epitaxial layer of the substrate 101 .

Continuing to refer to FIG. 6 , the conductive layer 231 is formed on the drain region 115 . In some embodiments of the present invention, the conductive layer 231 in the second region 100 - 2 and the conductive layer 230 in the first region 100 - 2 can be formed by the same process. formed together. An interlayer dielectric layer 317 is formed on the top surface of the substrate 101 . Contacts 319 , such as conductive plugs, are formed in the interlayer dielectric layer 317 and extend downward to contact the conductive layer 231 . A top conductive layer 270 is formed on the top surface of the substrate 101 and is electrically connected to the contact 319. The drain region 115 of the MOS component can be electrically connected to other components or external circuits through the top conductive layer 270. A bottom conductive layer 260 is formed on the bottom surface of the substrate 101, which can be electrically connected to the first source region 138. The first source region 138 of the MOS component can be electrically connected to other components or external circuits through the bottom conductive layer 260. sexual connection.

7, 8, 9, 10 and 11 are schematic cross-sectional views of various stages of a manufacturing method of a semiconductor device according to an embodiment of the present invention, with the cross-section along the cross-sectional tangent line C- in Figure 1. C', DD' and EE' are obtained, in which the cross-section tangent line CC' is along the second direction (for example, the X direction) and passes through the first trench 110 and the third trench of the second region 100-2. The groove 130 and the fourth groove 140; the cross-sectional tangent line DD' is along the first direction (for example, the Y direction) and crosses the second trench 120 of the first region 100-1; the cross-sectional tangent line EE' is along oriented in the second direction (for example, the X direction) and across the first trench 110 of the first region 100-1.

First, referring to FIG. 7 , a substrate 101 is provided, and a well region of a second conductivity type (eg, p-type) is formed in the substrate 101 as the first base region 136 . Then, a patterned hard mask 301 is formed on the top surface of the substrate 101, and the openings of the hard mask 301 correspond to the areas where trenches will be formed subsequently. Referring to FIG. 7 and FIG. 1 , an etching process is used and a plurality of trenches extending along a first direction (eg, Y direction) are formed in the substrate 101 through the openings of the hard mask 301 , such as the first trench 110 , The third trench 130, the fourth trench 140, and the second trench 120 extending along the second direction (eg, X direction) are formed. Afterwards, in areas other than the first area 100-1, an ion implantation process of the first conductive type (eg, n-type) is performed on the substrate 101 through the first trench 110, the third trench 130, and the fourth trench 140, so as to A source contact region 134 is formed under the bottom surfaces of the first trench 110 , the third trench 130 and the fourth trench 140 .

Next, a dielectric liner 303 is compliantly formed on the inner sidewalls and bottom surfaces of the first trench 110, the second trench 120, the third trench 130, and the fourth trench 140. The dielectric liner 303 is, for example, Silicon oxide can be formed through a thermal oxidation process. Then, in areas other than the first region 100-1, gate material, such as polysilicon, is deposited in the first trench 110, the third trench 130 and the fourth trench 140, and the polysilicon is etched back to form the first trench 110, the third trench 130 and the fourth trench 140. Gate 111, third gate 131 and fourth gate 141. Afterwards, on the inner side walls of the first trench 110, the second trench 120, the third trench 130 and the fourth trench 140, and the bottom surfaces of the first trench 110 and the second trench 120 in the first region 100-1 A gate dielectric layer 305 is formed on and on top surfaces of the first gate 111 , the third gate 131 and the fourth gate 141 . The gate dielectric layer 305 may be made of silicon oxide. The gate dielectric layer 305 may be formed using a thermal oxidation process.

Continuing to refer to FIG. 7 , in step S101 , conductive material 307 , such as polysilicon, is deposited in the first trench 110 , the second trench 120 , the third trench 130 , and the fourth trench 140 in all areas, and then the conductive material 307 is Etch back so that the top surface of the conductive material 307 in all areas of the first trench 110 , the second trench 120 , the third trench 130 , and the fourth trench 140 is lower than the top surface of the substrate 101 .

Referring to Figure 8, in step S103, an etching process is used to remove all the conductive material 307 in the first trench 110 and the second trench 120 of the first region 100-1. During this etching process, the first region 100 Areas other than -1 can be protected by covering with a photoresist layer.

Still referring to FIG. 8 , in step S105 , a deposition process, such as high-density plasma chemical vapor deposition, is used in the first trench 110 , the second trench 120 , the third trench 130 , and the fourth trench 140 in all areas. (High density plasmachemical vapor deposition, HDP-CVD) process is used to fill the dielectric material 309, such as silicon oxide, silicon nitride or other suitable dielectric materials. Then, a chemical-mechanical planarization (CMP) process is used to remove the dielectric material 309 outside each trench, the gate dielectric layer 305 and part of the hard mask 301, so that the dielectric material 309 in each trench is removed. The top surface of electrical material 309 is flush with the top surface of remaining hard mask 301 .

Referring to FIG. 9 , in step S107 , an etching process is used to remove the dielectric material 309 , the gate dielectric layer 305 and the dielectric liner in the first trench 110 and the second trench 120 in the first region 100 - 1 303, form the first opening 311 in the first trench 110, and form the second opening 312 in the second trench 120; wherein the first opening 311 is along the direction of the first trench 110, that is, the first direction ( For example, the Y direction) extends, the second opening 312 extends along the direction of the second trench 120, that is, the second direction (for example, the X direction), and the first opening 311 and the second opening 312 are within the first region 100-1 Intertwined. During the etching process of step S107, the area other than the first area 100-1 may be covered and protected with a photoresist layer. Continuing to refer to FIG. 9 , in step S109 , a dielectric spacer 313 , such as silicon oxide, silicon nitride, or nitrogen is formed on the inner side walls of the first opening 311 and the second opening 312 in the first region 100 - 1 . Silicon oxide or a combination of the foregoing materials, a deposition process and an etching process may be used to form the dielectric spacer layer 313, and the first opening 311 and the second opening 312 still expose the first trench 110 and the first opening 312 respectively in the first region 100-1. The bottom surface of the second trench 120 is below the substrate 101 .

Please refer to FIG. 10 and FIG. 12 at the same time. FIG. 12 is a perspective view and a top view of implementing the first self-aligned ion implantation process 410 and the second self-aligned ion implantation process 420 according to an embodiment of the present invention. In step S111, a second self-aligned ion implantation process 420 is performed on the substrate 101 under the bottom surface of the second trench 120 through the second opening 312, and impurities of the second conductivity type (for example, p-type) are implanted into the substrate 101 to form a second The doped region 220 is under the bottom surface of the second trench 120 . As shown in FIG. 12 , in some embodiments of the present invention, the second self-aligned ion implantation process 420 along the second direction (for example, the X direction) first performs ion implantation in the second opening 312 at a third tilt angle θ3, And the second self-aligned ion implantation process 420 performs ion implantation in the second opening 312 at a fourth tilt angle θ4, where the order of ion implantation at the third tilt angle θ3 and the fourth tilt angle θ4 can be exchanged, and the third tilt angle The ion implantation at the angle θ3 and the fourth tilt angle θ4 is along the second direction (for example, the X direction) and two different directions relative to the same plane (for example, the XY plane). In some embodiments, the third tilt angle θ3 and the fourth tilt angle θ4 may be the same or different, and each of the third tilt angle θ3 and the fourth tilt angle θ4 is between the angle θa to the angle θb, θa=tan ^-1 (Lcd/Ltr), θb=tan ^-1 (W/2Ltr), as shown in Figure 12, where Lcd is the width of the trench top opening, that is, the width of the first opening 311 in the second direction (such as the X direction); Ltr is the trench depth, that is, the same depth of the first opening 311 and the second opening 312 in the third direction (for example, the Z direction); W is the ions along the second direction (for example, the X direction) in the first region 100-1 The extended length of the injection is the length of the second opening 312 in the second direction (for example, the X direction). The third tilt angle θ3 and the fourth tilt angle θ4 can be determined according to the required depth of the second doped region 220 of the semiconductor device. The larger the third tilt angle θ3 and the fourth tilt angle θ4 are, the larger the second doped region 220 will be. The depth of the mixed area 220 is deeper. In addition, since the range of the second doped region 220 can be determined by the range of the second opening 312, the second doped region 220 can be formed without additional photomask and photolithography processes. The ion implantation process may be called the second self-aligned ion implantation process 420 and makes the first base region 136 and the second doping region 220 electrically conductive.

Still referring to FIGS. 10 and 12 , in step S113 , a first self-aligned ion implantation process 410 is performed on the substrate 101 under the bottom surface of the first trench 110 through the first opening 311 to transfer the first conductive type (for example, n-type) Impurities are implanted into the substrate 101 to form a first doped region 210 under the bottom surface of the first trench 110 . As shown in FIG. 12 , in some embodiments of the present invention, along the first direction (for example, Y direction), the first self-aligned ion implantation process 410 first performs ion implantation in the first opening 311 at a first tilt angle θ1 , and the first self-aligned ion implantation process 410 performs ion implantation in the first opening 311 at a second tilt angle θ2, where the order of ion implantation at the first tilt angle θ1 and the second tilt angle θ2 can be exchanged, and the first The ion implantation at the tilt angle θ1 and the second tilt angle θ2 is along the first direction (for example, the Y direction) and two different directions relative to the same plane (for example, the XY plane). In some embodiments, the first tilt angle θ1 and the second tilt angle θ2 may be the same or different, and the first tilt angle θ1 and the second tilt angle θ2 are each between the angle θa and the angle θb, and the definitions of θa and θb As mentioned before. The first tilt angle θ1 and the second tilt angle θ2 can be determined according to the required depth of the first doped region 210 of the semiconductor device. The greater the angle between the first tilt angle θ1 and the second tilt angle θ2, the greater the first doping angle θ1 and the second tilt angle θ2. The depth of the mixed area 210 is deeper. In addition, since the range of the first doped region 210 can be determined by the range of the first opening 311, the first doped region 210 can be formed without additional photomask and photolithography processes. The ion implantation process may be called the first self-aligned ion implantation process 410 and makes the source contact region 134 under the bottom surface of the first trench 110 and the first doping region 210 electrically conductive.

In addition, the execution order of the first self-aligned ion implantation process 410 and the second self-aligned ion implantation process 420 can be exchanged. For example, the first self-aligned ion implantation process 410 can be performed first, and then the second self-aligned ion implantation can be performed. Craft 420. As shown in FIG. 12 , the first doped region 210 and the second doped region 220 are interleaved with each other, and the interleaved region CA contains both impurities of the second conductive type (for example, p-type) and first conductive type (for example, n-type). ) impurities.

Continuing to refer to FIG. 10 , in step S113 , after forming the first doped region 210 and the second doped region 220 , the hard mask 301 is removed. At this time, the top surface of the substrate 101 will be slightly lower than the top surface of each trench. Then, in one embodiment, an ion implantation process of a first conductivity type (eg, n-type) is performed on the top surface of the substrate 101 to form the drain region 115 as shown in FIG. 6 . In this embodiment, the first trench 110 , the third trench 130 and the fourth trench 140 located in the second region 100 - 2 are connected with the first gate 111 , the third gate 131 and the fourth gate. 141 Conductive materials separated from each other in the depth direction of each trench may serve as the field plate 113, and the field plate 113 is covered by the dielectric material 309.

In another embodiment, an ion implantation process of a second conductivity type (for example, p-type) can be sequentially performed on the top surface of the substrate 101 to form the second base region 137 as shown in FIG. 5 , and the first conductivity type can be performed. A type (for example, n-type) ion implantation process is used to form the second source region 139 above the second base region 137 as shown in FIG. 5 . In this embodiment, the first trench 110 , the third trench 130 and the fourth trench 140 located in the second region 100 - 2 are connected with the first gate 111 , the third gate 131 and the fourth gate. 141 The conductive materials separated from each other in the depth direction of each trench can serve as the second gate 112, the other gate 132 and the other gate 142 respectively, and the second gate 112, the other gate 132 and the other Gate 142 is covered by dielectric material 309 .

Referring to FIG. 11 , in step S115 , a self-aligned silicide (salicide) process or a deposition process may be used in the first trench 110 and the second trench 120 in the first region 100 - 1 , the conductive layer 230 is formed through the first opening 311 and the second opening 312, and the conductive layer 230 can contact the top surfaces of the first doped region 210 and the second doped region 220, and then be electrically connected to the first doped region 210 and the second doped region 220, and then the source contact region 134 and the first base region 136 under the bottom surface of the first trench 110, which are electrically connected to the two doped regions respectively, are electrically connected. At the same time, this self-aligned metal silicide process or deposition process will also form a conductive layer 231 on the top surface of the substrate 101. In this embodiment, the conductive layer 231 may be formed on the drain region 115 as shown in FIG. 6 . The self-aligned metal silicide process forms metal silicide by depositing a metal layer on the first doped region 210, the second doped region 220 and the drain region 115, and then performing a rapid thermal annealing (RTA) process. conductive layers 230 and 231. The deposition process uses chemical vapor deposition or physical vapor deposition to deposit conductive material in the first opening 311 and the second opening 312 to form the conductive layer 230, and also deposit the conductive material on the drain region 115 to form the conductive layer 231. .

Continuing to refer to FIG. 11 , in step S117 , a deposition process is used to fill the first trench 110 and the second trench 120 in the first region 100 - 1 with the dielectric material 240 to cover the conductive layer 230 . Then, an interlayer dielectric layer 317 is formed on the top surface of the substrate 101 , and contacts 319 , such as conductive plugs, are formed in the interlayer dielectric layer 317 , and the contacts 319 extend downward to contact the conductive layer 231 . In addition, a bottom conductive layer 260 and a top conductive layer 270 as shown in FIG. 6 may be formed on the bottom surface and the top surface of the substrate 101 respectively to complete the semiconductor device.

In some embodiments of the present invention, there is no need to increase the number of additional masks and use photolithography processes. In the body contact area of the semiconductor device, that is, the first area, the opening of the trench is used to implement self-alignment. The ion implantation process can form interleaved first doped regions with first conductive type impurities and second doped regions with second conductive type impurities under the bottom surface of the staggered trenches, where the first doped regions can The second doped region is electrically connected to the source contact region, and the second doped region can be electrically connected to the first base region. In addition, embodiments of the present invention may also use a self-aligned metal silicide process or a deposition process to form a conductive layer in the opening of the staggered trench in the base contact region to be electrically connected to the first doped region and the second doped region. Therefore, embodiments of the present invention can form a contact structure in which the source electrode located in the contact area of the base body is electrically connected to the base body. In addition, the conductive layer can be electrically coupled to the ground terminal, so that the semiconductor device has a stable threshold voltage (Vt). In some embodiments of the present invention, the manufacturing cost of the semiconductor device can be saved. At the same time, the semiconductor device of the present invention also has various advantages such as reducing chip area, increasing component layout density, and reducing on-resistance.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.

Claims (21)

1. A semiconductor device, comprising:

the first groove extends along a first direction and is arranged in a substrate;

the second groove extends along a second direction and is arranged in the substrate, and the first groove and the second groove are mutually staggered in a first area;

a first doped region having an impurity of a first conductivity type disposed in the first region along the first direction below a bottom surface of the first trench;

a second doped region having an impurity of a second conductivity type, disposed in the first region along the second direction below the bottom surface of the second trench, and the first doped region and the second doped region being staggered with each other; and

and the conductive layer is arranged in the first groove and the second groove in the first area and is electrically connected to the first doping area and the second doping area.

2. The semiconductor device according to claim 1, wherein a top view profile of the conductive layer is cross-shaped and is in direct contact with top surfaces of the first doped region and the second doped region.

3. The semiconductor device according to claim 1, further comprising:

a first gate disposed in the first trench and located in a second region adjacent to the first region;

a source contact region having the first conductivity type and disposed below the bottom surface of the first trench along the first direction in the second region, wherein the first doped region is electrically connected to the source contact region;

a first source region having the first conductivity type and disposed in the substrate and adjacent to the bottom surface of the substrate; and

the first substrate region is provided with the second conductive type, is arranged in the substrate, is arranged above the first source region along the first direction in the second region, and is electrically connected with the first substrate region.

4. The semiconductor device according to claim 3, further comprising:

the second grid electrode is arranged in the first groove and is positioned in the second area, and the first grid electrode and the second grid electrode are separated from each other along the depth direction of the first groove;

A second source region of the first conductivity type disposed within the substrate and adjacent to a top surface of the substrate;

a second substrate region having the second conductivity type, disposed in the substrate and under the second source region; and

and a shared drain region of the first conductivity type disposed in the substrate and between the first body region and the second body region.

5. The semiconductor device according to claim 4, wherein the first gate electrode and the second gate electrode are separated from the conductive layer in the first direction.

6. The semiconductor device according to claim 3, further comprising:

a third groove, which is arranged in the substrate and is positioned between the two first areas, is parallel to the first groove and is staggered with the second groove; and

a third gate disposed in the third trench and extending into the second trench along the first direction,

wherein the third gate is separated from the conductive layer in the second direction.

7. The semiconductor device according to claim 6, further comprising:

A fourth groove, which is arranged in the substrate and is positioned between the two first areas, is parallel to the first groove and is staggered with the second groove; and

a fourth grid electrode arranged in the fourth groove and extending into the second groove along the first direction,

at least one of the third gate and the fourth gate extends along the second direction in the second trench, so that the third gate and the fourth gate are electrically connected.

8. The semiconductor device according to claim 6, further comprising:

another gate electrode disposed in the third trench, the another gate electrode and the third gate electrode being separated from each other along a depth direction of the third trench, the another gate electrode extending into the second trench along the first direction,

wherein the other gate is separated from the conductive layer in the second direction.

9. The semiconductor device according to claim 3, further comprising:

a field plate disposed in the first trench and separated from the first gate along a depth direction of the first trench; and

And a drain region of the first conductivity type disposed in the substrate and over the first body region.

10. The semiconductor device of claim 1, further comprising a dielectric material filled in the first trench and the second trench of the first region and covering the conductive layer.

11. The semiconductor device of claim 10, wherein the conductive layer is electrically connected to a bottom conductive layer below the bottom surface of the substrate, and the bottom conductive layer is electrically coupled to ground.

12. The semiconductor device of claim 10, further comprising a conductive plug disposed within the first trench and the second trench of the first region through the dielectric material and electrically connected to the conductive layer.

13. A method for manufacturing a semiconductor device, comprising:

providing a substrate;

forming a first groove and a second groove in the substrate, wherein the first groove extends along a first direction, the second groove extends along a second direction, and the first groove and the second groove are mutually staggered in a first area;

Performing a first self-aligned ion implantation process of a first conductivity type on the substrate through a first opening of the first trench in the first region to form a first doped region below the bottom surface of the first trench;

performing a second self-aligned ion implantation process of a second conductivity type on the substrate through a second opening of the second trench in the first region to form a second doped region below the bottom surface of the second trench; and

and forming a conductive layer in the first groove and the second groove in the first area, wherein the conductive layer is electrically connected to the first doping area and the second doping area.

14. The method for manufacturing a semiconductor device according to claim 13, wherein the first opening and the second opening are staggered with each other, and wherein forming the first opening and the second opening comprises:

filling the first trench and the second trench with a dielectric material; and

etching to remove the dielectric material filled in the first and second trenches in the first region to form the first and second openings.

15. The method of claim 13, wherein the first self-aligned ion implantation process performs ion implantation at a first tilt angle and a second tilt angle in the first opening.

16. The method of claim 15, wherein the second self-aligned ion implantation process performs ion implantation at a third tilt angle and a fourth tilt angle in the second opening.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the first inclination angle, the second inclination angle, the third inclination angle, and the fourth inclination angle are each between an angle θa to an angle θb, θa=tan ^-1 (Lcd/Ltr)，θb＝tan ^-1 (W/2 Ltr), wherein Lcd is the width of the first opening in the second direction, ltr is the same depth of the first opening and the second opening, and W is the length of the second opening in the second direction.

18. The method for manufacturing a semiconductor device according to claim 13, further comprising:

forming a first gate and a second gate longitudinally separated from each other in the first trench in a second region adjacent to the first region;

Forming a source contact region of the first conductivity type along the first direction under the bottom surface of the first trench in the second region;

forming a first source region of the first conductivity type in the substrate adjacent to a bottom surface of the substrate;

forming a first body region of the second conductivity type over the first source region in the substrate;

forming a second source region of the first conductivity type within the substrate adjacent a top surface of the substrate;

forming a second body region of the second conductivity type in the substrate below the second source region; and

a shared drain region of the first conductivity type is formed within the substrate between the first body region and the second body region.

19. The method for manufacturing a semiconductor device according to claim 13, further comprising:

forming a field plate and a grid longitudinally separated from each other in the first groove in a second area adjacent to the first area;

forming a source doped region of the first conductivity type along the first direction under the bottom surface of the first trench in the second region;

Forming a source region of the first conductivity type within the substrate adjacent a bottom surface of the substrate;

forming a body region of the second conductivity type over the source region in the substrate; and

a drain region of the first conductivity type is formed in the substrate above the body region.

20. The method for manufacturing a semiconductor device according to claim 13, wherein the conductive layer is formed by a salicide process through the first opening and the second opening.

21. The method of manufacturing a semiconductor device according to claim 13, wherein a conductive material is deposited in the first opening and the second opening to form the conductive layer.