Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc., are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
Fig. 1 is a block diagram of a point-to-point laser communication system, referring to fig. 1, the coding and decoding principles in the laser communication system can be summarized as follows:
The original data u is subjected to channel coding to generate a coding sequence c, and the code sequence c is subjected to PPM modulation to obtain an optical pulse x. Wherein, the channel coding and PPM modulation can be summarized as a transmitting end. The optical pulses pass through a channel (which may be, but is not limited to, a poisson channel) and reach the receiving end in the form of photons. And a photon detector included in the receiving end counts the arriving photons to obtain photon counts y corresponding to the light pulses x. The receiving end uses y to make soft decision or hard decision, calculates Log Likelihood Ratio (LLR) to obtain symbol LLR, then makes PPM demodulation and channel decoding to symbol LLR gamma (y) to finally obtain the predicted value of original data It should be further explained that PPM demodulation may also be referred to as PPM decoding. In practical application, the independent PPM demodulator and the independent channel decoder can be selected to perform PPM demodulation respectively according to a specific coding and decoding scheme, or the integrated decoder can be selected to perform PPM demodulation and channel decoding simultaneously.
In the point-to-point laser communication system model shown in fig. 1, pulse position modulation, PPM modulation and PPM demodulation are key elements affecting the computational complexity and error performance of the coding and decoding.
Wherein PPM modulation is the use of the relative position of a single pulse over a period of time to communicate information. In an M-bit PPM (M-PPM, also known as M-order PPM, m=log 2 M > 1) modulation system, every M bits of information c= [ c 1,c2,...,cm ] are mapped onto one PPM symbol x. The transmission of one PPM symbol requires the occupation of M time slots (unit time), only one of which transmits an optical pulse whose position of occurrence represents the value of c. Thus x can be written as a pulse sequence of M bits x= [ x 1,x2,...,xM ], where x i = {0,1} represents the i-th slot of the symbol with no/no optical signal. The one-to-one mapping of values of c to light pulse positions may use a variety of mapping schemes such as natural order mapping, gray (Gray) mapping, inverse Gray (anti-Gray) mapping. In the embodiment of the invention, the PPM modulation uses natural sequence mapping without special description.
Natural order mapping PPM: given bit information c= [ c 1,c2,...,cm ], performing bit-wise decimal calculation (c 1 is the most significant bit) to obtain a symbol valueC is more than or equal to 0 and less than or equal to M-1. The pulse sequence of the PPM symbol corresponding to C is x= [ x 1,x2,...,xM],xC+1=1,x1≤i≤M,i≠C+1 =0, that is, in the 1 st to M-th slots of one PPM symbol, the c+1st slot transmits the optical pulse, and the rest slots do not transmit the pulse.
Considering one PPM symbol, the photon number sequence detected by the receiving end in each time slot is denoted as y= [ y 1,y2,...,yM ]. The receiving end first performs soft decision calculation using y to obtain a time slot transition probability Pr { y i|xi }, then calculates a symbol transition probability Pr { y|c } and a symbol log likelihood ratio (LLR,) Where log represents the natural logarithm if no additional base is noted. Symbol LLR Γ (y) = { Γ C (y): 0.ltoreq.C.ltoreq.M-1 will be the input to the decoder. For an ideal poisson channel, the exact symbol LLR may be calculated using Γ C(y)=yC+1·log(1+ns/nb), note that the symbol LLR calculation formula may be different in an actual system, but the definition of the symbol LLR is unchanged. For example, the symbol LLR calculation formula may be Γ C(y)=yC+1 or Γ C(y)=(yC+1-y0)·log(1+ns/nb).
In addition, for PPM demodulation, the embodiment of the present invention describes computation of PPM demodulation or PPM decoding depending on only channel information (i.e., the received signal y). It is to be understood that the following description is intended to be illustrative, and not restrictive.
Symbol set definition: order theRepresenting the aggregate set of all PPM symbols. Several are defined belowIs a subset of: order theRepresenting a collection of symbols satisfying a value of 0 for the ith bit position,Representing a collection of symbols satisfying the value 1 of the ith bit position,Examples: for the purpose of 8-PPM,
Bit C i is calculated using symbol transition probability Pr { y|c } (i=1, 2.,. M) bit transition probability Pr { y|c i=0}、Pr{y|ci =1 } and bit LLR when 0, 1, respectivelyThe detailed definition is as follows:
Operator max * defines: max * represents addition calculation in a natural logarithmic domain (hereinafter referred to simply as logarithmic domain). I.e., a+b=c, the corresponding calculation in the logarithmic domain is max * (log (a), log (b))=log (c). Then represents the running-in of x to satisfy the condition.
Convolutional codes are a widely used coding scheme. Its main feature is that the continuously input information sequence u gets the continuously output coded sequence v. For a convolutional code of input length k bits, output length n bits, constraint length α, registers in the encoder may hold a fraction of the values during encoding at α -1 consecutive instants. The encoder sequentially inputs k bits in the information sequence u at time t, and decides the values of n output bits together according to the input at time t and the data (the values stored in the register are called encoder states) stored in the register and related to time t-alpha+1 to time t-1, and updates the values of the register. In other words, the output at time t is related to the input information from time t- α+1 to time t.
The encoding process of the convolutional code can be represented by a trellis diagram. Each column of points in the trellis diagram represents a time-wise encoder state, a connection between states represents a state transition, and a numerical label on the connection represents an input/output corresponding to the state transition. A trellis diagram for a common (5, 7) convolutional code is shown in fig. 2.
Convolutional codes typically use trellis-based decoding algorithms, the Viterbi algorithm and the BCJR algorithm being the most representative. The calculation process of the two decoding algorithms is closely related to the structure of the grid graph, so that the calculation complexity of the two decoding algorithms is also linearly and positively related to the edge number (the total number of connecting lines between states at two moments) of the grid graph, namely, the decoding complexity is O (2 α-1·2k).
SCPPM coding is a scheme for PPM coding, and the structural schematic of the SCPPM coder is shown in FIG. 3. First, SCPPM encoder inputs data u of length K, and generates bit sequence v of length n=k/R using a convolutional code encoder of code rate R. The bit interleaver then rearranges the bits in v to v'. The accumulator input v' generates a bit sequence c of the same length. Finally, C obtains K/(mR) PPM symbol sequences C and corresponding MK/(mR) time slot pulse sequences x through a PPM encoder.
SCPPM the outer code encoder is a convolutional code. In general, the convolutional code may use a convolutional code having an arbitrary code rate of less than 1. In the embodiment of the invention, the common convolution code with the code rate of 1/2 and the generation formula of (5, 7) is considered to be used. The convolutional code structure is shown in fig. 4, where D represents a register,Representing a binary addition (modulo-2 addition) operation. Given the input bit sequence u= [ u 1,u2,...,uK ] of the (5, 7) convolutional code, at time t, the encoder inputs u t, outputting two bitsAndFinally, the total output bit stream of the convolutional code encoder is v= [ v 1,1,v1,2,v2,1,v2,2,...,vK,1,vK,2 ].
The block diagram of the coding structure of the accumulator is shown in fig. 5. The accumulator can be regarded as a special convolutional code with a code rate of 1 (1 bit is input and 1 bit is output at each moment), and the generation formula can be written as 1/(1+D). Given an input sequence v '= [ v 1,v2,...,vN ], an output sequence c' = [ c 1,c2,...,cN ], where c 1=u1,
For PPM (M-PPM) with m=2 m bits, the PPM encoder inputs C (m-1)t+1,c(m-1)t+2,...,cmt at time t, outputs C t=bi2de([c(m-1)t+1,c(m-1)t+2,...,cmt).
The SCPPM structure is peculiar in that the accumulator and PPM encoder of the inner code portion can also be considered as a whole, called APPM encoder. By considering the inner code portion as two separate structures or as a whole, different decoding schemes can be implemented correspondingly.
When using a PPM encoder with m=2 m bits, the APPM encoder combines the successive M-time operations of the accumulator and regards it as an equivalent M-bit APPM encoder (M-APPM), i.e. the M-APPM encoder inputs v (m-1)t+1,v(m-1)t+2,...,vmt at time t, immediately outputting the PPM symbol C t. Correspondingly, the receiving end will directly use the PPM symbol LLR Γ C (y) to decode based on the trellis diagram using M-APPM.
In the M-APPM trellis, given the encoder state s 1 = a at the current time, there are 2 m outputs that can cause the encoder to transition to the same state s 2 = b at the next time. In other words, each pair of state transitions (a→b) contains 2 m parallel sides.
As an example, the accumulator grid and 4-APPM grids are shown in fig. 6 and 7. The accumulator grid spanning m=2 times (t=1 to t=3) is merged into a 4-APPM grid spanning 1 time (t=1 to t=2), i.e. the state transitions a→b→c in the accumulator grid are merged into a state transition a→c in the 4-APPM grid. Note that a→0→c and a→1→c in the accumulator grid, although the corresponding inputs/outputs are different, can be combined into a→c in the 4-APPM grid, both of which are referred to as parallel edges of a→c.
The inventors have found that APPM coding schemes suffer from the disadvantage that the complexity of M-APPM coding is positively correlated with the modulation order. Specifically, the calculation complexity and the number of sides of the mesh are in a linear relationship O (2·2 m). For example, the number of sides of the trellis diagram of 16-APPM is 2×16=32, the number of sides of the trellis diagram of 4-APPM is 2×4=8, and the number of sides of the accumulator trellis diagram is 4, so the computational complexity of the 16-APPM decoding is about 4 times that of the 4-APPM decoding, and 8 times that of the accumulator decoding.
In view of this, the inventors have attempted to develop a low complexity decoding scheme, i.e., a single bit demodulation scheme. The scheme demodulates the received PPM symbol to obtain bit LLR corresponding to the check bit stream cAs decoder input. The decoder then performs iterative decoding between the accumulator and the convolutional code.
The disadvantage of the single bit demodulation scheme is poor error performance. For higher order modulation, the demodulation of the received symbols to bit LLRs inevitably results in information loss, and thus decoding error performance loss.
Referring to fig. 8, when m=16 and nb=0.1, the single bit demodulation scheme has a performance loss of 1dB with respect to the APPM coding scheme.
Delay BICM (DBICM) is a common coded modulation scheme for higher order modulation, without specifying specific coding and modulation formats. The scheme introduces feedback information output from the decoder to the demodulator at the receiving end, so that the information loss when demodulating the received symbols to obtain bit LLR can be reduced to a certain extent.
The transmitting end of DBICM is shown in fig. 9. The code may be any channel code, and the modulation may be any kind of higher order modulation. At time t, the bit sequence of the t-th code block c (t) (interleaved) is divided into m equal-length sub-sequences c (t, 1), c (t, m), where at most m-1 sub-sequences are delayed for transmission at a later time. The sub-sequence which is not delayed is modulated and transmitted together with the sub-sequence which is reserved to the current moment by the delay module in the previous code word. Specifically, the subsequence sent at time t is c (t- δ 1,1),...,c(t-δm, m), at least one value equal to 0 (i.e., the subsequence not delayed in c (t)) must be included in the delay bit number δ= { δ 1,...,δm } and the remaining values are greater than 0 (i.e., the sequence delayed in the previous codeword). Upon modulation, each sub-sequence will map to a fixed bit in the modulation symbol.
The processing flow of DBICM at the receiving end is shown in fig. 10. The received signal y (t) at each instant is demodulated with the feedback information of the previously decoded successful code block to obtain the log-likelihood ratio (LLR) result Γ (c (t- δ 1,1)),...,Γ(c(t-δm, m)) of the sub-sequence. After the LLR results Γ (c (t)) of all sub-sequences of c (t) are completely received, the receiving end decodes the code block and decodes the soft decision or hard decision decoding resultAnd fed back to the demodulator to assist in demodulation of the subsequent signal. Therefore, the decoding information of each code block can be coupled with other code blocks at the symbol level, and the feedback information of the demodulator is utilized to assist the demodulation of other code blocks, so that the overall decoding error performance is improved.
DBICM, the selection of delay sub-symbols and delay time has an impact on decoding error performance. Meanwhile, the receiving end adopts hard decision or soft decision feedback information when demodulating, and whether iterative demodulation is performed or not can also influence the overall decoding error performance.
The disadvantage of this scheme is that if the coded portion of SCPPM (convolutional code + accumulator) is directly brought into the encoder at the transmitter end of DBICM, the inner code does not have the APPM structure and therefore the decoder can only use the bit-level decoding scheme and not the APPM decoding scheme. Therefore DBICM performance, while improved over single bit demodulation schemes, is still a gap from SCPPM coding.
In view of the above, in the case of high-order modulation, the complete independent processing of demodulation and decoding as two steps inevitably results in an error performance loss, while the complexity of the (demodulation+decoding) integrated processing is high. For SCPPM, the APPM coding scheme with high error performance is highly complex, but the single bit demodulation scheme with low complexity has excessive error performance loss.
In view of the above, an embodiment of the present invention proposes an improved coding modulation scheme based on SCPPM, called delay SCPPM (hereinafter abbreviated as DSCPPM), and a corresponding demodulation and decoding scheme. Overall, DSCPPM achieves better error performance than SCPPM single bit demodulation scheme in the case of APPM decoding where the inner code decoding complexity is significantly less than SCPPM, and in some cases can achieve error performance approaching that of APPM decoding of SCPPM.
Consider the case where multiple codewords { c (T) |t=1, 2,..t } need to be transmitted consecutively. For SCPPM, c (t) directly performs PPM modulation to obtain a symbol sequence x (t). For DSCPPM, we split each codeword c (t) into multiple sub-symbol sequences { S (t, i) |i=1, 2,..m' }, and delay part of the sub-sequences for modulation with the sub-sequences of the subsequent codewords. Thus, each symbol sequence x (t) will contain a plurality of sub-symbol sequences from different codewords.
At the receiving end, the received signal y (t) at each moment can utilize the feedback information of the code block decoded successfully before to assist demodulation, and a Log Likelihood Ratio (LLR) result of the subsequence is obtained. After all the LLRs of sub-sequences of c (t) are completely received, the receiving end decodes the code block and feeds back the soft decision or hard decision decoding result to the demodulator to assist in demodulation of the subsequent signal.
Referring to fig. 11 and 12, the present invention provides a delay serial cascade pulse position modulation system, which includes a transmitting end and a receiving end. The transmitting end comprises a coding module, a transmitting terminal symbol sequence segmentation module, a sub-symbol interleaving module, a delay module, a sub-symbol sequence merging module and a PPM modulation module which are sequentially connected. The receiving end comprises a PPM sub-symbol demodulation module, a receiving terminal symbol sequence segmentation module, a reverse delay module, a sub-symbol de-interleaving module, a decoding module and a feedback module which are connected with the decoding module and the PPM sub-symbol demodulation module in sequence.
The coding module receives the original data sequence, and outputs a code word sequence after coding. The transmission terminal symbol sequence division module outputs a sub-symbol sequence based on the codeword sequence. The sub-symbol interleaving module receives the sub-symbol sequence corresponding to each codeword, interleaves the bit sequences in the sub-symbol sequences, and outputs an interleaved sub-symbol sequence. The delay module is configured with delay parameters, the interleaving sub-symbol sequence is input into the delay module at preset time, and the delay interleaving sub-symbol sequence is output after the delay parameters are reached. The sub-symbol sequence combining module receives the delay interleaving sub-symbol sequences at preset moments and combines all the delay interleaving sub-symbol sequences into a delay codeword sequence. The PPM modulation module receives the delayed codeword sequence and performs M-PPM modulation to output a PPM symbol sequence.
The PPM sub-symbol demodulation module is configured with prior information, receives a received signal corresponding to the PPM symbol sequence, and determines a sub-symbol log-likelihood ratio by using the prior information and the received signal. The receiving terminal symbol sequence dividing module receives the sub-symbol log-likelihood ratio, divides and then combines the sub-symbol log-likelihood ratio into a sub-symbol log-likelihood ratio sequence. The reverse delay module caches the sub-symbol log-likelihood ratios, and outputs the sub-symbol log-likelihood ratios to the sub-symbol de-interleaving module after collecting all the sub-symbol log-likelihood ratios. The sub-symbol de-interleaving module de-interleaves the sub-symbol log-likelihood ratio sequences respectively, and outputs de-interleaved sub-symbol log-likelihood ratios. The decoding module outputs a decoding result and a sub-symbol feedback sequence based on the deinterleaved sub-symbol log-likelihood ratio. The sub-symbol feedback sequence is sent to the PPM sub-symbol demodulation module through the feedback module, and the sub-symbol feedback sequence and the received signal participate in the demodulation and decoding process together in the next demodulation and decoding period.
As a possible implementation manner, the coding module in this embodiment may specifically include convolutional code coding, bit interleaving, and accumulator shown in fig. 3. The coding module receives an original data sequence, and the coded output codeword sequence is specifically executed as follows: all data u (1), u (2), u (T) are encoded separately, resulting in codewords c (1), c (2), c (T).
As one possible implementation manner, the transmitting terminal symbol sequence dividing module outputs a sub-symbol sequence based on the codeword sequence specifically includes: the transmitting terminal symbol sequence segmentation module receives the codeword sequences, segments each codeword in the codeword sequences into bit sequences, and then merges the bit sequences into sub-symbol sequences.
As an example, a transmit terminal symbol sequence segmentation module (S/P for short) segments c (T) into m bit sequences c (T, 1) for codeword c (T), 1.ltoreq.t.ltoreq.t, and then merges into sub-symbol sequences S (T, 1). The bit sequence dividing mode is as follows: assuming c (t) = [ c 1,c2,...,cN ], thenN is an integer multiple of m. The sub-symbol sequence combining mode is as follows: given the sub-symbol segmentation scheme d, the i-th sub-symbol sequence is S (t, i) = [ c (t, d i-1,sum+1);...;c(t,di,sum) ].
For example, for 16-PPM, d= (2|2), c (t) = [ c 1,c2,...,cN ] is first split into 4 bit sequences c(t,1)=[c1,c5,...,cN-3],c(t,2)=[c2,c6,...,cN-2],c(t,3)=[c3,c7,...,cN-1],c(t,4)=[c4,c8,...,cN]. sub-symbol sequences:
I.e. the i-th bit in c (t, 1) and the i-th bit in c (t, 2) correspond to the i-th sub-symbol in S (t, 1), i.e. the i-th bit in c (t, 3) and the i-th bit in c (t, 4) correspond to the i-th sub-symbol in S (t, 2).
As a possible implementation manner, the sub-symbol interleaving module interleaves the bit sequences in the sub-symbol sequence according to the following interleaving principle, so as to output an interleaved sub-symbol sequence:
the interleaving coefficients used for bit sequences belonging to different sub-symbol sequences are different;
bit sequences belonging to the same sub-symbol sequence use the same interleaving coefficients.
As an example, given the sub-symbol segmentation scheme d, bit sequences are interleaved separately. The bit sequences belonging to different sub-symbol sequences are different in the interleaving sequence used, and the bit sequences belonging to the same sub-symbol sequence are the same interleaving sequence. The resulting sequence after interleaving c (t, i) is denoted as c π(t,i),Sπ(t,i)=[cπ(t,di-1,sum+1);...;cπ(t,di,sum).
For example, for 16-PPM, d= (2.sub.2). Bit interleaving c (t, 1) and c (t, 2) respectively by using an interleaving coefficient 1 to obtain c π(t,1)、cπ (t, 2); bit interleaving is performed on c (t, 3) and c (t, 4) using interleaving coefficient 2, respectively, to obtain c π(t,3)、cπ (t, 4) (interleaving coefficient 1 and interleaving coefficient 2 are different). Equivalently, interleaving the S (t, 1) in units of sub-symbols using the interleaving sequence 1 to obtain S π (t, 1); s π (t, 2) is obtained by interleaving S (t, 2) with interleaving sequence 2 in sub-symbol units.
As a possible implementation, the delay module is configured with delay parameters based on the following principle:
after determining the number of sub-symbol sequences contained in the PPM modulation module and the code word, the delay parameter satisfies the following conditions:
And for the delay parameter corresponding to the ith sub-symbol sequence, wherein the delay parameter is a non-negative integer, the minimum delay parameter in all delay parameters corresponding to all sub-symbol sequences is zero, and the maximum delay parameter is greater than zero and less than the number of the sub-symbol sequences of the code word, wherein i is greater than or equal to 1 and less than or equal to the number of the sub-symbol sequences. For example, if a codeword contains 3 sub-symbol sequences, the delay parameter may have values of 0, 1, and 2, and the maximum value does not exceed 2.
The number of delay parameters is equal to the number of sub-symbol sequences contained in the code word, i.e. one of the sub-symbol sequences corresponds to one of the delay parameters.
As an example, the delay parameter δ= [ δ 1,δ2,...,δm′ ] of a given delay module. At time t, the delay module buffers the sub-symbol sequence S π(t,1),...,Sπ (t, m '), after which the delay module outputs the sub-sequence S π(t-δ1,1),...,Sπ(t-δm′, m'). In other words, S π (t, i) is input to the delay module at time t, and output by the delay module at time t+δ i.
As an example, the delay parameter δ value is determined as follows:
Given M-PPM and sub-symbol segmentation scheme d= (d 1|d2|...|dm′). The delay parameter δ= [ δ 1,δ2,...,δm ] needs to satisfy the following condition.
For 1.ltoreq.i.ltoreq.m, δ i is a non-negative integer and at least one of δ 1,δ2,...,δm must be 0 (min (δ) =0), but not all values are zero (max (δ) > 0).
The maximum delay parameter must be greater than zero and less than the number of sub-symbol sequences, 0 < max (delta) < m'.
Examples: for 16-PPM, d= (2|2), the delay parameter δ may be [0,1] or [1,0], but not [0,2] (condition 2 is not met, consuming more cache but not providing additional improvement in error performance). For 64-PPM, schemes { d= (2|2|2), δ= [0,1,2] }, { d= (2|2|2), δ= [0,1] }, { d= (3|3), δ= [0,1] }, { d= (2|4), δ= [0,1] }, and the like can be used.
For convenience of description, given a pair of sub-symbols+delay parameters { d, delta }, the transmission sequence may be abbreviated asWhere D i represents the sequence number of a sub-sequence at a delay value of i, e.g., D i contains sub-sequences that are assigned to different sub-symbols, which are divided by brackets [ ] sub-symbols. Examples: { (2.sub.2), [0,1] } can be written asExamples: { (2.sub.2.sub.2), [0,1] } can be written as
As a possible implementation, the sub-symbol sequence combining module combines the delay module outputs c π(t-δ1,1),...,cπ(t-δm, m) at time t into one sequence c δ (t). The dividing mode is as follows: assume c π(t-δi,i)=[ci,1,ci,2.+ -. The combined sequence is c δ(t)=[c1,1,c2,1,...,cm,1,c1,2,c2,2,...,cm,2.].
As a possible implementation manner, the PPM modulation module performs M-PPM modulation on the sequence c δ (t) to generate a PPM symbol sequence x (t).
It should be further explained that when the transmitting end needs to transmit T sets of data u (1), u (2), u (T), the t+δ max sets of symbol sequences x (1), x (2), x (t+δ max).δmax =max (δ) are actually required to be transmitted.
As a possible implementation manner, the PPM sub-symbol demodulation module determines a sub-symbol log likelihood ratio by using the prior information and the received signal, and specifically includes:
For a sequence of sub-symbols satisfying a delay parameter equal to a maximum delay parameter, sub-symbol log likelihood ratios are determined using the received signal;
for a sequence of sub-symbols satisfying a delay parameter less than a maximum delay parameter, the sub-symbol log likelihood ratios are determined jointly using the received signal and a priori information.
For example, the receiving end needs to transmit T groups of data u (1), u (2), u (T), and the detailed coding scheme of DSCPPM with the modulation bit number M is as follows:
PPM sub-symbol demodulation module: when the transmitting end transmits x (t), the receiving end receives a corresponding signal y (t). Given a delay parameter δ= [ δ 1,δ2,...,δm],δmax =max (δ). The PPM sub-symbol demodulator uses y (t) and a priori information Γ a(Sπ(t-δi, i) to calculate sub-symbol LLR Γ (S π(t-δi, i)), i=1, 2.
For the sub-symbol sequence S π(t-δi, i satisfying δ i=δmax, its sub-symbol LLR Γ (S π(t-δi, i)) is calculated using only the received signal y (t) (no a priori information).
For the sub-symbol sequence S π(t-δi, i satisfying δ i<δmax, its sub-symbol LLR Γ (S π(t-δi, i)) is calculated using the received signal y (t) and a priori information { Γ a(Sπ(t-δj,j))|δj>δi }.
As a possible implementation, the inverse delay module stores all received sub-symbol LLRs in a buffer, and outputs them to the deinterleaver after the set of the buffer { Γ (S π (t, i))|i=1, 2,..m' }.
As one possible implementation, the sub-symbol de-interleaving module de-interleaves Γ (S π(t,1)),...,Γπ (t, m ')) to obtain Γ (S (t, 1)),/i (S (t, m')).
As a possible implementation manner, the decoding module inputs Γ (S (t, 1)),..Γ (S (t, m')), and outputs a hard-decision decoding resultAnd the sub-symbol feedback Γ a(S(t,1)),...,Γa (S (t, m')). Note that: there are a number of feedback ways, examples of which are listed below:
feedback sub-symbol soft-decision LLR (decoder extrinsic information LLR).
Feedback sub-symbol hard decisions
In the case where u (t) contains CRC check bits: and transmitting sub-symbol hard decisions if the CRC check (system judgment and decoding are successful) is passed, and transmitting soft decision LLR if the CRC check (system judgment and decoding are not passed).
In the case where u (t) contains CRC check bits: and transmitting sub-symbol hard decisions when the CRC check is passed, and taking 0 (without effective feedback) for all feedback values when the CRC check is not passed.
The feedback LLR is interleaved to obtain Γ a(Sπ(t,1)),...,Γa(Sπ (t, m'), and buffered in a delay module.
As one possible implementation manner, the method of PPM sub-symbol demodulation is as follows:
feedback information-free (sub-symbol demodulation with received symbol y only):
Sub-symbol set definition: order the Representing the aggregate set of all PPM symbols.Representing the aggregate of symbols of value j satisfying the ith sub-symbol (S i) among all PPM symbols, namely:
Assuming that the PPM sub-symbol demodulator has only symbol LLR Γ C (y) from the channel, the sub-symbol LLR is calculated as: The number of LLRs corresponding to the sub-symbol is 2 d (d is the sub-symbol bit length), i.e., the value range of the sub-symbol is j e {0, 1..2 d -1}. Examples: assuming that the sub-symbol S i contains 2 bits, S i has 4 LLR values: Γ (S i)={ΓS(i),0,ΓS(i),1,ΓS(i),2,ΓS(i),3).
Soft decision feedback information, assuming PPM sub-symbol demodulator with channel LLR Γ C (y) and a priori sub-symbols The calculation formula of the sub-symbol LLR (posterior) is: Wherein the method comprises the steps of The calculation formula of the sub-symbol LLR (extrinsic information) is:
examples: for 16-PPM, d= (2|2), given c=13, then
Hard decision feedback information, assuming that the PPM sub-symbol demodulator has hard decisions of channel LLR Pr { y|C } and sub-symbol S i at the same timeThe calculation formula of the sub-symbol LLR (posterior) is: note that: when the sub-symbol demodulator is known The decoder no longer recalculates Γ S(i),j, i.e. k+.i.
As a possible implementation manner, the feedback module includes a feedback sub-symbol interleaving unit and a feedback delay unit which are sequentially connected; the feedback sub-symbol interleaving unit receives the sub-symbol feedback sequence and then interleaves the sub-symbol feedback sequence to output an interleaved sub-symbol feedback sequence; the feedback delay unit is configured with delay parameters, the interleaving sub-symbol feedback sequence is input to the feedback delay unit at preset time, and the interleaving sub-symbol feedback sequence is output after the delay parameters are reached; in the next decoding period, the delay interleaving sub-symbol feedback sequence and the received signal participate in the demodulation decoding process together.
The following details the execution of the receiving end with specific examples, and it should be understood that the following examples are given by way of example only and not by way of limitation.
Referring to fig. 13, consider { d= (2|2|2), δ= [0,1,2] }. As shown in fig. 13, three sub-symbol sequences S (t, 1), S (t, 2), S (t, 3) corresponding to c (t) are transmitted in x (t), x (t+1), x (t+2), respectively. In other words, x (t) includes S (t, 1), S (t-1, 2), S (t-2, 3). Therefore, when x (t+2) is received, the LLR of S (t, 3) can be obtained through direct demodulation; after receiving x (t+1), and decoding c (t-1) to obtain feedback LLR of S (t-1, 3), demodulating to obtain LLR of S (t, 2); after x (t) is received and c (t-1) and c (t-2) are decoded to obtain feedback LLRs of S (t-1, 2) and S (t-2, 3), the LLRs of S (t, 1) can be obtained through demodulation. The following is a more detailed calculation step:
time t: the inverse delay block now has { Γ (S π (t-2, i))|i=1, 2}; the feedback delay module has Γ a(Sπ (t-3, 3)). Y (t) is received. Γ is calculated using y (t) (S π (t-2, 3)). The inverse delay block set { Γ (S π (t-2, i))|i=1, 2,3}. Decoding to obtain { Γ a (S (t-2, i))|i=2, 3}. Note that: Γ a (S (t-2, 1)) does not participate in the decoding of other sub-symbols and therefore the decoder does not calculate it. Calculating Γ (S π (t-1, 2)) using y (t) and Γ a (S (t-2, 3)); Γ is calculated using y (t-1) and Γ a (S (t-2, 2)) (S π (t-1, 1)).
Time t+1: y (t+1) is received. Γ is calculated using y (t+1) (S π (t-1, 3)). The inverse delay block has { Γ (S π (t-1, i)) |t=1, 2,3}. Decoding to obtain{ Γ a (S (t-1, i))|i=2, 3}. Calculating Γ (S π (t, 1)) using y (t), Γ a(Sπ(t-1,2))、Γa(Sπ (t-2, 3); Γ is calculated using y (t+1) and Γ a(Sπ (t-1, 3)) (S π (t, 2)).
Time t+2: y (t+2) is received. Γ is calculated using y (t+2) (S π (t, 3)). The inverse delay block has { Γ (S π (t, i)) |t=1, 2,3}. Decoding to obtain{ Γ a (S (t, i))|i=2, 3}. Calculating Γ (S π (t+1, 1)) using y (t+1), Γ a(Sπ(t,2))、Γa(Sπ (t-1, 3)); Γ is calculated using y (t+2) and Γ a(Sπ (t, 3)) (S π (t+1, 2)).
As an example: the PPM symbol is divided into sub-symbols of equal bit length, such as: d= (2|2), d= (3|3), d= (2|2|2), etc. In this case, the trellis diagram of (accumulator+sub-symbol of bit length d) coincides with the trellis of 2 d -APPM, so the decoding process of (convolutional code+accumulator+sub-symbol of bit length d) is equivalent to the decoding process of 2 d -SCPPM. Examples: for 16-PPM, d= (2|2). The codeword c (t) is N bits long, equivalent to N/4 symbols, N/2 sub-symbols. The decoder combines the sub-symbols Γ (S (t, 1))= [ Γ (S 1,1),Γ(S1,2),...,Γ(S1,N/2) ] and Γ (S (t, 2))= [ Γ (S 2,1),Γ(S2,2),...,Γ(S2,N/2) ] to Γ (S (t))= [ Γ (S 1,1),Γ(S2,1),Γ(S1,2),Γ(S2,2),...,Γ(S1,N/2),Γ(S2,N/2) ]. Wherein S 1,i=bi2de([c1+4(i-1),c2+4(i-1)]),S2,i=bi2de([c3+4(i-1),c4+4(i-1)). Then taking Γ (S (t)) as input to perform iterative decoding of (4-APPM + convolutional codes) (the grid diagram is shown in fig. 14 and 15).
Consider the more complex case: the PPM symbol is divided into sub-symbols of unequal bit lengths. In this case, the decoder needs to use a different APPM trellis. Examples: for 32-PPM, d= (2|3). The codeword c (t) has a length of N bits, which is equivalent to N/5 symbols, 2N/5 sub-symbols. The decoder merges the sub-symbols Γ (S (t, 1))= [ Γ (S 1,1),Γ(S1,2),...,Γ(S1,2N/5) ] and Γ (S (t, 2))= [ Γ (S 2,1),Γ(S2,2),...,Γ(S2,2N/5) ] into Γ (S (t))= [ Γ (S 1,1),Γ(S2,1),Γ(S1,2),Γ(S2,2),...,Γ(S1,2N/5),Γ(S2,2N/5) ], where S 1,i=bi2de([c1+5(i-1),c2+5(i-1)]),S2,i=bi2de([c3+5(i-1),c4+5(i-1),c5+5(i-1)). Then taking Γ (S (t)) as input to perform iterative decoding of (4/8-APPM + convolutional codes). The 4/8-APPM refers to APPM decoder using a hybrid trellis diagram, and using a 4-APPM trellis diagram for the odd sub-symbol S 1,i and an 8-APPM trellis diagram for the even sub-symbol S 2,i (see fig. 16 and 17).
Compared with the prior art, the delay serial cascade pulse position modulation system provided by the invention has the advantages that each codeword in the codeword sequence is segmented into a plurality of sub-symbol sequences by utilizing the transmitting terminal symbol sequence segmentation module, and the bit sequences in the sub-symbol sequences are further interleaved to obtain interleaved sub-symbol sequences. Based on this, the partially interleaved sub-symbol sequence is delayed and participates in modulation together with the sub-symbol sequence corresponding to the subsequent codeword. At this point, each PPM symbol sequence will contain multiple sub-symbol sequences from different codewords.
And at the receiving end, the received signal received at each moment can utilize the sub-symbol feedback sequence successfully decoded at the previous moment to assist demodulation, and the sub-symbol log-likelihood ratio is obtained. After the log-likelihood ratios of all sub-symbol sequences corresponding to all codewords are completely received, the receiving end decodes the code block and feeds back the soft decision or hard decision decoding result to the PPM sub-symbol demodulation module to assist in demodulation of the received signal. In view of this, the delay serial cascade pulse position modulation system provided by the invention has better error performance.
DSCPPM has a coding error performance significantly better than SCPPM + single demodulation coding scheme, and can approach SCPPM + APPM coding scheme in the best case. The reliability performance simulation results are shown in fig. 18 and 19. Referring to fig. 18, SCPPM, APPM decoding is ideal when m=16, nb=0.1. nb is background noise, nb=0.1 indicating that 0.1 photons are received per slot; m=16 indicates a modulation scheme of 16PPM; 4 bits in each symbol, the 4 bits being divided into 2 groups of 2-bit data streams via d (2, 2); delta [0,1] represents delay, 0 indicating no delay; a1 indicates a delay of 1.
Referring to fig. 19, when m=64, nb=0.1, where nb is background noise, nb=0.1 indicates that o.1 photons are received per slot; m=64 indicates that the modulation scheme is 64PPM; 6 bits in each symbol, the 6 bits being divided into 2 groups of 3-bit data streams via d (3, 3); delta [0,1] represents delay, 0 indicating no delay; 1 indicates a delay of 1, the 6 bits being divided into 3 groups of 2-bit data streams via d (2, 2); delta [0,1] represents a delay, 0 indicating no delay; a1 indicates a delay of 1.
Furthermore, the key point of the present invention is to use a joint method of splitting a codeword into a sequence of sub-symbols, interleaving, performing delay modulation, and performing APPM decoding on the sub-symbols, where the joint method equivalently splits a higher-order APPM into lower-order APPM by delay. Under the condition that the original coding module of the existing serial cascade pulse position modulation System (SCPPM) is not changed and APPM is used for decoding, the decoding complexity of the internal code is remarkably reduced compared with that of the existing SCPPM.
It should be further explained that the key idea of the scheme of DSCPPM is to divide the symbol sequence of one codeword into sub-symbol sequences, and disperse the sub-symbol sequences in different time periods to perform PPM modulation, so that the PPM signal sent in each time period includes sub-symbol sequences of multiple codewords at the same time. With this structure, the receiving end uses the decoding result of one codeword to assist the sub-symbol demodulation of the subsequent codeword.
The embodiment of the invention aims to provide a code modulation structure and a corresponding transmitting and receiving flow thereof. Some of these designs may be modified, such as: interleaving coefficients of an interleaving module, a segmentation scheme of sub-symbols and a delay scheme. Some of the computational details may replace different algorithms: such as decoding algorithms and their hardware implementations, used specifically within the decoder (from input of sub-symbol LLRs to giving and decoding results), calculation of feedback information, and specific calculation of sub-symbol demodulation.
In order to further reduce the computational complexity at the receiving end, the PPM signal may also be directly demodulated (directly calculating the bit LLR), and the decoder directly decodes using the bit LLR. DSCPPM + single bit demodulation decoding has a loss in decoding error performance compared with the sub-symbol decoding, but is still better than SCPPM + single bit demodulation decoding. For the case that the plurality of bit sequences have the same delay, SCPPM + multiple bit demodulation decoding may be used, that is, after decoding using the PPM bit demodulation LLR of c (t), the PPM bit demodulation is performed again using the feedback LLR of c (t), the PPM bit demodulation LLR of c (t) is updated, and c (t) is decoded again, and the process of c (t) PPM bit demodulation+c (t) decoding is repeated multiple times.
The error may be substantially ordered as follows: SCPPM + APPM > DSCPPM + sub-symbol APPM > DBICM + SCPPM + single bit demodulation decoding. For DSCPPM, the fewer splits, the better the error performance; when the number of sub-symbols is the same, the more the time of delay, the better the performance. Examples: for 64ppm, d= (3|3) is better than d= (2|2|2). For d= (2|2|2), δ= [0,1,2] is better than δ= [0, 1].
For an ideal poisson channel, the delay order of the sub-sequences does not affect the error performance. (example: for 16-PPM, d= (2|2), δ= [0,1] or δ= [1,0] error performance is consistent). However, the actual system may not be an ideal poisson channel, and the delay order of the sub-sequences may affect the error performance, so the delay order is not specifically defined in the embodiments of the present invention.
In a second aspect, the present invention further provides a delayed serial cascade pulse position modulation method, where the delayed serial cascade pulse position modulation system provided in the first aspect performs the delayed serial cascade pulse position modulation method, and the method includes the following steps:
S10, the transmitting end outputs a PPM symbol sequence based on the original data sequence;
s20, the receiving end outputs a decoding result and a sub-symbol feedback sequence based on the PPM symbol sequence, wherein the sub-symbol feedback sequence is fed back to the transmitting end and participates in the demodulation decoding process together with the received signal in the next demodulation decoding period.
As one possible implementation manner, the outputting, by the transmitting end, the PPM symbol sequence based on the original data sequence includes:
S100, an encoding module receives an original data sequence, and outputs a codeword sequence after encoding;
S101, a sending terminal symbol sequence segmentation module outputs a sub-symbol sequence based on a codeword sequence;
s102, receiving a sub-symbol sequence corresponding to each codeword by a sub-symbol interleaving module, interleaving bit sequences in the sub-symbol sequences, and outputting interleaved sub-symbol sequences;
S103, delay parameters are configured in the delay module, the interleaving sub-symbol sequence is input into the delay module at preset time, and the delay interleaving sub-symbol sequence is output after the delay parameters are reached;
s104, a sub-symbol sequence merging module receives delay interleaving sub-symbol sequences at preset moments and merges all the delay interleaving sub-symbol sequences into delay codeword sequences;
s105, a PPM modulation module receives the delayed codeword sequence, performs M-PPM modulation and outputs a PPM symbol sequence.
As a possible implementation manner, the receiving end outputs the decoding result and the sub-symbol feedback sequence based on the PPM symbol sequence includes:
S200, configuring prior information in a PPM sub-symbol demodulation module, wherein the PPM sub-symbol demodulation module receives a received signal corresponding to a PPM symbol sequence, and determining a sub-symbol log-likelihood ratio by using the prior information and the received signal;
S201, a receiving terminal symbol sequence segmentation module receives the sub-symbol log-likelihood ratio, and segments and then merges the sub-symbol log-likelihood ratio into a sub-symbol log-likelihood ratio sequence; the reverse delay module caches the sub-symbol log-likelihood ratios, and outputs the sub-symbol log-likelihood ratios to the sub-symbol de-interleaving module after collecting all the sub-symbol log-likelihood ratios;
S202, respectively de-interleaving the sub-symbol log-likelihood ratio sequences by a sub-symbol de-interleaving module, and outputting de-interleaved sub-symbol log-likelihood ratios;
s203, the decoding module outputs a decoding result and a sub-symbol feedback sequence based on the de-interleaving sub-symbol log-likelihood ratio;
S204, the sub-symbol feedback sequence is sent to a PPM sub-symbol demodulation module through a feedback module, and the sub-symbol feedback sequence and a received signal participate in a demodulation and decoding process together in the next demodulation and decoding period.
Compared with the prior art, the beneficial effects of the delay serial cascade pulse position modulation method provided by the invention are the same as those of the delay serial cascade pulse position modulation system provided by the first aspect and/or any implementation manner of the first aspect, and the description is omitted here.
In a third aspect, the present invention further provides a deep space optical communication system, where a coding and decoding system adopted by the deep space optical communication system is the delay serial cascade pulse position modulation system provided in the first aspect.
Compared with the prior art, the deep space optical communication system provided by the invention has the same beneficial effects as the delay serial cascade pulse position modulation system provided by the first aspect and/or any implementation manner of the first aspect, and the description is omitted here.
In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.