CN117580360A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which relate to the technical field of semiconductor devices and are used to increase the capacitance of a capacitor and improve the data storage performance of the capacitor while ensuring a higher yield rate of the semiconductor device. The semiconductor device includes: a substrate, a metal interconnection layer, a connection structure and a capacitor. The substrate has an active area. A metal interconnect layer is formed on the substrate. The connection structure runs through the metal interconnect layer. Capacitors are formed on the metal interconnect layer. The lower electrode included in the capacitor is electrically connected to the active area through the connection structure. The manufacturing method of a semiconductor device is used to manufacture the semiconductor device.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to the technical field of semiconductor devices, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

A capacitor is a component that stores electricity and electrical energy. Different amounts of charge can be stored in the capacitor by applying different voltages across the capacitor. On this basis, different data can be stored through capacitors. It can be seen that the quality of capacitors directly affects the data storage performance of semiconductor devices.

However, existing semiconductor devices include metal interconnect layers that limit the increase in capacitance of capacitors, resulting in poor data storage performance of capacitors.

Contents of the invention

The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which are used to increase the capacitance of the capacitor and improve the data storage performance of the capacitor while ensuring a high yield rate of the semiconductor device.

In order to achieve the above object, the present invention provides a semiconductor device, which includes:

a substrate having an active region;

a metal interconnect layer formed on the substrate;

Connection structures through metal interconnect layers;

A capacitor is formed on the metal interconnection layer; the lower electrode included in the capacitor is electrically connected to the active area through the connection structure.

Compared with the prior art, in the semiconductor device provided by the present invention, the metal interconnection layer is formed on the substrate. Furthermore, the capacitor is formed on the metal interconnection layer, and the lower electrode included in the capacitor can be electrically connected to the active area of the substrate through a connection structure penetrating the metal interconnection layer. Based on this, the corresponding structure formed on the surface of the substrate and to be extracted can be electrically connected to the external device through the metal interconnection layer. In practical applications, under the control of external devices, different amounts of charges can be stored in the capacitor electrically connected to the active area to achieve the storage of different data. At the same time, because the metal interconnection layer is provided below the capacitor, even if the capacitance of the capacitor is increased by increasing the height of the lower electrode included in the capacitor, or by changing the structural design of the capacitor, the metal interconnection layer will not be affected. The vertical distance between the connecting layer and the substrate can solve the problem in the existing technology that the metal interconnection layer is formed on the capacitor, and the height of the lower electrode is increased or the structural design of the capacitor is changed, resulting in the difficulty of manufacturing the metal interconnection layer. This is a major technical problem to prevent the metal interconnection layer from limiting the increase in capacitance of the capacitor and improve the data storage performance of the capacitor.

In addition, during the manufacturing process of the semiconductor device provided by the present invention, since the metal interconnection layer is formed below the capacitor, that is, when the metal interconnection layer is manufactured, the capacitor has not yet been formed. Based on this, even if the process temperature required to form the metal interconnection layer is relatively high, the metal ions in the upper electrode included in the metal interconnection layer and the capacitor will not diffuse downward into the lower electrode, causing the lower electrode to deform. It can reduce the leakage loss of the capacitor, improve the operating speed of the capacitor, and further improve the data storage performance of the capacitor.

The invention also provides a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device includes:

providing a substrate having an active area;

forming a metal interconnect layer on the substrate;

Form a connection structure that penetrates the metal interconnection layer;

A capacitor is formed on the metal interconnection layer; a lower electrode included in the capacitor is electrically connected to the active area through the connection structure.

Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the present invention and the beneficial effects of the semiconductor device provided by the above technical solution will not be described again here.

Description of the drawings

The drawings described here are used to provide a further understanding of the present invention and constitute a part of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached picture:

Figure 1 is a schematic cross-sectional view of the structure of a semiconductor device in the prior art;

Figure 2 is a block diagram showing the positional relationship of various structures formed on the memory unit area in the prior art;

Figure 3 is a schematic cross-sectional view of the structure after forming the first insulating layer and the first contact hole in the embodiment of the present invention;

4 is a schematic cross-sectional view of the structure after forming a contact structure included in the metal interconnection layer in an embodiment of the present invention;

Figure 5 is a schematic cross-sectional view of a structure after forming metal interconnect lines in an embodiment of the present invention;

Figure 6 is a schematic cross-sectional view of the structure after forming the second insulating material and the trench in the embodiment of the present invention;

Figure 7 is a schematic cross-sectional view of another structure after metal interconnect lines are formed in the embodiment of the present invention;

Figure 8 is a schematic cross-sectional view of the structure after forming a metal interconnection layer in an embodiment of the present invention;

Figure 9 is a schematic cross-sectional view of the structure after the connection structure is formed in the embodiment of the present invention;

Figure 10 is a schematic structural diagram after forming a capacitor in an embodiment of the present invention;

FIG. 11 is a block diagram showing the positional relationship of various structures formed on the memory cell area in the embodiment of the present invention.

Reference signs:

1 is the base, 11 is the active area, 12 is the memory unit area,

13 is the peripheral circuit area, 14 is the semiconductor substrate, 15 is the isolation layer,

16 is the bit line structure, 17 is the storage contact, 18 is the landing plug,

19 is the insulation part;

2 is the metal interconnection layer, 21 is the first insulating layer, 22 is the contact structure,

23 is a metal interconnection line, 24 is a second insulating layer, 25 is a first contact hole,

26 is the groove,

3 is the connection structure,

4 is a capacitor, 41 is a lower electrode, 42 is a dielectric layer,

43 is the upper electrode.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The drawings are not drawn to scale, with certain details exaggerated and may have been omitted for purposes of clarity. The shapes of the various regions and layers shown in the figures, as well as the relative sizes and positional relationships between them are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art will base their judgment on actual situations. Additional regions/layers with different shapes, sizes, and relative positions can be designed as needed.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on" another layer/element in one orientation, then the layer/element can be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited. "Several" means one or more than one, unless otherwise expressly and specifically limited.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

As shown in FIGS. 1 and 2 , during the manufacturing process of a semiconductor device, the transistors in the semiconductor device, the landing plugs 18 electrically connected to the active regions 11 of the corresponding transistors, and the landing plugs 18 used to isolate two adjacent lands After the insulating portion 19 of the plug 18 is manufactured, a molding layer covering the landing plug 18 and the insulating portion 19 needs to be formed, and electrode holes are opened in the molding layer. Next, a lower electrode 41 is formed in each electrode hole. The bottom of each lower electrode 41 is in contact with the corresponding landing plug 18 . After that, the dielectric layer 42 covering the surface of the lower electrode 41 is formed, and the upper electrode 43 is formed on the dielectric layer 42. Then, the manufacturing of the capacitor 4 located on the memory cell region 12 is completed. Finally, the metal interconnection layer 2 covering the capacitor 4 and the peripheral circuit area 13 is formed. The metal interconnection layer 2 is used to lead out corresponding structures (eg word lines, peripheral circuit components) formed on the memory cell area 12 and the peripheral circuit area 13 to facilitate electrical connection between the above structures and external devices.

Based on the above content, because the capacitance of the capacitor is proportional to the facing area between the upper and lower electrodes, and in order to meet the gradually increasing demand for capacitance of capacitors in semiconductor devices, the height of the lower electrode included in the capacitor gradually increase. Correspondingly, the vertical distance between the metal interconnection layer and the structure that needs to be lead out becomes larger, so it is necessary to etch a contact hole deeper than the height of the lower electrode to achieve electrical connection between the metal interconnection layer and the corresponding structure that needs to be lead out. However, when the depth-to-width ratio of the contact hole is large, when the insulating layer is etched downward from the top of the insulating layer to form the contact hole, it is difficult for the etchant to etch through the insulating layer. Or, the etchant takes a long time to etch the top of the insulating layer and a short time to etch the bottom of the insulating layer. Therefore, in order to obtain a contact hole that penetrates the insulating layer, the etchant will etch near the opening of the contact hole. The etching amount is greater than the etching amount near the bottom of the contact hole, which easily causes other structures (such as capacitors) located near the contact hole opening to be affected by the etchant, reducing the yield of the semiconductor device. It can be seen that in existing semiconductor devices, the metal interconnection layer formed on the capacitor limits the increase in capacitance of the capacitor. Furthermore, with the shrinkage of semiconductor devices, the size of each part within the semiconductor device is gradually reduced, and forming a metal interconnection layer on the capacitor is not conducive to changing the design of the capacitor.

In addition, when manufacturing the metal interconnection lines included in the metal interconnection layer, because the formation temperature of the metal interconnection lines is relatively high, and the metal interconnection layer is formed on the capacitor, in a higher temperature environment, the metal interconnection lines And metal ions in the upper electrode easily diffuse into the lower electrode, causing the lower electrode to deform. When the morphology of the lower electrode does not meet the requirements of the preset plan, it is easy to cause leakage between the upper and lower electrodes, affecting the data storage performance of the capacitor.

In order to solve the above technical problems, embodiments of the present invention provide a semiconductor device and a manufacturing method thereof. Among them, in the semiconductor device provided by the embodiment of the present invention, the metal interconnection layer is arranged below the capacitor to prevent the metal interconnection layer from limiting the increase in capacitance of the capacitor and improve the data storage performance of the capacitor. Also, when the metal interconnect layer is fabricated, the capacitor has not yet been formed. Based on this, even if the process temperature required to form the metal interconnection layer is relatively high, the metal ions in the upper electrode included in the metal interconnection layer and the capacitor will not diffuse downward into the lower electrode, causing the lower electrode to deform. It can reduce the leakage loss of the capacitor, improve the operating speed of the capacitor, and further improve the data storage performance of the capacitor.

As shown in Figure 10, an embodiment of the present invention provides a semiconductor device. The semiconductor device may be an electronic device such as DRAM (Dynamic Random Access Memory), FLASH (Flash Memory), etc.

As shown in FIGS. 10 and 11 , the semiconductor device includes: a substrate 1 , a metal interconnect layer 2 , a connection structure 3 and a capacitor 4 . Wherein, the above-mentioned substrate 1 has an active region 11 . Metal interconnection layer 2 is formed on substrate 1 . The connection structure 3 penetrates the metal interconnection layer 2 . Capacitor 4 is formed on metal interconnection layer 2 . The lower electrode 41 included in the capacitor 4 is electrically connected to the active area 11 through the connection structure 3 .

Specifically, from a functional perspective, as shown in FIG. 10 , the above-mentioned substrate 1 may include a memory cell region 12 and a peripheral circuit region 13 . Among them, the peripheral circuit area 13 is mainly an area where the peripheral support circuit of the semiconductor device is located, and is formed around the memory cell area 12 . The memory cell area 12 is mainly an area in the semiconductor device where the memory cells are located. For example: for DRAM, the memory unit includes a transistor (not shown in the figure) and a capacitor 4. At this time, the transistor and capacitor 4 included in the memory cell are located on the memory cell region 12 . Specifically, the positional relationship between the memory unit area 12 and the peripheral circuit area 13 and the specific structures of the two can be designed according to the actual application scenario, and are not specifically limited here.

In addition, as shown in FIG. 10 , both the memory cell region 12 and the peripheral circuit region 13 included in the substrate 1 may have an active region 11 and an isolation layer 15 for defining the active region 11 . Among them, the active region 11 is doped with N-type or P-type impurities. The isolation layer 15 may be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

From a structural perspective, the above-mentioned substrate may be a stack in which part of the semiconductor structure has been formed. It is conceivable that depending on the type of semiconductor device, the semiconductor structure included in the substrate is also different. For example: as shown in Figure 10, when the semiconductor device is a DRAM, the above-mentioned substrate 1 may at least include a semiconductor substrate 14, a transistor, a bit line structure 16, a storage contact 17, an isolation part (not shown in the figure), a landing plug Plug 18, insulator 19 and active circuit components (e.g. gate structure). The above-described transistor is formed on the portion of the semiconductor substrate 14 located in the memory cell region 12 . Bit line structure 16 is formed over the transistors. Storage contacts 17 and isolations are formed between adjacent bit line structures 16 . The storage contact 17 is in contact with the source region (or drain region) on the active region 11 . The isolation part is used to isolate two adjacent storage contact parts 17 . At the same time, each landing plug 18 is formed on its corresponding storage contact 17 . The landing plug 18 is electrically connected to the source area (or drain area) on the active area 11 through the storage contact 17 . Insulating portions 19 are formed on the bit line structures 16 and isolation portions. The insulation part 19 is used to isolate two adjacent landing plugs 18 .

The above-mentioned transistor may be a buried trench transistor, or any other transistor that meets the requirements. The gate electrodes of corresponding transistors may be electrically connected together to form a word line. The above bit line structure may include a bit line body, a cover layer located on the bit line body, and sidewalls located on both sides of the bit line body and the cover layer. The above-mentioned bit line body can be electrically connected to the drain region (or source region) on the active region through the bit line contact portion. The materials contained in each of the above parts can be set according to the actual application scenario, and there are no specific limitations here.

The above-mentioned active circuit components are formed on the portion of the semiconductor substrate located in the peripheral circuit region. Specifically, the active circuit components are formed on the active area located in the peripheral circuit area. The active circuit components constitute peripheral support circuitry. For example, the active circuit component may be a readout unit, a decoder, or an amplification circuit that controls memory cells formed in the memory cell region. The specific structure of the above-mentioned active circuit components can be designed according to actual needs and is not specifically limited here.

Regarding the above metal interconnection layer, as shown in FIG. 10 , when the substrate 1 includes the memory cell region 12 and the peripheral circuit region 13 , the metal interconnection layer 2 may cover the memory cell region 12 and the peripheral circuit region 13 . The metal interconnection layer 2 can lead out corresponding structures such as word lines in the memory cell area 12 and active circuit components in the peripheral circuit area 13 to achieve vertical signal conduction. The number of metal interconnection layers 2 may be one layer or multiple layers. Specifically, the structure, specific number of layers, and material of the metal interconnection layer 2 can be designed according to the actual application scenario, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention.

Regarding the above connection structure, as shown in FIG. 10 , the connection structure 3 penetrates the metal interconnection layer 2 and is insulated from the metal interconnection layer 2 . The position of the connection structure 3 in the metal interconnection layer 2 can be set according to the position of the capacitor 4 on the metal interconnection layer 2 and the position of the active area 11, so as to facilitate the electrical connection between the lower electrode 41 and the active area 11. connect. For example: in the case where the substrate 1 includes the memory cell region 12 and the peripheral circuit region 13, and the metal interconnection layer 2 covers the memory cell region 12 and the peripheral circuit region 13, the connection structure 3 may be formed where the metal interconnection layer 2 is located on the memory cell. within the section on area 12. Among them, the material of the connection structure 3 can be copper, tungsten, aluminum and other conductive materials.

For the above-mentioned capacitors, the number of capacitors formed on the metal interconnection layer can be set according to the actual application scenario, and is not specifically limited here. When the number of capacitors is multiple, the arrangement of the multiple capacitors can be designed according to actual needs, as long as it can be applied to the semiconductor device provided by the embodiment of the present invention. Specifically, since the capacitor is a memory device that can store data, when the substrate includes a memory unit area and a peripheral circuit area, the capacitor is formed above the memory unit area. In addition, as shown in FIG. 10 , the capacitor 4 may also include a dielectric layer 42 covering the surface of the lower electrode 41 and an upper electrode 43 formed on the dielectric layer 42 . Wherein, when the substrate 1 also has the bit line structure 16, the storage contact portion 17 and the isolation portion, the lower electrode 41 can be electrically connected to the active area 11 through the connection structure 3 and the storage contact portion 17 in sequence. The lower electrode 41 may be a cylindrical electrode or a columnar electrode. Of course, other types of electrodes are also possible. The cross-sectional shape of the lower electrode 41 may be circular, polygonal, annular, or other shapes. The height of the lower electrode 41 can be designed according to actual requirements. Specifically, since the capacitance of the capacitor 4 is proportional to the facing area between the lower electrode 41 and the upper electrode 43, when other factors are the same, the greater the height of the lower electrode 41, the greater the capacitance of the capacitor 4. big. On the contrary, the smaller the height of the lower electrode 41 is, the smaller the capacitance of the capacitor 4 is.

Furthermore, the above-mentioned lower electrode and upper electrode are made of conductive materials, and commonly used conductive materials are doped polysilicon, silicon germanium, metal or metal nitride, etc. The material of the lower electrode and the material of the upper electrode may be the same or different. The specific materials of the two can be designed according to the actual application scenario, and are not specifically limited here.

For the above dielectric layer, the material of the dielectric layer is an insulating material, and commonly used insulating materials are silicon oxide or high K (dielectric constant) materials. The thickness of the dielectric layer can be set according to the actual application scenario. Specifically, the thickness of the dielectric layer determines the distance between the lower electrode and the upper electrode. The distance between the lower electrode and the upper electrode is inversely proportional to the capacitance of the capacitor, that is, as the distance between the lower electrode and the upper electrode becomes smaller, the capacitance of the capacitor becomes larger. When the distance between the lower electrode and the upper electrode becomes larger, the capacitance of the capacitor becomes smaller.

It can be seen from the above that, as shown in FIGS. 10 and 11 , in the semiconductor device provided by the embodiment of the present invention, because the metal interconnection layer 2 is disposed below the capacitor 4 , even if the lower electrode 41 included in the capacitor 4 is enlarged, Increasing the capacitance of the capacitor 4 by changing the structural design of the capacitor 4 will not affect the vertical distance between the metal interconnection layer 2 and the substrate 1, thereby solving the problem of metal interconnection in the existing technology. The formation of the connecting layer 2 on the capacitor 4 and increasing the height of the lower electrode 41 or changing the structural design of the capacitor 4 lead to technical problems that make the manufacturing of the metal interconnection layer 2 more difficult to prevent the metal interconnection layer 2 from limiting the The increase in the capacitance of the capacitor 4 improves the data storage performance of the capacitor 4 .

In addition, as shown in FIGS. 3 to 10 , in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, because the metal interconnection layer 2 is formed below the capacitor 4 , that is, when the metal interconnection layer 2 is manufactured, the metal interconnection layer 2 has not yet been formed. Capacitor 4 is formed. Based on this, even if the process temperature required to form the metal interconnection layer 2 is relatively high, the metal ions in the upper electrode 43 included in the metal interconnection layer 2 and the capacitor 4 will not diffuse downward into the lower electrode 41 . The lower electrode 41 is deformed, thereby reducing the leakage loss of the capacitor 4, improving the operating speed of the capacitor 4, and further improving the data storage performance of the capacitor 4.

In an example, as shown in FIG. 10 , the above-mentioned metal interconnection layer 2 may include a first insulation layer 21 , a contact structure 22 , a metal interconnection line 23 and a second insulation layer 24 . Wherein, the first insulating layer 21 is formed on the substrate 1 . The contact structure 22 penetrates the first insulation layer 21 . The metal interconnection lines 23 are formed on the first insulation layer 21 and are in contact with the corresponding contact structures 22 . The second insulating layer 24 covers the metal interconnection lines 23 and the first insulating layer 21 . The connection structure 3 penetrates the first insulation layer 21 and the second insulation layer 24 .

Specifically, the first insulating layer and the second insulating layer are made of insulating materials such as silicon dioxide or silicon oxynitride. The thicknesses of the first insulating layer and the second insulating layer can be set according to actual requirements and are not specifically limited here.

The materials of the above-mentioned contact structures and metal interconnection lines can be metal materials such as copper, aluminum, and gold. The number of the above contact structures and the number of metal interconnection lines can be set according to actual needs. In addition, in the case where the substrate includes a memory cell region and a peripheral circuit region, the metal interconnection line located above the memory cell region may be electrically connected to the structure from which the word line is to be drawn out through a corresponding contact structure. Metal interconnect lines located over the peripheral circuit area may be electrically connected to the active circuit components through corresponding contact structures.

In an example, as shown in FIG. 10 , the radial cross-sectional area of the lower electrode 41 may be larger than the radial cross-sectional area of the connection structure 3 . It can be understood that compared with the radial cross-sectional area of the lower electrode 41 being less than or equal to the radial cross-sectional area of the connection structure 3 , when the radial cross-sectional area of the lower electrode 41 is greater than the radial cross-sectional area of the connection structure 3 , the lower electrode 41 Has a larger surface area. Based on this, since the capacitance of the capacitor 4 is proportional to the facing area of the lower electrode 41 and the upper electrode 43, when other factors are the same, the lower electrode 41 has a larger surface area, which can increase the capacitance of the capacitor 4. , further improving the data storage performance of capacitor 4.

An embodiment of the present invention also provides a method for manufacturing a semiconductor device. The manufacturing process will be described below based on cross-sectional views of the operations shown in FIGS. 3 to 10 . Specifically, the manufacturing method of the semiconductor device includes:

First, a substrate with an active area is provided. Specifically, the specific structure and material of the substrate can be referred to the above, and will not be described again here.

As shown in FIG. 3 , in one example, in the case where the metal interconnection layer 2 includes a first insulation layer 21 , a contact structure 22 , a metal interconnection line 23 and a second insulation layer 24 , the metal interconnection layer 2 may first be formed on the substrate 1 The first insulating layer 21 is formed. A first patterning process is performed on the first insulating layer 21 to form a first contact hole 25 penetrating the first insulating layer 21 .

For example, when the substrate includes a memory unit area and a peripheral circuit area, a chemical vapor deposition or physical vapor deposition process may be used to form the first insulating material covering the memory unit area and the peripheral circuit area. Then, chemical mechanical polishing or other processes may be used to planarize the first insulating material to obtain the first insulating layer. Afterwards, photolithography and etching processes may be used to perform a first patterning process on the first insulating layer to form the above-mentioned first contact hole. Specifically, the bottom of the first contact hole located on the memory cell area is in contact with the contact portion electrically connected to the word line waiting lead-out structure. The bottom of the first contact hole located on the peripheral circuit area is in contact with the contact portion for electrical connection of the active circuit component.

As shown in FIG. 4 , a contact structure 22 is formed in the first contact hole.

For example, a chemical vapor deposition or physical vapor deposition process may be used to form the contact structure filled in the first contact hole.

As shown in FIGS. 5 to 7 , metal interconnection lines 23 are formed on the first insulating layer 21 . Metal interconnect lines 23 are in contact with corresponding contact structures 22 .

For example, as shown in FIG. 5 , a chemical vapor deposition or physical vapor deposition process may be used to form a metal material layer covering the contact structure 22 and the first insulating layer 21 . Then, photolithography and etching processes can be used to selectively etch the metal material layer to form metal interconnection lines 23 in contact with the corresponding contact structures 22 . Alternatively, as shown in FIG. 6 , a chemical vapor deposition or physical vapor deposition process may also be used to form the second insulating material covering the contact structure 22 and the first insulating layer 21 . Then, photolithography and etching processes are used to selectively etch the second insulating material to preform trenches 26 in areas where metal interconnection lines are subsequently formed. The bottom of each trench 26 is in contact with the corresponding contact structure 22 . Finally, as shown in Figure 7, metal interconnection lines 23 are formed within each trench.

As shown in FIG. 8 , a second insulating layer 24 covering the metal interconnection lines 23 and the first insulating layer 21 is formed. The first insulation layer 21 , the contact structure 22 , the metal interconnection lines 23 and the second insulation layer 24 constitute the metal interconnection layer 2 .

For example, as mentioned above, when the metal interconnection lines are obtained by selectively etching the metal material layer, a process such as chemical vapor deposition or physical vapor deposition can be used to form a layer covering the metal interconnection layer and the first Third insulating material on the insulating layer. Then the third insulating material can be planarized using processes such as chemical mechanical polishing to obtain a second insulating layer with a relatively flat top, so that structures such as capacitors can be subsequently formed on the relatively flat second insulating layer, so that the internal structure of the semiconductor device can be The structure is more regular. Alternatively, when a metal interconnection line is formed in a trench opened in the second insulating material, the third insulating material covering the second insulating material and the metal interconnection line can be formed in the above manner. After the third insulating material is planarized, the remaining second insulating material and the third insulating material constitute the second insulating layer. Since the first insulating layer, the contact structure, the metal interconnection lines and the second insulating layer constitute the metal interconnection layer, after the second insulating layer is formed, the operation of forming the metal interconnection layer on the substrate is completed.

It should be noted that when the manufactured semiconductor device includes a multi-layer metal interconnection layer, the upper layer can be formed on the formed metal interconnection layer along the thickness direction of the substrate using the method given in the above example. metal interconnect layer. In addition, information such as the material and thickness of the above-mentioned first insulating layer, contact structure, metal interconnection line and second insulating layer can be referred to the above.

As shown in FIG. 9 , a connection structure 3 penetrating the metal interconnection layer 2 is formed.

For example, when the substrate includes a memory unit area and a peripheral circuit area, photolithography and etching processes may be used to perform a second patterning process on the portions of the first insulating layer and the second insulating layer located on the memory unit area. , forming a second contact hole penetrating the first insulating layer and the second insulating layer. Specifically, the bottom of the second contact hole may be in contact with the top of the storage contact portion (if a landing plug is formed, it should be the top of the landing plug). Then, a process such as chemical vapor deposition or physical vapor deposition can be used to form a connection structure in the second contact hole. The material of the connection structure can be referred to the previous article.

As shown in FIG. 10 , a capacitor 4 is formed on the metal interconnection layer 2 . The lower electrode 41 included in the capacitor 4 is electrically connected to the active area 11 through the connection structure 3 . It can be understood that when the structure type of the lower electrode 41 is different, the manner of forming the capacitor 4 on the metal interconnection layer 2 is also different. The following takes the electrode 41 as a cylindrical electrode and a columnar electrode as an example to describe the manufacturing process of forming the capacitor 4 respectively:

For example, in the case where the lower electrode is a columnar electrode, at least a molding layer covering the metal interconnection layer may be formed. Wherein, when the substrate includes a memory cell region and a peripheral circuit region, the metal interconnection layer covers the memory cell region and the peripheral circuit region. The above-described molding layer is formed over the memory cell region and the peripheral circuit region. The molding layer may be made of easily removable material such as silicon dioxide. Since the lower electrode will be formed later in the electrode hole opened in the molding layer, the height of the molding layer can be set according to the height of the lower electrode. Then, photolithography and etching processes can be used to perform a third patterning process on the portion of the molding layer located above the memory cell area to form an electrode hole pattern penetrating the molding layer. Specifically, the specifications and number of the electrode holes included in the electrode hole pattern, and the distribution position of each electrode hole in the molding layer can be determined according to the specifications and number of the lower electrodes included in the capacitor, and the position of each lower electrode on the metal interconnect. Set the distribution position on the connection layer. Afterwards, a process such as chemical vapor deposition or physical vapor deposition can be used to form the lower electrode within the electrode hole pattern. Each lower electrode fills the corresponding electrode hole. Finally, processes such as wet etching can be used to remove the molding layer around the lower electrode to release the lower electrode from the molding layer. and forming a dielectric layer covering the surface of the lower electrode, and forming an upper electrode on the dielectric layer. Since the lower electrode, dielectric layer and upper electrode constitute a capacitor, the manufacturing of the capacitor is completed after the upper electrode is formed. Among them, information such as the materials and specifications of the lower electrode, dielectric layer and upper electrode can be referred to the previous article.

For example, when the lower electrode is a cylindrical electrode, at least one layer composed of a molding layer and a support layer can be formed on the metal interconnection layer in the above manner. The number of stacked layers and the thickness of the support layer and the molding layer can be set according to the height of the lower electrode, and are not specifically limited here. In addition, the support layer in the stack is located on the molding layer, and there is a certain etching selectivity ratio between the material of the support layer and the material of the molding layer. For example: when the material of the molding layer is silicon dioxide, the material of the support layer can be silicon nitride or the like. Then it is necessary to perform a third patterning process on the molding layer and the support layer to form a pattern of electrode holes penetrating the support layer and the molding layer. And forming a lower electrode covering the inner wall of each electrode hole included in the electrode hole pattern. Finally, the molded layer is removed to release the lower electrode. And forming a dielectric layer covering the surface of the support layer and the lower electrode, and an upper electrode formed on the dielectric layer, thereby realizing the manufacture of the capacitor.

Compared with the prior art, the beneficial effects of the method for manufacturing a semiconductor device provided by the embodiments of the present invention are the same as those of the semiconductor device provided by the above embodiments, and will not be described again here.

In the above description, there is no detailed explanation of the technical details such as patterning and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. in desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. In addition, although each embodiment is described separately above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the disclosure.

Claims (10)

1. A semiconductor device, characterized in that it includes: a substrate having an active region; a metal interconnect layer formed on the substrate; A connection structure extending through the metal interconnection layer; A capacitor is formed on the metal interconnection layer; a lower electrode included in the capacitor is electrically connected to the active area through the connection structure. 2. The semiconductor device according to claim 1, wherein the substrate includes a memory cell region and a peripheral circuit region; the metal interconnection layer covers the memory cell region and the peripheral circuit region; and the connection A structure is formed in a portion of the metal interconnect layer over the memory cell region; the capacitor is formed over the memory cell region. 3. The semiconductor device according to claim 1, wherein the metal interconnection layer includes a first insulating layer, a contact structure, a metal interconnection line and a second insulating layer; The first insulating layer is formed on the substrate; the contact structure penetrates the first insulating layer; the metal interconnection line is formed on the first insulating layer and contacts the corresponding contact structure; The second insulating layer covers the metal interconnection line and the first insulating layer; The connection structure penetrates the first insulation layer and the second insulation layer. 4. The semiconductor device according to claim 1, wherein the radial cross-sectional area of the lower electrode is greater than the radial cross-sectional area of the connection structure; and/or, The lower electrode is a cylindrical lower electrode or a columnar lower electrode. 5. The semiconductor device according to claim 1, wherein the substrate further has a bit line structure located on the active area, and a storage contact portion and an isolation portion located between adjacent bit line structures; The isolation part is used to isolate two adjacent storage contact parts; the lower electrode is electrically connected to the active area through the connection structure and the storage contact part. 6. The semiconductor device according to any one of claims 1 to 4, wherein the capacitor further includes a dielectric layer covering the surface of the lower electrode, and an upper electrode formed on the dielectric layer. 7. A method for manufacturing a semiconductor device, characterized by comprising: providing a substrate having an active area; forming a metal interconnect layer on the substrate; Forming a connection structure through the metal interconnection layer; A capacitor is formed on the metal interconnection layer; a lower electrode included in the capacitor is electrically connected to the active area through the connection structure. 8. The method of manufacturing a semiconductor device according to claim 7, wherein forming a metal interconnection layer on the substrate includes: forming a first insulating layer on the substrate; Perform a first patterning process on the first insulating layer to form a first contact hole penetrating the first insulating layer; and form a contact structure in the first contact hole; Forming metal interconnection lines on the first insulating layer; the metal interconnection lines are in contact with the corresponding contact structures; A second insulating layer covering the metal interconnection lines and the first insulating layer is formed; the first insulating layer, the contact structure, the metal interconnection lines and the second insulating layer constitute the metal interconnection layer. 9. The method of manufacturing a semiconductor device according to claim 8, wherein forming a connection structure penetrating the metal interconnection layer includes: Perform a second patterning process on the first insulating layer and the second insulating layer to form a second contact hole penetrating the first insulating layer and the second insulating layer; The connection structure is formed in the second contact hole. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the substrate includes a memory cell region and a peripheral circuit region; the metal interconnect layer covers the memory cell region and the peripheral circuit region; The forming a capacitor on the metal interconnection layer includes: forming at least a molding layer overlying the metal interconnect layer; Perform a third patterning process on the portion of the molding layer located above the memory unit area to form an electrode hole pattern penetrating the molding layer; forming a lower electrode within the electrode hole pattern; A dielectric layer covering the surface of the lower electrode is formed, and an upper electrode is formed on the dielectric layer; the lower electrode, the dielectric layer and the upper electrode constitute the capacitor.