CN218920890U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Abstract

The utility model discloses a semiconductor device, which comprises a substrate, a storage node bonding pad, a capacitor structure and a supporting structure. The storage node pads are disposed on the substrate. The capacitor structure is arranged on the storage node bonding pad and comprises a plurality of capacitors, wherein the capacitors comprise a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, and the top of the bottom electrode layer is provided with a groove. The supporting structure comprises a plurality of first supporting layers and a plurality of second supporting layers from bottom to top, and is connected with two adjacent capacitors, wherein the grooves face each second supporting layer respectively.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The present utility model relates to a semiconductor device, and more particularly, to a semiconductor memory device.

Background

With the trend toward miniaturization of various electronic products, the design of semiconductor memory devices must meet the requirements of high integration and high density. For the DRAM (dynamic random access memory, DRAM) with recessed gate structure, the current trend is that it has gradually replaced the DRAM with planar gate structure because it can obtain longer carrier channel length in the same semiconductor substrate to reduce the leakage of capacitor structure.

In general, a dram with a recessed gate structure is formed by aggregating a large number of memory cells (memory cells) to form an array region for storing information, and each memory cell may be formed by a transistor element in series with a capacitor element for receiving voltage information from Word Lines (WL) and Bit Lines (BL). In response to product requirements, the density of memory cells in the array region must be increased continuously, which results in increased difficulty and complexity in the related manufacturing process and design. Accordingly, the prior art or structure is further improved to effectively improve the performance and reliability of the related memory device.

Therefore, a semiconductor device is invented to solve the above-mentioned problems.

Disclosure of Invention

In order to achieve the above object, one embodiment of the present utility model provides a semiconductor device, in which a recess is additionally provided on at least a portion of the bottom electrode layer toward the second supporting layer, so as to additionally pull the distance between the bottom electrode layers, which is beneficial to forming a capacitor dielectric layer and a top electrode layer with more optimized structure. Therefore, the semiconductor device can improve the structural reliability of the storage node, and further optimize the functions and the performances of the storage node.

In order to achieve the above object, one embodiment of the present utility model provides a method for manufacturing a semiconductor device, which locally reduces the thickness of the top portion of the bottom electrode layer by lateral etching in the etching process, so as to additionally form a recess on the bottom electrode layer, wherein the recess faces the second supporting layer, so that the manufacturing process of the subsequent capacitor dielectric layer and the top electrode layer can be optimized. Therefore, the manufacturing method of the semiconductor device can form the storage node with both structural reliability and device efficiency even on the premise of continuously improving the density of the storage unit.

A semiconductor device provided according to one embodiment of the present utility model includes a substrate, a storage node pad, a capacitance structure, and a support structure. The storage node pad is disposed on the substrate. The capacitor structure is arranged on the storage node bonding pad and comprises a plurality of capacitors, each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, and the top of the bottom electrode layer is provided with a groove. The supporting structure comprises a plurality of first supporting layers and a plurality of second supporting layers from bottom to top, and is connected with two adjacent capacitors, wherein the grooves face to the second supporting layers respectively.

The manufacturing method of the semiconductor device provided by one embodiment of the utility model comprises the following steps. First, a substrate is provided, on which a plurality of storage node pads are formed. And forming a capacitor structure on the storage node bonding pad, wherein the capacitor structure comprises a plurality of capacitors, each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, and the top of the bottom electrode layer is provided with a groove. And then forming a supporting structure to connect two adjacent capacitors, wherein the supporting structure comprises a first supporting layer and second supporting layers from bottom to top, and the grooves face each second supporting layer respectively.

Drawings

The accompanying drawings provide a further understanding of the embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 7 are schematic views illustrating steps of a method for fabricating a semiconductor device according to a first embodiment of the present utility model, wherein:

fig. 1 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a support layer structure;

fig. 2 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming an electrode material layer;

FIG. 3 is a schematic cross-sectional view of the semiconductor device of the present utility model after a first etching process is performed;

fig. 4 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a bottom electrode layer;

FIG. 5 is a schematic cross-sectional view of the semiconductor device of the present utility model after etching the support layer structure;

fig. 6 is a schematic cross-sectional view of the semiconductor device of the present utility model after the third support material layer and the first support material layer are completely removed; and

fig. 7 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a capacitor.

Fig. 8 to 9 are schematic views illustrating steps of a method for fabricating a semiconductor device according to a second embodiment of the present utility model, wherein:

fig. 8 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a bottom electrode layer; and

fig. 9 is a schematic cross-sectional view of a semiconductor device of the present utility model after forming a capacitor.

Fig. 10 to 11 are schematic views illustrating steps of a method for fabricating a semiconductor device according to a third embodiment of the present utility model, wherein:

fig. 10 is a schematic cross-sectional view of the semiconductor device of the present utility model after the third support material layer and the first support material layer are completely removed; and

fig. 11 is a schematic cross-sectional view of the semiconductor device of the present utility model after forming a capacitor.

Fig. 12 is a schematic diagram showing steps of a method for fabricating a semiconductor device according to a fourth embodiment of the present utility model.

Wherein reference numerals are as follows:

100. 300, 400, 500 semiconductor device

101. Insulating region

110. Substrate and method for manufacturing the same

130. Insulating layer

131. Oxide layer

133. Nitride layer

135. Oxide layer

140. Spacer structure

141. First spacer

143. Second spacer

145. Third spacer

150. Contact point

160. Bit line

160a bit line contact

161. Semiconductor layer

163. Barrier layer

165. Conductive layer

167. Cover layer

170. Dielectric layer

180. Storage node bonding pad

190. Supporting layer structure

191. A first support material layer

192. Through hole

193. A second supporting material layer

195. A third supporting material layer

197. Fourth support material layer

200. Electrode material layer

210. Initial bottom electrode layer

211. 411 first part

213. 313, 513 second part

215. 315, 515 inclined plane

217. 317 groove

220. Mask pattern

230. 232, 332, 430, 432 bottom electrode layers

234. Capacitor dielectric layer

236. Top electrode layer

240. 440 support structure

241. A first supporting layer

243. 443 second supporting layer

250. 350, 450 capacitor structure

T1 first thickness

T2 second thickness

P1 first etching process

P2 and P5 second etching process

P21 and P51 vertical downward etching process

P22 and P52 lateral etching process

P3 third etching process

P4 and P6 fourth etching process

Detailed Description

The following description sets forth the preferred embodiments of the present utility model and, together with the accompanying drawings, provides a further understanding of the utility model, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the utility model pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the utility model to accomplish other embodiments.

Referring to fig. 1 to 7, a schematic diagram of steps of a method for manufacturing a semiconductor device 100 according to a first embodiment of the utility model is shown. First, as shown in fig. 1, a substrate 110, such as a silicon substrate, a silicon-containing substrate (e.g., siC, siGe, etc.), or a silicon-on-insulator (SOI) substrate, is provided, at least one insulating region 101, such as a shallow trench isolation (shallow trench isolation, STI), is formed in the substrate 110, and a plurality of active areas (AA, not shown) are defined on the substrate 110. In one embodiment, the insulating region 101 is formed by, for example, forming a plurality of trenches (not shown) in the substrate 110 by an etching process, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride).

In addition, a plurality of buried gates (not shown) are further formed in the substrate 110, and the buried gates extend in parallel to each other along a direction (such as an x-direction, not shown) and are staggered with the active region, so as to be used as buried word lines (BWL, not shown) of the semiconductor device 100. A plurality of bit lines 160 and a plurality of contacts 150 may be formed over the substrate 110, wherein each bit line 160 extends parallel to each other along another direction (e.g., y-direction, not shown) perpendicular to the direction, so as to be alternately arranged with each contact 150 in the direction. Although the overall extension of the active region, the buried gate and the bit line 160 is not specifically shown in the drawings of the present embodiment, it should be readily understood by those skilled in the art that the bit line 160 should be perpendicular to the buried gate and cross the active region and the buried gate at the same time when viewed from a top view.

In detail, each bit line 160 is formed on the substrate 110 separately from each other and includes a semiconductor layer (e.g. including polysilicon) 161, a barrier layer 163 (e.g. including titanium and/or titanium nitride), a conductive layer 165 (e.g. including low-resistance metal such as tungsten, aluminum or copper), and a cap layer 167 (e.g. including silicon oxide, silicon nitride or silicon oxynitride), but not limited thereto. It should be noted that in principle, all the bit lines 160 are located parallel to each other on the insulating layer 130 above the substrate 110, wherein the insulating layer 130 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure including an oxide layer 131-nitride layer 133-oxide layer 135 (ONO), but not limited thereto. In addition, each bit line 160 extends across a plurality of the active regions, wherein the bit line 160 crossing each of the active regions may further extend into each of the active regions by a Bit Line Contact (BLC) 160a correspondingly formed thereunder.

It should be noted that the bit line contact 160a is integrally formed with the semiconductor layer 161 of the bit line 160 and directly contacts the underlying substrate 110 (i.e., the active region). On the other hand, the contacts 150 are also formed on the substrate 110 separately from each other and extend further into the active regions, so that each contact 150 can serve as a storage node plug (storage node contact, SNC) for the semiconductor device 100 and directly contact the underlying substrate 110 (including the active regions and the insulating region 101). In one embodiment, the contacts 150 are made of a low-resistance metal material such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and the contacts 150 and the bit lines 160 are insulated from each other by the spacer structures 140. In an embodiment, the spacer structure 140 may optionally have a single layer structure or a composite layer structure as shown in fig. 1, for example, but not limited to, a first spacer 141 (e.g., including silicon nitride), a second spacer 143 (e.g., including silicon oxide), and a third spacer 145 (e.g., including silicon nitride) sequentially stacked on the sidewalls of each bit line 160.

Referring to fig. 1 again, a plurality of storage node pads (SN pads) 180 are also formed in the dielectric layer 170 on the substrate 110, and are located above the contacts 150 and the bit lines 160 and are aligned with the contacts 150, respectively. In one embodiment, the storage node pad 180 also includes a low resistance metal material such as aluminum, titanium, copper, or tungsten, for example, but not limited to, a metal material different from the contact 150. In another embodiment, storage node pad 180 may alternatively be integrally formed with contact 150 and may comprise the same material. Subsequently, the capacitive structure 250 may continue to be formed over the storage node pad 180 to directly contact and electrically connect the underlying storage node pad 180.

In one embodiment, the fabrication process of the capacitor structure 250 includes, but is not limited to, the following steps. First, a support layer structure 190, for example comprising at least one layer of oxide material and at least one layer of nitride material alternately stacked, is formed on the dielectric layer 170 over the substrate 110. In the present embodiment, the support layer structure 190 includes, for example, a first support material layer 191 (including, for example, silicon oxide), a second support material layer 193 (including, for example, silicon nitride or silicon carbonitride), a third support material layer 195 (including, for example, silicon oxide), and a fourth support material layer 197 (including, for example, silicon nitride or silicon carbonitride, etc., but not limited thereto), which are sequentially stacked from bottom to top, preferably, the oxide material layer (including, for example, the first support material layer 191 and the third support material layer 195) may have a relatively large thickness, for example, about 5 times to 10 times the thickness of the nitride material layer (including, for example, the second support material layer 193 or the fourth support material layer 197), and the thickness of the nitride material layer (including, for example, the fourth support material layer 197) disposed at a position distant from the substrate 110 is preferably greater than the thickness of the nitride material layer (including, for example, the second support material layer 193) disposed at a position adjacent to the substrate 110, as shown in fig. 1, but not limited thereto, the thickness of the support layer 190 may reach, but not limited thereto, about 2000 a.

It should be understood by those skilled in the art that the specific number of stacks of the oxide material layers (e.g., the first support material layer 191 or the third support material layer 195) and the nitride material layers (e.g., the second support material layer 193 or the fourth support material layer 197) is not limited to the above number, but may be adjusted according to practical requirements, such as 3 layers, 4 layers, or other numbers. Then, a plurality of through holes 192 are formed in the support layer structure 190, penetrating through the fourth support material layer 197, the third support material layer 195, the second support material layer 193, and the first support material layer 191 in order, and aligning each storage node pad 180 below. As such, the top surface of each storage node pad 180 may be exposed from each of the via holes 192, respectively, as shown in fig. 1.

Next, as shown in fig. 2, a deposition process is performed on the substrate 110 to form an electrode material layer 200. In detail, the electrode material layer 200 is formed on the supporting layer structure 190 to cover the top surface of the fourth supporting material layer 197, the surface of each through hole 192 and the top surface of each storage node pad 180, wherein the electrode material layer 200 includes, but is not limited to, a low-resistance metal material such as aluminum, titanium, copper or tungsten.

Then, as shown in fig. 3, a first etching process P1, for example, a dry etching process is performed to remove the electrode material layer 200 covering the top surface of the fourth support material layer 197, so as to form a plurality of initial bottom electrode layers 210. Wherein, each of the initial bottom electrode layers 210 is formed in each of the through holes 192, and uniformly covers the top surface of each of the storage node pads 180 and the surface of each of the through holes 192, and may have a uniform first thickness T1 as a whole. In addition, each of the initial bottom electrode layers 210 is simultaneously covered on two opposite sidewalls of each of the through holes 192, and thus may have two first portions 211 extending upward and having the same height in a direction perpendicular to the substrate 110, wherein a top surface of each of the first portions 211 is coplanar with a top surface of the fourth supporting material layer 197, for example. Thus, each of the initial bottom electrode layers 210 may have a laterally symmetrical structure, such as a U-shaped structure as shown in fig. 3, but not limited thereto.

As shown in fig. 4, a plurality of mask patterns 220 are formed on the support layer structure 190 to cover a portion of the fourth support material layer 197 and a portion of the via 192, and a second etching process P2, for example, another dry etching process is performed through the mask patterns 220. In detail, each mask pattern 220 is formed on the support layer structure 190 in a manner of simultaneously covering any one of the through holes 192 and the support layer structure 190 on both sides thereof, and exposing two adjacent through holes 192 on both sides of the through hole 192, such that the remaining fourth support material layer 197 can be exposed from the mask pattern 220 and removed by the vertically downward etching process P21 in the second etching process P2 to expose the third support material layer 195 therebelow. On the other hand, when the remaining portion of the fourth support material layer 197 is removed, the first portion 211 exposed from the mask pattern 220 may be partially removed by the vertical downward etching process P21 and the lateral etching process P22 of the second etching process P2. The height of the exposed first portion 211 may be reduced by the vertically downward etching process P21, and the thickness of the exposed first portion 211 may be partially reduced by the lateral etching process P22, so that the second portion 213 having a lower height and being partially thinner may be formed.

It should be noted that, in the present embodiment, parameters of the lateral etching process P22 (such as etching temperature, etching rate, or etching selectivity) are further adjusted, so that the second portion 213 is intentionally formed with a uniform, relatively small second thickness T2 on top, and the inclined surface 215 gradually inclined downward toward the non-etched fourth support material layer 197 is formed on the second portion 213 according to the etching angle of the lateral etching process P22, so that a recess 217 with a notch toward the fourth support material layer 197 is formed on top of each second portion 213, as shown in fig. 4. In this manner, the top aperture of each of the through holes 192 exposed from the mask pattern 220 may be correspondingly enlarged. Also, note that the inclined surface 215 on the second portion 213 is located between the fourth support material layer 197 and the second support material layer 193, which are not etched, in the direction perpendicular to the substrate 110, such that the portion of the second portion 213 above the inclined surface 215 has a relatively smaller second thickness T2 and the portion below the inclined surface 215 has a relatively larger first thickness T1.

As shown in fig. 5, a third etching process P3, such as a dry etching process or a wet etching process with a relatively high etching selectivity, is performed through the mask pattern 220 to completely remove the third support material layer 195 exposed from the mask pattern 220 and the second support material layer 193 and the first support material layer 191 directly thereunder. In other words, the third etching process P3 removes the supporting layer structure 190 directly contacting each of the second portions 213, while leaving the supporting layer structure 190 directly contacting each of the first portions 211, and then completely removes the mask pattern 220.

Next, as shown in fig. 6, a fourth etching process P4, for example, an isotropic wet etching process is performed to completely remove the remaining third supporting material layer 195 and the first supporting material layer 191. Specifically, in the isotropic wet etching process, an etchant such as tetramethyl ammonium hydroxide (tetramethylammonium hydroxide, TMAH) is introduced, and the space generated after the support layer structure 190 is removed by the third etching process P3 is continuously removed from the remaining third support material layer 195 and the first support material layer 191, but not limited to the etchant. In this way, a plurality of bottom electrode layers 230, 232 may be formed, wherein each bottom electrode layer 230 has two first portions 211 extending upward and having the same height in the direction perpendicular to the substrate 110 to form a symmetrical U-shaped structure, and the bottom electrode layer 232 has a first portion 211 and a second portion 213 disposed opposite to each other in the direction perpendicular to the substrate 110 to form an asymmetrical U-shaped structure.

Meanwhile, the remaining second support material layer 193 (as shown in fig. 5) and the remaining fourth support material layer 197 (as shown in fig. 5) may form the first support layer 241 and the second support layer 243, respectively, and the first support layer 241 and the second support layer 243 sequentially disposed from bottom to top may together form the support structure 240 supporting the bottom electrode layers 230, 232 and directly contact and support the first portion 211 of each bottom electrode layer 230, 232. The top surface of the second supporting layer 243 may be flush with the top surface of the first portion 211 of each bottom electrode layer 230, 232 and higher than the top surface of the second portion 213, and the thickness of the second supporting layer 243 may be preferably greater than the thickness of the first supporting layer 241 disposed adjacent to the substrate 110, for example, about 2 to 5 times the thickness of the first supporting layer 241, as shown in fig. 6, but not limited thereto.

Then, as shown in fig. 7, a deposition process is performed on the substrate 110 to sequentially form the capacitor dielectric layer 234 and the top electrode layer 236, so that the bottom electrode layers 230, 232, the capacitor dielectric layer 234 and the top electrode layer 236 can together form the capacitor structure 250. In detail, the capacitor dielectric layer 234 is conformally covered on the exposed surfaces of the bottom electrode layers 230 and 232 and the dielectric layer 170, and the top electrode layer 236 fills the remaining space between the bottom electrode layers 230 and 232, and part of the capacitor dielectric layer 234 and the top electrode layer 236 may be further filled between the second supporting layer 243 and the first supporting layer 241, and further between the first supporting layer 241 and the dielectric layerBetween the mass layers 170. In one embodiment, the capacitor dielectric layer 234 comprises a high-k dielectric material, such as a material selected from hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO) ₄ ) Hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO ₂ ) Titanium oxide (TiO) ₂ ) And zirconia-alumina-zirconia (ZAZ), preferably comprising zirconia-alumina-zirconia; the top electrode layer 236 is made of low-resistance metal such as aluminum, titanium, copper or tungsten, preferably titanium, but not limited thereto.

Thus, the fabrication process of the capacitor structure 250 is completed. The capacitor structure 250 includes a plurality of capacitors extending vertically to serve as Storage Nodes (SN) of the semiconductor device 100, and the storage nodes can be electrically connected to transistor elements (not shown) of the semiconductor device 100 through the storage node pads 180 and the storage node plugs (i.e., the contacts 150), so that the capacitor structure 250 and the storage node plugs disposed on the substrate 110 can have a good contact relationship. Thus, the semiconductor device 100 of the present embodiment can form a dynamic random access memory (dynamic random access memory, DRAM) device, which is a minimum cell (memory cell) in a DRAM array formed by at least one of the transistor elements and at least one of the capacitors, for receiving voltage information from the bit line 160 and the buried word line.

According to the method of the first embodiment of the present utility model, when the fourth supporting material layer 197 is partially removed, the semiconductor device 100 etches the first portion 211 of the initial bottom electrode layer 210 by the etching process P21 vertically downward in the etching process (the second etching process P2 shown in fig. 4) to reduce the height of the first portion 211, and simultaneously reduces the thickness of the first portion 211 locally by the lateral etching process P22 in the etching process to form the second portion 213 with a lower height and a thinner locally. In this way, at least a portion of the bottom electrode layer 232 is formed by the first portion 211 and the second portion 213 with different heights, and has an asymmetric U-shaped structure. In addition, it should be specifically noted that the top of the second portion 213 has a recess 217 disposed toward the second supporting layer 243, so that the top aperture of each through hole 192 can be correspondingly enlarged to additionally pull the distance between the first portion 211 and the second portion 213 of each bottom electrode layer 230, 232 (as shown in fig. 4). In this operation, the deposition process of the capacitor dielectric layer 234 and the top electrode layer 236 that are formed later is performed more smoothly, so that the capacitor dielectric layer 234 can uniformly and conformally cover the bottom electrode layers 230 and 232, and the top electrode layer 236 can densely fill the remaining space, thereby forming the semiconductor device 100 with more optimized structure. Therefore, the manufacturing method of the semiconductor device 100 according to the first embodiment of the present utility model can effectively improve the manufacturing defects caused by the increase of the memory cell density, optimize the manufacturing process of the capacitor dielectric layer 234 and the top electrode layer 236, and further achieve the effect of improving the functional and structural reliability of the semiconductor device 100.

In addition, it should be readily understood by those skilled in the art that other aspects of the present utility model are possible in forming the semiconductor device and the method of fabricating the same in order to meet the actual product requirements, and are not limited to the foregoing. For example, when the support layer structure 190 is partially removed through the mask pattern 220, the remaining portion of the fourth support material layer 197 and the third support material layer 195 thereunder may be removed by the second etching process P2, and then the remaining third support material layer 195 may be completely removed by an isotropic wet etching process. Then, the exposed second support material layer 193 and the first support material layer 191 below the second support material layer 193 are removed through the mask pattern 220 by using a subsequent etching process, and the remaining first support material layer 191 is completely removed by using another isotropic wet etching process. Further embodiments or variations of the method of the semiconductor device of the present utility model are described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present utility model are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 8 to 9, schematic steps of a method for fabricating a semiconductor device 300 according to a second embodiment of the utility model are shown. The manufacturing steps of the semiconductor device 300 in this embodiment are substantially the same as those of the semiconductor device 100 in the first embodiment, and will not be repeated here. The main difference between the present embodiment and the foregoing first embodiment is that, in the present embodiment, by adjusting the parameters of the second etching process P5, the vertical downward etching process P51 does not affect the height of the first portion 211, and only the lateral etching process P52 locally reduces the thickness of the exposed first portion 211, so as to form the second portion 313 with a height equal to the height of the first portion 211 and a local thinner thickness.

It should be noted that the second portion 313 is also partially formed with a second thickness T2 that is uniform throughout and relatively small, and an inclined surface 315 that is gradually inclined downward to face the non-etched fourth support material layer 197, so that a recess 317 is formed at the top of the second portion 313 and is disposed toward the fourth support material layer 197, as shown in fig. 8. Note that the inclined surface 315 on the second portion 313 is located on the top surface and bottom surface of the non-etched fourth support material layer 197 in the direction perpendicular to the substrate 110, so that the portion of the second portion 313 above the inclined surface 315 has a relatively smaller second thickness T2 and the portion below the inclined surface 315 has a relatively larger first thickness T1. Thus, at least a portion of the bottom electrode layer 332 is formed by the first portion 211 and the second portion 313 which have the same height and the top surface is flush with the top surface of the fourth supporting material layer 197, wherein the bottom electrode layer 332 has an asymmetric U-shaped structure as a whole due to the partial thickness of the second portion 313 being thinner. In this operation, the top aperture of each of the through holes 192 exposed from the mask pattern 220 may be correspondingly enlarged, which is advantageous for the subsequent deposition process.

Then, the third etching process P3 shown in fig. 5, the fourth etching process P4 shown in fig. 6, and the deposition process of the capacitor dielectric layer 234 and the top electrode layer 236 shown in fig. 7 in the foregoing embodiment are continued to form the semiconductor device 300 shown in fig. 9, so that the bottom electrode layers 230, 332, the capacitor dielectric layer 234 and the top electrode layer 236 can form the capacitor structure 350 together. In this embodiment, the fabrication and material selection of the capacitor dielectric layer 234 and the top electrode layer 236 are substantially the same as those of the first embodiment, and will not be repeated here.

Thus, the semiconductor device 300 of the present embodiment is completed. The capacitor structure 350 of the present embodiment also includes a plurality of vertically extending capacitors formed by sequentially stacking the bottom electrode layers 230, 332, the capacitor dielectric layer 234 and the top electrode layer 236, which serve as storage nodes of the semiconductor device 300, and are electrically connected to transistor elements (not shown) of the semiconductor device 300 through the storage node pads 180 and the storage node plugs (i.e., the contacts 150). Thus, the semiconductor device 300 of the present embodiment can also form a DRAM device.

According to the method of the second embodiment of the present utility model, when the fourth supporting material layer 197 is partially removed, the semiconductor device 300 is partially reduced in thickness by the lateral etching process P52 in the etching process (the second etching process P5 shown in fig. 8) to form the partially thinner second portion 313. In this manner, at least a portion of the bottom electrode layer 332 includes a second portion 313 having the same height as the first portion 211, the top surface of which is flush with the top surface of the second supporting layer 243, but a partial thickness of which is thinner, and has an overall asymmetric U-shaped structure, wherein the inclined surface 315 of the second portion 313 is higher than the bottom surface of the second supporting layer 243 in a direction perpendicular to the substrate 110. Under this setting, the top of the second portion 313 also has a recess 317 formed toward the second supporting layer 243 to additionally pull the distance between the first portion 211 and the second portion 313 of each bottom electrode layer 230, 332 (as shown in fig. 8), which is beneficial for the subsequent deposition process of the capacitor dielectric layer 234 and the top electrode layer 236. Therefore, the manufacturing method of the semiconductor device 300 according to the second embodiment of the utility model can also effectively improve the manufacturing defects caused by the increase of the memory cell density, optimize the manufacturing process of the capacitor dielectric layer 234 and the top electrode layer 236, and further achieve the effect of improving the functional and structural reliability of the semiconductor device 300.

Referring to fig. 10 to 11, schematic steps of a method for fabricating a semiconductor device 400 according to a third embodiment of the utility model are shown. The manufacturing steps of the semiconductor device 400 in this embodiment are substantially the same as those of the semiconductor device 100 in the first embodiment, and will not be repeated here. The main difference between the present embodiment and the foregoing first embodiment is that in the present embodiment, when the mask pattern 220 shown in fig. 5 is removed, the remaining fourth support material layer 197 and the first portion 211 shown in fig. 5 are partially etched together.

In detail, in this embodiment, when the mask pattern 220 is removed, the first portion 411 with a smaller height and the second supporting layer 443 with a smaller thickness are further formed, so that the height of the first portion 411 can be the same as the height of the second portion 213 and slightly lower than the top surface of the second supporting layer 443, and then the fourth etching process P6 is performed to completely remove the remaining third supporting material layer 195 and the first supporting material layer 191 as shown in fig. 5. Thus, part of the bottom electrode layer 430 is composed of two first portions 411 having the same height and uniform first thickness T1, and the other part of the bottom electrode layer 432 is composed of the first portions 411 and the second portions 213 having the same height and lower top surface than the top surface of the second supporting layer 443, wherein the bottom electrode layer 432 has an asymmetric U-shaped structure as a whole due to the thinner local thickness of the second portions 213. Note that in the present embodiment, the inclined surface 215 on the second portion 213 is still located between the second support layer 443 and the first support layer 241 in the direction perpendicular to the substrate 110, so that the portion of the second portion 213 above the inclined surface 215 has a relatively smaller second thickness T2 and the portion below the inclined surface 215 has a relatively larger first thickness T1. In this operation, the top aperture of the partial via 192 can be correspondingly enlarged, which is advantageous for the subsequent deposition process.

Then, as shown in fig. 11, the deposition process is continued to form a capacitor dielectric layer 234 and a top electrode layer 236. In this manner, bottom electrode layers 430, 432, capacitive dielectric layer 234, and top electrode layer 236 may collectively form capacitive structure 450. In this embodiment, the fabrication and material selection of the capacitor dielectric layer 234 and the top electrode layer 236 are substantially the same as those of the first embodiment, and will not be repeated here. Thus, the semiconductor device 400 of the present embodiment is completed. The capacitor structure 450 of the present embodiment also includes a plurality of capacitors extending vertically to serve as storage nodes of the semiconductor device 400 and electrically connected to transistor elements (not shown) of the semiconductor device 400 through the storage node pads 180 and the storage node plugs (i.e., the contacts 150). Thus, the semiconductor device 400 of the present embodiment can also form a DRAM device.

According to the method of fabricating the third embodiment of the present utility model, the semiconductor device 400 partially etches the remaining fourth support material layer 197 and the first portion 211 together through the etching process when the mask pattern 220 is removed. Thus, a portion of the bottom electrode layer 430 is formed by two first portions 411 having the same height and a top surface slightly lower than the top surface of the second supporting layer 443, and another portion of the bottom electrode layer 432 is formed by the first portions 411 and the second portions 213 having the same height and a top surface lower than the top surface of the second supporting layer 443. In this arrangement, the top of the second portion 213 also has a recess 217 recessed toward the second supporting layer 443 to additionally pull the distance between the first portion 411 and the second portion 313 of each bottom electrode layer 430, 432 (as shown in fig. 10), which is advantageous for the subsequent deposition process of the capacitor dielectric layer 234 and the top electrode layer 236. Therefore, the manufacturing method of the semiconductor device 400 in the third embodiment of the utility model can also effectively improve the manufacturing defects caused by the increase of the memory cell density, optimize the manufacturing process of the capacitor dielectric layer 234 and the top electrode layer 236, and further achieve the effect of improving the function and the structural reliability of the semiconductor device 400.

Referring to fig. 12, a schematic diagram of steps of a method for fabricating a semiconductor device 500 according to a fourth embodiment of the utility model is shown. The manufacturing steps of the semiconductor device 500 in this embodiment are substantially the same as those of the semiconductor device 100 in the first embodiment, and will not be repeated here. The main difference between this embodiment and the foregoing first embodiment is that in this embodiment, by adjusting various parameters of the etching process, the inclined surface 515 of the second portion 513 may also be made to face the inclined surface 515 of the adjacent second portion 513. In this way, the head space between two adjacent second portions 513 may be correspondingly increased, again facilitating a subsequent deposition process for forming the capacitive dielectric layer 234 and the top electrode layer 236.

According to an embodiment of the present utility model, by adjusting different parameters of the etching process, the top surface of the second portion 513 is flush with the top surface of the first portion 211, such that the inclined surface 515 is located between the bottom surface of the second supporting layer 243 and the first supporting layer 241 in the direction perpendicular to the substrate 110, as shown in fig. 12. However, in another embodiment, the parameters of the etching process are modified according to actual needs, so that the top surface of the second portion 513 is not flush with the top surface of the second supporting layer 243, for example, but not limited thereto. In addition, in another embodiment (not shown), the parameters of the etching process may be modified according to the actual requirement, so that the first portion 211 may have a top surface that is flush with the second portion 513, and the top surface may be flush with the top surface of the second supporting layer 243 as shown in fig. 9, or may be lower than the top surface of the second supporting layer 243 as shown in fig. 11, and the inclined surface 515 on the second portion 513 may be higher than the bottom surface of the second supporting layer 243 in the direction perpendicular to the substrate 110, and may be between the bottom surface and the top surface of the second supporting layer 243, or may be located between the bottom surface of the second supporting layer 243 and the first supporting layer 241 as shown in fig. 11.

Therefore, the manufacturing method of the semiconductor device 500 according to the fourth embodiment of the present utility model also effectively improves manufacturing defects caused by the increase of the memory cell density, optimizes the manufacturing process of the capacitor dielectric layer 234 and the top electrode layer 236, and further achieves the effect of improving the functional and structural reliability of the semiconductor device 500.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a plurality of storage node pads disposed on the substrate;

the capacitor structure is arranged on the storage node bonding pad and comprises a plurality of capacitors, each capacitor comprises a bottom electrode layer, a capacitor dielectric layer and a top electrode layer from bottom to top, and the top of the bottom electrode layer is provided with a groove; and

the supporting structure comprises a plurality of first supporting layers and a plurality of second supporting layers from bottom to top, and is connected with two adjacent capacitors, wherein the grooves face each second supporting layer respectively

And a support layer.

2. The semiconductor device of claim 1, wherein the bottom electrode layer further comprises an inclined surface, the bottom electrode layer having a first thickness below the inclined surface and a second thickness above the inclined surface, the first thickness being greater than the second thickness.

3. The semiconductor device according to claim 2, wherein the inclined surface is located between the second support layer and the first support layer in a direction perpendicular to the substrate.

4. The semiconductor device according to claim 2, wherein the inclined surface is higher than a bottom surface of the second support layer in a direction perpendicular to the substrate.

5. The semiconductor device of claim 1, wherein the bottom electrode layer comprises first and second portions extending upward, the recess is disposed on the second portion, and a top surface of the second portion is lower than a top surface of the second support layer.

6. The semiconductor device of claim 5, wherein a top surface of the first portion is flush with the top surface of the second support layer.

7. The semiconductor device of claim 5, wherein a top surface of the first portion is lower than the top surface of the second support layer.

8. The semiconductor device according to claim 5, wherein a top surface of the first portion or the top surface of the second portion is higher than a bottom surface of the second support layer.

9. The semiconductor device of claim 5, wherein each of the first portions directly contacts each of the first support layers and each of the second support layers of the support structure.

10. The semiconductor device of claim 1, wherein each bottom electrode layer has a symmetrical or asymmetrical U-shaped structure.

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