CN117574808B - Low-energy consumption MCU circuit, chip and control method - Google Patents
Low-energy consumption MCU circuit, chip and control method Download PDFInfo
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Abstract
The patent relates to the field of chip low-power design and discloses a low-energy consumption MCU circuit, a chip and a control method, wherein the low-energy consumption MCU circuit comprises a CLK clock signal input circuit, an IR instruction decoding circuit, an SRAM clock control circuit, an SRAM circuit, an SFR clock control circuit and an SFR circuit. The IR instruction decoding circuit outputs control signals of the SRAM clock control circuit and the SFR clock control circuit according to the instructions, and when the SRAM circuit or the SFR circuit does not work, the IR instruction decoding circuit controls the SRAM clock control circuit and the SFR clock control circuit to be turned off according to the instructions, so that the clock tree structure of the SFR or the SRAM circuit does not work, and the use power consumption is greatly reduced.
Description
Technical Field
The invention relates to a low-power consumption design method, in particular to a low-energy consumption MCU circuit, a chip and a control method.
Background
In the design of a digital synchronous circuit, clock edges of all registers in a clock domain must arrive at the same time to meet design requirements, and to achieve the effect, special processing of a clock tree must be performed on clock signals in the clock domain, and clock tree is used to ensure that clock offsets reaching the registers in the clock domain are consistent, so that normal operation of the digital circuit is ensured.
The clock tree ensures the time sequence safety and simultaneously brings great power consumption. As shown in fig. 1, the clock tree generally consists of a buffer and an inverter, the clock signal is the signal with the highest flip rate in the design, and is also an important source of power consumption, the power consumption of the clock tree may be up to 30% of the whole design power consumption, and with the progress of the process and the increase of the design scale, the power consumption generated by the clock tree is higher and higher in proportion to the power consumption of the whole digital integrated circuit, and can be almost 50% in some cases. By adopting the gating clock, the power consumption generated by the clock can be very effectively reduced. However, as shown in fig. 2, a gating unit is added to each register for gating, which increases the area and generates power consumption due to the continuous inversion of the clock CLK.
The clock tree structure in the current MCU design is shown in fig. 3, in which registers in the analog SFR/ALU/PC/SRAM are designed by the clock tree of fig. 4, and a gated clock design similar to that of fig. 2 may be used. It can be seen that when CLK is inverted, there are a large number of buffers or inverters inverting, thereby generating power consumption, even with the gating clock of fig. 2, the input second output of the AND gate AND the LATCH clock still generate power consumption due to the inversion of CLK.
Disclosure of Invention
In order to solve the problem of large power consumption of the clock tree in the background technology, the embodiment of the invention provides the low-energy consumption MCU circuit, the clock is closed from the source, and the whole module can stop running when other modules are operated, so that the power consumption is greatly reduced.
The embodiment of the invention provides a low-energy consumption MCU circuit, which comprises:
the clock signal input circuit is connected with the IR instruction decoding circuit, the SRAM clock control circuit and the SFR clock control circuit, the output end of the IR instruction decoding circuit is respectively connected with the first input end of the SRAM clock control circuit and the first input end of the SFR clock control circuit, the output end of the SRAM clock control circuit is connected with the SRAM circuit, a clock tree circuit is arranged in the SRAM circuit, the output end of the SFR clock control circuit is connected with the SFR circuit, and a clock tree structure is arranged in the SFR circuit;
the IR instruction decoding circuit outputs control signals of the SRAM clock control circuit and the SFR clock control circuit according to the instruction, and when the SRAM circuit or the SFR circuit does not work, the IR instruction decoding circuit controls the SRAM clock control circuit and the SFR clock control circuit to be turned off according to the instruction, so that the clock tree structure of the SFR or the SRAM circuit does not work.
Optionally, the CLK clock signal input circuit includes a CLK signal input terminal and a first clock tree structure, wherein one end of the first clock tree structure is connected to the CLK signal input terminal, and the other end is respectively connected to the IR instruction decoding circuit, the SRAM clock control circuit, the SFR clock control circuit, and the ALU arithmetic logic circuit.
Optionally, the IR instruction decoding circuit includes a program pointer PC, a program memory, and a decoder, where one end of the program pointer PC is connected to the buffer of the first clock tree structure, one end of the program pointer PC is connected to the program memory, one end of the program memory is connected to the program pointer PC, the other end of the program memory is connected to the decoder, one end of the decoder is connected to the program pointer PC, and one end of the decoder is connected to the SRAM clock control circuit and the SFR clock control circuit, and the program memory is used to provide instruction signals required by the circuit on one hand, and stores the CLK clock signal on the other hand.
Optionally, the SRAM clock control circuit includes a first latch, a first logic and gate circuit, where a first input terminal of the first latch is connected to the decoder output terminal, a second input terminal is connected to a buffer of the first clock tree structure, and is connected to a second output terminal of the first logic and gate circuit, a first output terminal of the first latch is connected to a first input terminal of the first logic and gate circuit, a first output terminal of the first logic and gate circuit is connected to a first output terminal of the first latch, a second output terminal of the first logic and gate circuit is connected to a second output terminal of the first latch, and an output terminal of the first logic and gate circuit is connected to the SRAM circuit.
Optionally, the SRAM circuit includes a second clock tree structure and a static random access memory, wherein the first gated clock circuit output is coupled to the second clock tree structure, and the second clock tree structure is coupled to the static random access memory.
Optionally, the SFR clock control circuit includes a second latch, and a second logic and gate circuit, where a first input end of the second latch is connected to an output end of the decoder, a second input end of the second latch is connected to a buffer of the first clock tree structure and is connected to a second output port of the second logic and gate circuit, a first output end of the second latch is connected to a first output port of the second logic and gate circuit, a first input end of the second logic and gate circuit is connected to a first output end of the second latch, a second input end of the second logic and gate circuit is connected to a second input port of the second latch, and an output end of the second logic and gate circuit is connected to the SFR circuit.
Optionally, the SFR circuit includes a third clock tree structure and a special function register, wherein an output terminal of the second gating clock circuit is connected to the third clock tree structure, and the third clock tree structure is connected to the special function register.
Optionally, the method further comprises: an arithmetic logic unit ALU connected to the inverter of the first clock tree structure.
The embodiment of the invention also provides a chip with the low-energy consumption MCU circuit.
The embodiment of the invention also provides a control method adopting the low-energy consumption MCU circuit, which comprises the following steps:
the IR instruction decoding circuit outputs control signals of the SRAM clock control circuit and the SFR clock control circuit according to the instruction, and when the SRAM circuit or the SFR circuit does not work, the IR instruction decoding circuit controls the SRAM clock control circuit and the SFR clock control circuit to be turned off according to the instruction, so that the clock tree structure of the SFR or the SRAM circuit does not work.
In summary, the low-energy consumption MCU circuit and the method have the following advantages:
1. the low-energy consumption MCU circuit can realize that when the SRAM circuit or the SFR circuit does not work, the IR instruction decoding circuit controls the SRAM clock control circuit and the SFR clock control circuit to be turned off according to the instruction, so that the clock tree structure of the SFR or the SRAM circuit does not work, and the use power consumption is greatly reduced;
2. the low-energy consumption MCU circuit has simple structure and strong expandability, and greatly saves the cost.
Drawings
FIG. 1 is a prior art clock tree structure;
FIG. 2 is a prior art register gating clock structure;
FIG. 3 is a prior art clock tree structure in an MCU circuit;
the prior art MCU circuit of fig. 4 has a register clock tree structure inside the module SFR/ALU/PC/SRAM;
FIG. 5 is a circuit diagram of a low-power MCU according to an embodiment of the present invention;
FIG. 6 is a circuit structure diagram of a low-energy MCU according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a clock tree structure of an SRAM circuit in accordance with an embodiment of the present invention;
FIG. 8 is a schematic circuit diagram of the clock tree structure of the SFR circuit in an embodiment of the present invention.
Detailed Description
The technology in the embodiments of the present invention will be clearly and completely described in the following with reference to the drawings and detailed description of the embodiments of the present invention.
An embodiment of the present invention provides a low-power MCU circuit, as shown in fig. 5, including:
the clock signal input circuit 10 is respectively connected with the IR instruction decoding circuit 20, the SRAM clock control circuit 30 and the SFR clock control circuit 40, the SRAM clock control circuit 30 and the SFR clock control circuit 60, the IR instruction decoding circuit 20 is connected with the SRAM clock control circuit 30 and the SFR clock control circuit 40, the SRAM clock control circuit 30 is connected with the SRAM circuit, and the SFR clock control circuit 40 is connected with the SFR circuit 60;
specifically, the CLK clock signal input circuit 10 includes:
the clock signal processing circuit comprises a CLK input signal end and a first clock tree structure, wherein one end of the first clock tree structure is connected with the CLK input end, and the other end of the first clock tree structure is respectively connected with an IR instruction decoding circuit, an SRAM clock control circuit, an SFR clock control circuit and an ALU arithmetic logic circuit. The first clock tree structure is used for increasing the driving capability of the CLK clock signal, so that the CLK clock signal has better rising edge and falling edge.
The IR instruction decoding circuit 20 includes: the system comprises a program pointer PC, a program memory and a decoder, wherein one end of the program pointer PC is connected with a buffer in a first clock tree structure, one end of the program pointer PC is connected with the program memory, one end of the program memory is connected with the program pointer PC, the other end of the program memory is connected with the decoder, one end of the decoder is connected with the program pointer PC, and one end of the decoder is connected with an SRAM clock control circuit and an SFR clock control circuit. The program pointer PC is used for storing an instruction address to be executed next time of the CLK clock signal, ensuring that the CLK clock signal is executed in order, the program memory is used for storing the CLK clock signal and the instruction signal, and the decoder is used for converting the CLK clock signal and the instruction signal in the program memory into clock control signals and transmitting the clock control signals to the SRAM clock control circuit 30 and the SFR clock control circuit 40.
The SRAM clock control circuit 30 comprises: a first LATCH1, a first logic AND circuit AND1, wherein a first input end of the first LATCH1 is connected with an output end of the decoder, a second input end of the first LATCH1 is connected with a buffer of a first clock tree structure AND is connected with a second output end of the first logic AND circuit AND1, the first output end of the first LATCH1 is connected with the first input port of the first logic AND gate circuit AND1, the first output end of the first logic AND gate circuit AND1 is connected with the first output end of the first LATCH, the second output end of the first LATCH1 is connected with the second output port of the first LATCH, AND the output end of the first logic AND gate circuit AND1 is connected with the SRAM circuit. The SRAM clock control circuit 30 is turned on and off by a clock control signal, the gate is turned on when the clock signal is high, signals in the circuit can be transferred, and the gate is turned off when the clock signal is low, i.e. no signals are transferred.
The SFR clock control circuit 40 includes: a second LATCH2, a second logic AND gate circuit AND2, wherein a first input end of the second LATCH2 is connected with an output end of the decoder, a second input end of the second LATCH2 is connected with a buffer of the first clock tree structure AND is connected with a second output port of the second logic AND gate circuit AND2, the first output end of the second LATCH2 is connected to the first output port of the second logic AND gate circuit AND2, the first input end of the second logic AND gate circuit AND2 is connected to the first output end of the second LATCH2, the second input end of the second logic AND gate circuit AND2 is connected to the second input port of the second LATCH, AND the output end of the second logic AND gate circuit AND2 is connected to the SFR circuit. The SFR clock control circuit 40 is turned on and off by the clock control signal, the gate is turned on when the clock signal is at high level, the signal in the circuit can be transmitted, the gate is turned off when the clock signal is at low level, i.e. the signal is not transmitted, the clock has the advantages that the transmission of the signal can be controlled, the probability of time sequence noise is reduced, and the stability and the reliability of the system are improved.
The SRAM circuit 50 has a third clock tree structure and a SRAM, as shown in fig. 7, where the output of the first gated clock circuit is connected to the third clock tree structure, and the third clock tree structure is connected to the SRAM, and this circuit can increase the data access speed, reduce the memory access delay, increase the memory utilization, relieve the memory pressure, increase the system scalability, and increase the system performance and response speed as a whole.
The SFR circuit 60 includes a third clock tree structure and special function registers, as shown in fig. 8, where the output end of the second gating clock circuit is connected to the third clock tree structure, and the third clock tree structure is connected to the special function registers, where the SFR circuit is a register for managing hardware modules, and can control, select, manage, and store the working modes, conditions, states, and results of each part in the single chip microcomputer.
Referring to fig. 5, the control method of the low-energy MCU circuit according to the embodiment of the present invention includes:
the MCU data operation instruction is decoded to obtain a read-write signal of an SRAM or a write signal of an SFR, when the signal is 1, CLK_SFR or CLK_SRAM is a clock signal, and when the CLK_SRAM and the CLK_SFR clock signals are inverted, a large number of buffers or inverters in CLK_SRAM and CLK_SFR clock trees are inverted to generate a large amount of power consumption; when the signal is 0, CLK_SFR or CLK_SRAM has no clock signal, and is of a fixed low level, when the instruction IR of MCU carries out read-write operation or SFR write operation on the SRAM, the input clocks of the SFR and the SRAM circuit are of a fixed low level, so that the clock tree of the whole module does not work, and the power consumption is greatly reduced.
In particular, the method comprises the steps of,
and S1.CLK clock signal input, which provides clock signals for the IR instruction decoding circuit, the SRAM clock control circuit and the SFR clock control circuit.
Step S2, the clock signal has better rising edge and falling edge through the buffer of the first clock tree structure, the clock signal is stored into the program memory together with the MCU data operation instruction after the next instruction address to be executed is acquired through the program pointer PC, the decoder converts the instruction signal and the clock signal in the program memory into an SRAM read-write signal and an SFR write signal, the SRAM read-write signal is transmitted to the SRAM clock control circuit, and the SFR write signal is transmitted to the SFR clock control circuit.
S3, the SRAM clock control circuit and the SFR clock control circuit control the whole circuit to work by taking the received control signals as EN signals, and when the SRAM read-write signals and the SFR write signals are 1, CLK_SRAM and CLK_SFR are clock signals; when the SRAM read/write signal and the SFR write signal are 0, CLK_SFR or CLK_SRAM has no clock signal and is at a fixed low level.
Step S4, when the CLK_SRAM and CLK_SFR clock signals are inverted, a plurality of buffers and inverters in the clock tree of the CLK_SRAM signal and the CLK_SFR signal are simultaneously inverted (as shown in figures 7 and 8), so that power consumption is generated; when CLK_SFR or CLK_SRAM is at a fixed low level, and instruction IR of MCU performs read-write operation or SFR write operation on SRAM, the input clocks of SFR and SRAM circuits are at a fixed low level, and clock trees (shown in FIG. 7 and FIG. 8) of CLK_SRAM signal and CLK_SFR signal do not work, thereby greatly reducing power consumption.
In this process, the ALU arithmetic logic circuit works normally, and the power consumption remains unchanged.
In summary, the low-power consumption MCU circuit of the invention can ensure that MCU data operation is normally carried out, and can greatly reduce system power consumption.
Finally, any modification or equivalent replacement of some or all of the technical features by means of the structure of the device according to the invention and the technical solutions of the examples described, the resulting nature of which does not deviate from the corresponding technical solutions of the invention, falls within the scope of the structure of the device according to the invention and the patent claims of the embodiments described.
Claims (10)
1. A low-power MCU circuit comprising:
the clock signal input circuit is connected with the IR instruction decoding circuit, the SRAM clock control circuit and the SFR clock control circuit, the output end of the IR instruction decoding circuit is respectively connected with the first input end of the SRAM clock control circuit and the first input end of the SFR clock control circuit, the output end of the SRAM clock control circuit is connected with the SRAM circuit, a clock tree circuit is arranged in the SRAM circuit, the output end of the SFR clock control circuit is connected with the SFR circuit, and a clock tree structure is arranged in the SFR circuit;
the IR instruction decoding circuit outputs control signals of the SRAM clock control circuit and the SFR clock control circuit according to the instruction, and when the SRAM circuit or the SFR circuit does not work, the IR instruction decoding circuit controls the SRAM clock control circuit and the SFR clock control circuit to be turned off according to the instruction, so that the clock tree structure of the SFR or the SRAM circuit does not work.
2. The low power MCU circuit of claim 1, wherein the CLK clock signal input circuit comprises a CLK signal input and a first clock tree structure, wherein one end of the first clock tree structure is connected to the CLK signal input and the other end is connected to the IR command decoder circuit, the SRAM clock control circuit, the SFR clock control circuit, and the ALU arithmetic logic circuit, respectively.
3. The low power MCU circuit of claim 1, wherein the IR instruction decoder circuit comprises a program pointer PC, a program memory, and a decoder, wherein the program pointer PC is connected to the buffer of the first clock tree structure at one end, the program memory is connected to the program pointer PC at one end, the decoder is connected to the program pointer PC at the other end, the SRAM clock control circuit and the SFR clock control circuit are connected to one end of the decoder, and the program memory is used to provide the instruction signals required by the circuit and store the CLK clock signal.
4. The low power MCU circuit of claim 1, wherein the SRAM clock control circuit comprises a first gated clock circuit having a first input coupled to an output of the IR instruction decode circuit, a second input coupled to a buffer of a first clock tree structure, a first output coupled to the SRAM circuit, the first gated clock circuit comprising: the first input end of the first latch is connected with the output end of the decoder, the second input end of the first latch is connected with the buffer of the first clock tree structure and is connected with the second output end of the first logic AND gate, the first output end of the first latch is connected with the first input port of the first logic AND gate, the first output end of the first logic AND gate is connected with the first output end of the first latch, the second output end of the first logic AND gate is connected with the second output port of the first latch, and the output end of the first logic AND gate is connected with the SRAM circuit.
5. The low power MCU circuit of claim 1, wherein the SRAM circuit comprises a second clock tree structure and a static random access memory, wherein the first gated clock circuit output is coupled to the second clock tree structure, the second clock tree structure being coupled to the static random access memory.
6. The low power MCU circuit of claim 1, wherein the SFR clock control circuit comprises a second gating clock circuit having a first input coupled to the output of the IR instruction decode circuit, a second input coupled to the buffer of the first clock tree structure, a first output coupled to the SRAM circuit, the second gating clock circuit comprising: the first input end of the second latch is connected with the output end of the decoder, the second input end of the second latch is connected with the buffer of the first clock tree structure and is connected with the second output port of the second logic AND gate, the first output end of the second latch is connected with the first output port of the second logic AND gate, the first input end of the second logic AND gate is connected with the first output end of the second latch, the second input end of the second logic AND gate is connected with the second input port of the second latch, and the output end of the second logic AND gate is connected with the SFR circuit.
7. The low power MCU circuit of claim 1, wherein the SFR circuit comprises a third clock tree structure and a special function register, wherein the second gating clock circuit output is coupled to the third clock tree structure, the third clock tree structure being coupled to the special function register.
8. The low power MCU circuit of claim 1, further comprising: an arithmetic logic unit ALU connected to the inverter of the first clock tree structure.
9. A chip having the low power MCU circuit of any one of claims 1 to 8.
10. A control method employing the low-power MCU circuit of claim 1, comprising:
the IR instruction decoding circuit outputs control signals of the SRAM clock control circuit and the SFR clock control circuit according to the instruction, and when the SRAM circuit or the SFR circuit does not work, the IR instruction decoding circuit controls the SRAM clock control circuit and the SFR clock control circuit to be turned off according to the instruction, so that the clock tree structure of the SFR or the SRAM circuit does not work.
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