CN116009647A

CN116009647A - Chip for reducing power consumption on clock tree and clock control method

Info

Publication number: CN116009647A
Application number: CN202211593144.3A
Authority: CN
Inventors: 包莉娜; 仝传连; 陈磊; 周祥标
Original assignee: Xiaohua Semiconductor Co ltd
Current assignee: Xiaohua Semiconductor Co ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-04-25

Abstract

The invention discloses a chip structure for reducing power consumption on a clock tree, which comprises a clock control module and a peripheral I P module. The clock control module comprises a first clock gating unit and a second clock gating unit, wherein the first clock gating unit is enabled through a configuration request signal and outputs a CPU configuration register clock, and the second clock gating unit is enabled through a function request signal and outputs a peripheral module working clock. The peripheral I P module includes a configuration module and a functional module. The configuration module includes a first register for CPU configuration, which uses a CPU configuration register clock as a clock signal and outputs a configuration request signal, and the function module includes a second register, i.e., a function register of the peripheral I P, which uses a peripheral module operation clock as a clock signal and outputs a function request signal. By dividing the clocks required by the peripheral I P into 2, the corresponding clock request signal is asserted to acquire the clock only when needed, effectively reducing power consumption on the clock tree.

Description

Chip for reducing power consumption on clock tree and clock control method

Technical Field

The invention relates to the technical field of chip design, in particular to a chip for reducing power consumption on a clock tree and a clock control method.

Background

The peripheral IP in the chip is also commonly referred to as a peripheral IP core (Peripheral IP Core), which is a generic term for peripheral dedicated function IP cores within the system chip, except for embedded CPUs, including serial bus interfaces, memory controllers, and the like. The peripheral IP generally operates under the control of a CPU that manages the peripheral by reading/writing its registers. The clock of the IP peripheral is given by a clock control module, and the clock is input to the peripheral IP through a network structure which is balanced and built by a plurality of buffer cells after the clock control module outputs the clock, so as to form a clock tree.

Currently, power consumption has become a primary consideration or constraint in many application fields. When the chip scale of the digital circuit is larger and the frequency is faster, the structure of the clock tree becomes larger and more complex, so that the consumed power consumption on the clock tree is higher and higher in proportion to the total power consumption of the chip, and some data show that the consumed power consumption of the clock tree is 30% -70% of the total power consumption of the chip.

Fig. 1 shows a conventional clock tree structure, as shown in fig. 1, a clock control module is controlled to endow an external IP clock in a software control manner, and a clock gating (clock gating) unit is automatically inserted by a tool when the back end is synthesized. Specifically, as shown in fig. 1, the clk_gate cell in the peripheral IP is automatically plugged in by a tool when it is integrated, and is typically plugged in the leaf terminal, i.e. near the register. In addition, the software controlled clk_gate cell is manually added in the clock control module. In practical application, normally, only when a certain peripheral IP is used, software control turns on clock enabling of clk_gate cell of the clock control module, so that a register in the corresponding peripheral IP obtains ip1_clk_i, and at this time, buffer units buffer on clock tree paths 1, 2, 3 and 4 are always turned over, and power consumption is consumed. However, in practice, for the peripheral IP, buffers on the same time paths 1, 2, 3, 4 do not have to be flipped, for example, when the registers 3, 4 need clocks, the registers 1, 2 do not need clocks, and then flipping on the clock tree paths 1, 2 wastes power consumption.

Disclosure of Invention

Aiming at solving part or all of the problems in the prior art and solving unnecessary power consumption waste on a clock tree to enable a chip to realize ultra-low power consumption, the first aspect of the invention provides a chip for reducing power consumption on the clock tree, which comprises the following components:

a clock control module, comprising:

a first clock gating unit which outputs a CPU configuration register clock through configuration request signal enable; and

a second clock gating unit which outputs a peripheral module working clock through the enabling of the function request signal; and

peripheral IP module, include:

the configuration module comprises a first register, wherein the first register is used for CPU configuration, a CPU configuration register clock is used as a clock signal, and the configuration module outputs a configuration request signal; and

the functional module comprises a second register, the second register comprises a functional register of an external IP, the functional register adopts an external module working clock as a clock signal, and the functional module outputs a functional request signal.

Further, the configuration request signal and the function request signal are hardware clock request signals.

Further, the configuration module outputs a configuration request signal when the CPU writes a signal to the peripheral IP operation.

Further, the function module outputs a function request signal when the CPU configures a configuration bit for enabling operation of the peripheral IP.

Further, the configuration module includes a third clock gating unit, which corresponds to the first register one by one, a clock end of the third clock gating unit is connected to an output end of the first clock gating unit, and the output end is connected to the clock end of the first register.

Further, the functional module includes a fourth clock gating unit, which corresponds to the functional registers of the peripheral IP one by one, where a clock end of the fourth clock gating unit is connected to an output end of the second clock gating unit, and an output end of the fourth clock gating unit is connected to a clock end of the second register.

Further, a plurality of buffer units are arranged between the third clock gating unit and the first clock gating unit to form a clock tree path; and/or

And a plurality of buffer units are arranged between the fourth clock gating unit and the second clock gating unit to form a clock tree path.

Further, the number of buffer units in each clock tree path is the same or different.

Based on the foregoing chip structure, another aspect of the present invention provides a clock control method, including:

when the CPU configures the register of the peripheral IP, the first register outputs a hardware clock request signal, and the first clock gating unit is enabled to output a CPU configuration register clock; and

when the CPU configures the configuration bit of the peripheral IP to start enabling work, the second register outputs a hardware clock request signal, and enables the second clock gating unit to output a peripheral module working clock.

The invention provides a chip for reducing power consumption on a clock tree and a clock control method, which divide clocks required by peripheral IP into 2 clocks which are respectively a clock of a CPU configuration register and a working clock of a peripheral module. The 2 clocks are valid only when needed, the clock control module respectively outputs the clocks to the peripheral IP at the root end, and the 2 clocks are not overturned at other times. The chip structure and the clock control method can effectively reduce the power consumption on the clock tree. Specifically, the peripheral IP working process generally first configures registers of the peripheral IP by the CPU, and then starts peripheral function operation. When the CPU configures the register of the peripheral IP, the clock request of the functional register module is invalid, the corresponding clock tree path does not have clock turnover, and therefore, no power consumption is wasted. In the same principle, after the CPU completes configuration of the peripheral IP register, the peripheral IP function operates for a period of time, the clock request of the configuration register module is invalid, and no clock inversion exists on the corresponding clock tree path, so that no power consumption is wasted. The chip structure and the clock control method can reduce the power consumption on the clock tree by about 40 to 50 percent, so that the power consumption on the whole chip can be reduced by about 10 to 30 percent.

Drawings

To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.

FIG. 1 is a schematic diagram of a prior art clock tree;

FIG. 2 is a schematic diagram of a chip for reducing power consumption on a clock tree according to an embodiment of the invention; and

FIG. 3 is a schematic diagram of a clock tree of a chip for reducing power consumption on the clock tree according to one embodiment of the invention.

Detailed Description

In the following description, the present invention is described with reference to various embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details, or with other alternative and/or additional methods or components. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific numbers and configurations are set forth in order to provide a thorough understanding of embodiments of the present invention. However, the invention is not limited to these specific details. Furthermore, it should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

Reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

In general, for peripheral IP, not all registers need be clocked at the same time, that is, not all buffer cells on the clock tree path need to flip at the same time. Based on the above, in order to reduce unnecessary power consumption waste on a clock tree and enable a chip to realize ultra-low power consumption, the invention provides a chip for reducing power consumption on the clock tree and a clock control method, and solves the problem of power consumption waste at an RTL level. Specifically, in the embodiment of the present invention, the clock required by the peripheral IP is divided into 2 clocks in the RTL design stage, which are respectively: the CPU configures the clocks of the registers, referred to as ip_bus_clk_i, and the peripheral module operating clock, which may be referred to as ip_func_clk_i. The 2 clocks are valid only when needed, and the clock control module can respectively clock out to the peripheral IP at the root end, and the 2 clocks cannot be overturned at other times, so that the power consumption on a clock tree is effectively reduced.

The embodiments of the present invention will be further described with reference to the accompanying drawings.

FIG. 2 is a schematic diagram of a chip for reducing power consumption on a clock tree according to one embodiment of the invention. As shown in fig. 2, a chip for reducing power consumption on a clock tree includes a clock control module and a peripheral IP module, where the clock control module is configured to provide a required clock for the peripheral IP module according to a request of the peripheral IP module.

The clock control module comprises two clock gating clk_gate units, which respectively control a CPU configuration register clock and a peripheral module working clock of the peripheral IP module at the root of the clock, as shown in fig. 2, the first clock gating unit outputs the CPU configuration register clock ip_bus_clk_o through a configuration request signal ip_bus_clk_req_i enable (gate), and the second clock gating unit outputs the peripheral module working clock ip_func_clk_o through a function request signal ip_func_clk_req_i enable (gate). In one embodiment of the present invention, the configuration request signal ip_bus_clk_req_i and the function request signal ip_func_clk_req_i are both hardware clock request signals.

The peripheral IP module eight-outline two sub-modules: configuration module ip_reg, and function module ip_func. The configuration module ip_reg mainly comprises a first register configured by the CPU. The configuration module ip reg typically includes a plurality of first registers therein. The clock signal of the first register is a CPU configuration register clock ip_bus_clk_i, which is output by the first clock gating cell. The configuration module ip_reg is controlled by a clock request signal ip_bus_clk_req_i when the clock control module is enabled, and the ip_bus_clk_i of the first register can be flipped only when the first register output hardware clock request signal ip_bus_clk_req_o is enabled. The functional module ip_func mainly includes a functional register of the peripheral IP, which is also denoted as a second register. The functional module ip_func typically comprises a plurality of second registers. The clock signal of the second register is a peripheral module working clock ip_func_clk_i, which is output by the second clock gating unit. The functional module ip_func is controlled by a clock request signal ip_func_clk_req_i at the clock control module, and the ip_func_clk_i of the second register will flip only when the output hardware clock request signal ip_func_clk_req_o of the second register is valid.

In one embodiment of the present invention, the configuration module outputs a configuration request signal ip_bus_clk_req_o when the CPU writes a signal to the peripheral IP:

assign wr_en＝psel&(～penable)&pwrite；

assign ip_bus_clk_req_o＝wr_en.

in one embodiment of the present invention, the function module outputs a function request signal ip_func_clk_req_o when the CPU configures configuration bits for the peripheral IP to start to operate:

wire ip_enable_wr_en＝(paddr＝＝IP_ENABLE_ADDR)&wr_en；

always@(posedge ip_bus_clk_i or negedge prstn)begin

if(prstn＝＝1’b0)

ip_enable<＝2’h0；

else if(ip_enable_wr_en)

ip_enable<＝pwdata[N]；

end

assign ip_func_clk_req_o＝ip_enable；

FIG. 3 is a schematic diagram of a clock tree of a chip for reducing power consumption on the clock tree according to one embodiment of the invention. As shown in fig. 3, a third clock gating unit is disposed in front of each first register, and a clock end of the third clock gating unit is connected to an output end of the first clock gating unit, and an output end of the third clock gating unit is connected to a clock end of the first register. In one embodiment of the present invention, a plurality of buffer units are disposed between the third clock gating unit and the first clock gating unit to form a clock tree path. It should be appreciated that the number of buffer elements provided in front of a different first register may be the same or different.

Similarly, a fourth clock gating unit is arranged in front of each second register, the clock end of the fourth clock gating unit is connected with the output end of the second clock gating unit, and the output end of the fourth clock gating unit is connected with the clock end of the second register. In one embodiment of the present invention, a plurality of buffer units are disposed between the fourth clock gating unit and the second clock gating unit to form a clock tree path. It should be appreciated that the number of buffer elements previously provided may be the same or different for a different second register.

Clocking based on the chip architecture as described above includes:

when the CPU configures a register of the peripheral IP, the first register outputs a hardware clock request signal, and enables the first clock gating unit to output a CPU configuration register clock; and

During the period that the CPU configures the registers of the peripheral IP, the clock request of the functional register module is invalid, so that no clock flip exists on the corresponding clock tree path, and no power consumption is wasted. In the same principle, after the CPU completes configuration of the peripheral IP register, the peripheral IP function operates for a period of time, the clock request of the configuration register module is invalid, and no clock inversion exists on the corresponding clock tree path, so that no power consumption is wasted. The chip structure and the clock control method can reduce the power consumption on the clock tree by about 40 to 50 percent, so that the power consumption on the whole chip can be reduced by about 10 to 30 percent.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A chip for reducing power consumption in a clock tree, comprising:

a clock control module, comprising:

peripheral IP module, include:

2. The chip of claim 1, wherein the configuration request signal and the function request signal are hardware clock request signals.

3. The chip of claim 1, wherein the configuration module outputs a configuration request signal when the CPU writes a signal to the peripheral IP operation.

4. The chip of claim 1, wherein the function module outputs a function request signal when the CPU configures a configuration bit for the peripheral IP to start an enabling operation.

5. The chip of claim 1, wherein the configuration module includes a third clock gating cell in one-to-one correspondence with the first register, a clock terminal of the third clock gating cell being connected to an output terminal of the first clock gating cell, the output terminal being connected to the clock terminal of the first register.

6. The chip of claim 1, wherein the functional module includes a fourth clock gating unit in one-to-one correspondence with the functional registers of the peripheral IP, a clock terminal of the fourth clock gating unit being connected to an output terminal of the second clock gating unit, and an output terminal being connected to a clock terminal of the second register.

7. The chip of claim 5, wherein a plurality of buffer units are disposed between the third clock gating unit and the first clock gating unit to form a clock tree path.

8. The chip of claim 6, wherein a number of buffer units are disposed between the fourth clock gating unit and the second clock gating unit to form a clock tree path.

9. The chip of claim 7 or 8, wherein the number of buffer units in each clock tree path is the same or different.

10. A method of clock control comprising the steps of: