CN117556761B - Anode short-circuited lateral insulated gate bipolar transistor simulation circuit and simulation method thereof - Google Patents
Anode short-circuited lateral insulated gate bipolar transistor simulation circuit and simulation method thereof Download PDFInfo
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Abstract
The invention relates to an anode short-circuit transverse insulated gate bipolar transistor model which comprises an NMOS tube M1, an NPN triode QN1, a PNP triode QP1, a controlled current source G2 and an NMOS transistor M1, wherein the source electrode of the NMOS tube M1 is connected with the emitter electrode of the SA-LIGBT, the grid electrode of the NMOS tube M1 is connected with the grid electrode of the SA-LIGBT, the emitter electrode of the NPN triode QN1 is connected with the drain electrode of the NMOS tube M1, the collector electrode of the NPN triode QP1 is connected with the collector electrode of the SA-LIGBT and the base electrode of the NPN triode QN1, the collector electrode of the PNP triode QP1 is connected with the emitter electrode of the SA-LIGBT, the base electrode of the NPN triode QP1 is connected with the emitter electrode of the NPN triode QN1, one end of the NPN triode QN1 is connected with the emitter electrode of the NPN triode QN1, and the other end of the NPN triode QN1 is connected with the source electrode of the NMOS tube, and the current generated by the controlled current source G2 is controlled by the NMOS tube M1. The invention can fit the static characteristic and the switching characteristic of the device well.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to an anode short-circuit transverse insulated gate bipolar transistor model and a modeling method of the anode short-circuit transverse insulated gate bipolar transistor model.
Background
The lateral insulated gate bipolar transistor (Lateral Insulated Gate Bipolar Transistor, LIGBT) is widely used in integrated circuit systems (IC, INTEGRATED CIRCUIT) because of its advantages of reduced on-voltage, high input impedance, high current density, and easy integration, where the anode shorted lateral insulated gate bipolar transistor (SA-LIGBT) has high withstand voltage, high power density, and fast switching speed, but the anode shorted lateral insulated gate bipolar transistor has many effects that are difficult to characterize, and these effects are difficult to characterize accurately using conventional IGBT models. Therefore, an anode short-circuit lateral insulated gate bipolar transistor model with high simulation accuracy and a modeling method thereof are needed.
Disclosure of Invention
Based on the above, it is necessary to provide an anode short-circuit lateral insulated gate bipolar transistor model with high simulation accuracy and a modeling method thereof.
An anode short-circuit lateral insulated gate bipolar transistor model suitable for an SA-LIGBT with an NPN triode at the anode, the SA-LIGBT comprising a base region of a first conductivity type, a body region of a second conductivity type in the base region, a doped region of the first conductivity type in the body region, and a doped region of the second conductivity type in the body region, the doped regions of the first and second conductivity types leading out as a collector of the SA-LIGBT; the model comprises an NMOS transistor M1, wherein a source electrode of the NMOS transistor M1 is connected with an emitter electrode of the SA-LIGBT, a grid electrode of the NMOS transistor M1 is connected with the grid electrode of the SA-LIGBT, an emitter electrode of an NPN triode QN1 is connected with a drain electrode of the NMOS transistor M1, a collector electrode of the NPN triode QN1 is connected with a collector electrode of the SA-LIGBT, a PNP triode QP1, an emitter electrode of the PNP triode QP1 is connected with the collector electrode of the SA-LIGBT and a base electrode of the NPN triode QN1, a collector electrode of the PNP triode QP1 is connected with the emitter electrode of the NPN triode QN1, one end of the NPN triode QN1 is connected with the emitter electrode of the NPN triode QN1, the other end of the NPN triode QN1 is connected with the source electrode of the NPN triode QN1, and current generated by the controlled current source G2 is controlled by the NMOS transistor M1.
According to the anode short-circuit transverse insulated gate bipolar transistor model, the anode of the IGBT device is provided with the NPN structure, so that the tail current is small, and the forward voltage retrace phenomenon is avoided. The model is matched with the structure, the controlled current source G2 is arranged to simulate the trailing current, the switching characteristic of the device can be well fitted, and the simulation accuracy is high.
In one embodiment, the anode short-circuit lateral insulated gate bipolar transistor model further includes a controlled current source G1, one end of the controlled current source G1 is connected to the emitter of the PNP triode QP1, the other end is connected to the collector of the PNP triode QP1, and the current generated by the controlled current source G1 is controlled by the current of the PNP triode QP 1.
In one embodiment, the controlled current source G1 includes a first current source, a first capacitor and a first resistor connected in parallel, where the first capacitor generates a capacitor terminal voltage according to the current of the PNP transistor QP1, so as to form a controlled current source related to the capacitor terminal voltage.
In one embodiment, the controlled current source G2 includes a second current source, a second capacitor and a second resistor connected in parallel, where the second capacitor generates a capacitor terminal voltage according to the current of the NMOS transistor M1, so as to form a controlled current source related to the capacitor terminal voltage, and the second resistor is used to adjust the size of the tail current by selecting a suitable resistance value.
In one embodiment, the anode short-circuit lateral insulated gate bipolar transistor model further comprises a drain end resistor Rd1, one end of the drain end resistor Rd is connected with the drain electrode of the NMOS transistor M1, the other end of the drain end resistor Rd is connected with the common end of the controlled current source G2 and the emitter electrode of the NPN transistor QN1, one end of the base resistor Rb1 is connected with the base electrode of the PNP transistor QP1, the other end of the base resistor Rb1 is connected with the common end of the controlled current source G2 and the emitter electrode of the NPN transistor QN1, one end of the external capacitor C1 is connected with the grid electrode of the NMOS transistor M1, the other end of the external capacitor C1 is connected with the collector electrode of the NPN transistor QN1, wherein the NPN transistor QN1 and the PNP transistor QP1 are characterized by using a G-P BJT model, the NMOS transistor M1 is characterized by using a BSIM3 model or a BSIM4 model, and the internal drain end capacitance parameter is closed by using the model of the NMOS transistor M1.
In one embodiment, the drain resistor Rd1 is a voltage controlled resistor.
In one embodiment, the base resistor Rb1 is a voltage-controlled resistor.
In one embodiment, the anode short-circuit lateral insulated gate bipolar transistor model further includes a base resistor Rp, one end of the base resistor Rp is connected to the base of the NPN triode QN1, and the other end is connected to the emitter of the PNP triode QP 1.
It is also desirable to provide a modeling method for an anode shorted lateral insulated gate bipolar transistor model.
A modeling method of an anode short-circuit lateral insulated gate bipolar transistor model comprises the following steps of A, establishing the anode short-circuit lateral insulated gate bipolar transistor model according to claim 1, and setting device parameters of the SA-LIGBT; the method comprises the steps of adjusting capacitance-voltage parameters of an NMOS tube M1 to fit a capacitance-voltage curve, adjusting threshold voltage parameters of the NMOS tube M1 to fit starting voltage of an SA-LIGBT, adjusting device parameters of an NPN triode QN1 to fit a transfer characteristic curve of a minimum Vce of the SA-LIGBT when the SA-LIGBT is started, adjusting linear region parameters of the NMOS tube M1 and device parameters of the PNP triode QP1 to fit a transfer characteristic curve of the SA-LIGBT when the Vce of the SA-LIGBT is in a first voltage value range, adjusting saturated region parameters of the NMOS tube M1 and device parameters of the PNP triode QP1 to fit a transfer characteristic curve of the SA-LIGBT when the Vce of the SA-LIGBT is in a second voltage value range, adjusting voltage values of left end points of the second voltage value range to be larger than the right end points of the first voltage value range, adjusting temperature coefficient of the PNP triode QP1 to fit the temperature coefficient of the SA-LIGBT, and adjusting temperature coefficient of the SA-LIGBT to fit the temperature coefficient.
In one embodiment, the anode short-circuit lateral insulated gate bipolar transistor model further comprises a drain terminal resistor Rd1, one end of the drain terminal resistor Rd is connected with the drain electrode of the NMOS transistor M1, the other end of the drain terminal resistor Rd is connected with the common terminal of the controlled current source G2 and the emitter electrode of the NPN transistor QN1, a base resistor Rb1, one end of the base resistor Rb1 is connected with the base electrode of the NPN transistor QP1, the other end of the base resistor Rb is connected with the gate electrode of the NMOS transistor M1, the other end of the base resistor Rp is connected with the base electrode of the NPN transistor QN1, the other end of the base resistor Rd is connected with the emitter electrode of the NPN transistor QP1, the step B comprises the steps of adjusting the capacitance-voltage parameter of the NMOS transistor M1 and the parameter of the external capacitor C1 to fit a capacitance-voltage curve, the step D comprises the step of adjusting the device parameter of the NPN 1 and the resistance value of the resistor Rp to fit the minimum Vce, and the step of adjusting the device parameter of the NPN transistor QN1 and the resistance value of the base resistor Rd comprises the step of adjusting the base resistor Rd to fit the characteristic curve of the device parameter of the NPN 1 and the base resistor Rd to a step of the step of adjusting the parameter of the base resistor Rd1 to be the base curve.
In one embodiment, the anode short-circuit lateral insulated gate bipolar transistor model further comprises a controlled current source G1, one end of the controlled current source G1 is connected with the emitter of the PNP triode QP1, the other end of the controlled current source G1 is connected with the collector of the PNP triode QP1, the current generated by the controlled current source G1 is controlled by the current of the PNP triode QP1, and the step F1 is followed by a step F2 of adjusting parameters of the controlled current source G1 to fit the self-heating effect of the SA-LIGBT.
In one embodiment, the step F2 is only performed after the step F2 if the fitting accuracy of the step B, the step C, the step D, the step F1, and the step F2 meet the requirement, otherwise, the step G is returned, and after the step G and before the step H, if the fitting accuracy of the temperature characteristic curve does not meet the requirement, the step G is returned.
Drawings
For a better description and illustration of embodiments and/or examples of those inventions disclosed herein, reference may be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be construed as limiting the scope of the disclosed invention, the presently described embodiments and/or examples, and any of the presently understood modes of carrying out the invention.
FIG. 1 is a schematic cross-sectional view of an SA-LIGBT with an NPN triode on the anode according to one embodiment;
FIG. 2 is an equivalent circuit schematic diagram of an anode shorted lateral insulated gate bipolar transistor model in an embodiment, and corresponding device structures for the anode are shown;
FIG. 3 is an equivalent circuit of the controlled current source G1 and the controlled current source G2 in one embodiment;
FIG. 4 is a flow chart of a method of modeling an anode shorted lateral insulated gate bipolar transistor model in one embodiment;
FIG. 5 is a flow chart of a method of modeling an anode shorted lateral insulated gate bipolar transistor model in another embodiment;
FIG. 6 is a graph of current-voltage characteristic fit of an IGBT device using an embodiment of a model at normal temperature (25 degrees Celsius);
FIG. 7 is a graph of current-voltage characteristics of an IGBT device fitted with a model of an embodiment at low temperature (minus 40 degrees Celsius);
FIG. 8 is a graph of current-voltage characteristic fit of an IGBT device using a model of an embodiment at high temperature (180 degrees Celsius);
FIG. 9 is a schematic diagram of a transient performance test circuit and a simulation fit curve of test data and model.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
For the IGBT device with the anode short-circuited full-anode structure, the operation of the IGBT device can be switched between an MOS operation state and an IGBT operation state, and the structure can have a forward voltage folding phenomenon. In order to improve tailing effect and forward voltage retrace phenomenon, an IGBT with an anode (also called a collector) provided with an NPN triode is designed, and the application provides an IGBT device with a semi-positive structure, namely an anode short-circuit transverse insulated gate bipolar transistor model of SA-LIGBT (SA-NPN-LIGBT for short-circuit anode) provided with the NPN triode. Referring to fig. 1, the sa-NPN-LIGBT includes a base region 110, a first body region 132 located in the base region 110, a second body region 134 located in the base region 110, a first conductivity-type doped region 142 located in the first body region 132, a second conductivity-type doped region 148 located in the first body region 132, a first conductivity-type doped region 144 located in the second body region 134, a second conductivity-type doped region 146 located in the second body region 134, a field oxide layer 150 located on the base region 110, and a gate 160. The first conductivity-type doped region 142 and the second conductivity-type doped region 148 are drawn out as collectors of the SA-LIGBT. In the embodiment shown in fig. 1, the first conductivity type is N-type and the second conductivity type is P-type.
The anode short-circuit lateral insulated gate bipolar transistor model comprises:
An NMOS tube M1, wherein a source electrode of the NMOS tube M1 is connected with an emitter electrode of the SA-LIGBT, and a grid electrode of the NMOS tube M1 is connected with a grid electrode of the SA-LIGBT;
An NPN triode QN1, wherein an emitter of the NPN triode QN1 is connected with a drain electrode of the NMOS tube M1, and a collector of the NPN triode QN1 is connected with a collector of the SA-LIGBT;
A PNP triode QP1, wherein the emitter of the PNP triode QP1 is connected with the collector of the SA-LIGBT and the base of the NPN triode QN1, the collector of the PNP triode QP1 is connected with the emitter of the SA-LIGBT, and the base of the PNP triode QP1 is connected with the emitter of the NPN triode QN 1;
one end of the controlled current source G2 is connected with the emitter of the NPN triode QN1, the other end of the controlled current source G2 is connected with the source of the NMOS tube M1, and the current generated by the controlled current source G2 is controlled by the current of the NMOS tube M1.
According to the anode short-circuit transverse insulated gate bipolar transistor model, the anode of the IGBT device is provided with the NPN structure, so that the tail current is small, and the forward voltage retrace phenomenon is avoided. The model is matched with the structure, the controlled current source G2 is arranged to simulate the trailing current, the switching characteristic of the device can be well fitted, and the simulation accuracy is high.
Fig. 2 is an equivalent circuit schematic diagram of an anode shorted lateral insulated gate bipolar transistor model in an embodiment, and the corresponding device structure of the anode is shown in the figure. In the embodiment shown in fig. 2, the anode shorted lateral insulated gate bipolar transistor model further comprises a controlled current source G1. One end of the controlled current source G1 is connected with the emitter of the PNP triode QP1, and the other end is connected with the collector of the PNP triode QP 1. The current generated by the controlled current source G1 is controlled by the current of the PNP transistor QP 1. The controlled current source G1 is used to characterize the self-heating effect of the SA-LIGBT, so the model fits well to the static characteristics of the device.
The equivalent circuit of the controlled current source G1 can be seen in fig. 3, comprising a current source G, a capacitor C and a resistor R connected in parallel with each other. The capacitor C generates a capacitor terminal voltage according to the current of the PNP triode QP1, thereby generating a controlled current source of a capacitor terminal voltage related expression, namely, generating the controlled current source through an RC circuit.
The equivalent circuit of the controlled current source G2 can also be seen in fig. 3. And the influence of the subcircuit when the device is turned on and the size of the tail current of the SA-LIGBT when the device is turned off can be controlled by adjusting the resistance value of the resistor R in the subcircuit.
In one embodiment of the application, NPN transistor QN1 and PNP transistor QP1 are characterized using G-P (Gummel-poon, rheumel-Puen) BJT model, and NMOS transistor M1 is characterized using BSIM3 model or BSIM4 model.
In the embodiment shown in fig. 2, the anode shorted lateral insulated gate bipolar transistor model further includes a drain terminal resistor Rd1, a base resistor Rb1, and an external capacitor C1. One end of the drain end resistor Rd1 is connected with the drain electrode of the NMOS tube M1, and the other end is connected with the common end of the controlled current source G2 and the emitter electrode of the NPN triode QN 1. One end of the base resistor Rb1 is connected with the base of the PNP triode QP1, and the other end is connected with the common end of the controlled current source G2 and the emitter of the NPN triode QN 1. One end of the external capacitor C1 is connected with the grid electrode of the NMOS tube M1, and the other end is connected with the collector electrode of the NPN triode QN 1.
The capacitance characteristics of NPN transistor QN1 and PNP transistor QP1 are characterized by corresponding parameters in the G-P BJT model. Because of the existence of the drain terminal resistor Rd1, the expression for calculating the drain terminal capacitance in the MOS model cannot correctly correspond to the endpoint voltage, so that the capacitance of the drain terminal cannot be reasonably represented, and therefore, the capacitance parameter of the internal drain terminal of the MOS model (the model used by the NMOS tube M1) is closed in the model of the embodiment and is represented by the external capacitance C1. The capacitance characteristic of the source terminal of the NMOS transistor M1 is still characterized by corresponding parameters in the MOS model.
In the embodiment shown in fig. 2, the anode shorted lateral insulated gate bipolar transistor model further comprises a base resistance Rp. One end of the base resistor Rp is connected with the base of the NPN triode QN1, and the other end is connected with the emitter of the PNP triode QP 1.
In the embodiment shown in fig. 2, the drain resistor Rd1 and the base resistor Rb1 are voltage-controlled resistors. The drain resistor Rd1 characterizes the drain drift region resistor of the NMOS tube M1. Base resistor Rb1 characterizes the modulation resistance in the base region of PNP triode QP 1.
In one embodiment of the present application, the voltage-controlled mathematical expression of the drain resistance Rd1 is as follows:
Rd1=Rd_tfac×Rcdw1×(Crd*Vd,d1 Erdd×(1/(1+Prwge1×Vg,e))+1)/(W×
1E6)wrd1
wherein V d,d1 represents the node voltage between d and d1 (i.e., the two ends of the drain resistor Rd 1), rcdw1 represents the resistance value of the drain resistor Rd1 when the voltage is zero, crd is the first voltage coefficient of the drain resistor Rd1, erdd is the power exponent term coefficient of the first voltage of the drain resistor Rd1, prwge1 is the second voltage coefficient of the drain resistor Rd1, W is the channel width of LIGBT, and wrd1 is the correction parameter of W. And:
Rd_tfac=(1+Td1*(TEMP-25)+Td2*(TEMP-25)*(TEMP-25))
wherein TEMP is the system temperature, td1 is the temperature coefficient of the first-order exponential term of the drain terminal resistor Rd1, and Td2 is the temperature coefficient of the second-order exponential term of the drain terminal resistor Rd 1.
In one embodiment of the application, the voltage-controlled mathematical expression of the base resistor Rb1 is as follows:
Rb1=Rb_tfac×Rbw1×(1+Prwge2×Vg,e Erge2+Prwbd2×Vb1,d Erbd)/(W×
1E6)wrd2
Wherein V b1,d represents the node voltage between b1 and d (i.e., the two ends of the base resistor Rb 1), rbw1 represents the resistance value of the base resistor Rb1 when the voltage is zero, prwge is the first voltage coefficient of the base resistor Rb1, V g,e is the absolute value of the voltage between the gate and the emitter of the NMOS transistor M1, erge2 is the power exponent coefficient of the first voltage of the base resistor Rb1, prwbd2 is the second voltage coefficient of the base resistor Rb1, erbd is the power exponent coefficient of the second voltage of the base resistor Rb1, and wrd is the correction parameter of W. And:
Rb_tfac=(1+Tb1*(TEMP-25)+Tb2*(TEMP-25)*(TEMP-25))
wherein Tb1 is the temperature coefficient of the first-order exponential term of the base resistor, and Tb1 is the temperature coefficient of the second-order exponential term of the base resistor.
In one embodiment of the application, the simulation model of the controlled current source G1 (self-heating effect controlled current source subcircuit) is implemented as follows:
rth t1 0rth m=multi
cth t1 0cth m=multi
grth2 0t1 vccs cur='abs(i(q1)*v(c,e))'m=multi
grth1 c e vccs cur='(pwr((1+v(t1,0)/t0),-k)-1)*(-i(q1))'m=multi
in one embodiment of the application, the simulation model of the controlled current source G2 (tail current controlled current source subcircuit) is implemented as follows:
gsen 0a cur='(i(m1))'m=multi
rt1 a 0'pwr(ttail,max(1,((i(m1)*ttail))/(0.01+v(a,0))))'m=multi
ct1 a 0cap1 m=multi
gfsen d e cur='(cap1*(abs(v(a,0)))/tt)-i(m1)'m=multi
The anode short-circuit transverse insulated gate bipolar transistor model can accurately simulate the static characteristic and the switching characteristic of a novel IGBT, the model comprises self-heating effect and can simulate trailing current, and meanwhile, the model consists of a standard model BSIM3/BSIM4 MOS model, a G-P BJT model, a voltage control resistance model, a capacitance model and a controlled current source which are commonly used in industry, can be compatible with a standard circuit simulator HSPICE, SPECTRE, and can keep consistent simulation results on different simulators through format conversion.
The application correspondingly provides a modeling method of the anode short-circuit transverse insulated gate bipolar transistor model, which is based on the anode short-circuit transverse insulated gate bipolar transistor model in any embodiment. Fig. 4 is a flow chart of a modeling method of an anode shorted lateral insulated gate bipolar transistor model in an embodiment, comprising the steps of:
S410, an SA-LIGBT model is built, and device parameters of the SA-LIGBT are set.
The anode short-circuit lateral insulated gate bipolar transistor model of any of the previous embodiments is built, and device process parameters such as channel width, channel length, cell number and the like of the SA-LIGBT are set.
S420, adjusting the capacitance-voltage (CV) parameters of M1 to fit the capacitance-voltage (CV) curve.
The CV parameters of NMOS tube M1 are adjusted. Further, for embodiments in which an external capacitance C1 is provided between the gate of the NMOS transistor M1 and the collector of the NPN transistor QN1 in the model, step S420 includes adjusting the CV parameters of the NMOS transistor M1 and the parameters of the external capacitance C1 to fit the CV curve. In one embodiment of the application, step S420 includes adjusting at least one of the gate-collector overlap capacitance Cgdo, the lightly doped region overlap capacitance Cgdl, and the lightly doped region overlap capacitance coefficient Ckappad to fit the CV curve.
S430, adjusting the threshold voltage parameter of M1 to fit the turn-on voltage of SA-LIGBT.
S440, adjusting the device parameters of QN1 to fit the transfer characteristic curve of the minimum Vce when SA-LIGBT is turned on.
The device parameters of NPN transistor QN1 are adjusted to fit the transfer characteristic of minimum Vce (voltage between collector and emitter) of SA-LIGBT at SA-LIGBT turn on. Further, for embodiments in which the base resistor Rp is provided between the base of NPN transistor QN1 and the emitter of PNP transistor QP1 in the model, step S440 includes adjusting the device parameters of NPN transistor QN1 and the resistance value of base resistor Rp to fit the transfer characteristic of minimum Vce when the device is on. In one embodiment of the present application, the device parameters of NPN transistor QN1 adjusted in step S440 include at least one of transmission saturation current Is, forward current emission coefficient Nf, and forward amplification Bf.
S450, adjusting the linear region parameters of M1 and the device parameters of QP1 to fit the transfer characteristic curve when Vce is small.
The linear region parameters of NMOS transistor M1 and the device parameters of PNP transistor QP1 are adjusted to fit the transfer characteristics of SA-LIGBT with smaller Vce. Further, for embodiments in which the base resistor Rb1 is provided in the model between the base of the PNP transistor QP1 and the common terminal of the controlled current source G2 and the emitter of the NPN transistor QN1, step S450 includes adjusting the linear region parameters of the NMOS transistor M1, the device parameters of the PNP transistor QP1, and the parameters of the base resistor Rb1 to fit the transfer characteristic curve when Vce is small. In one embodiment of the present application, the linear region parameters of the NMOS transistor M1 adjusted in step S450 include at least one of the low electric field mobility U0, the first-order mobility degradation coefficient Ua, the second-order mobility degradation coefficient Ub, the drain parasitic resistance Rdw, and the gate bias coefficient Prwg of the drain parasitic resistance. In one embodiment of the present application, the device parameters of the PNP transistor QP1 adjusted in step S450 include at least one of the transmission saturation current Is, the forward current emission coefficient Nf, the forward amplification Bf, the roll-off angle Ikf at high current, and the index parameter Nkf of the forward amplification roll-off at high current.
S460, the saturation region parameter of M1 and the device parameter of QP1 are adjusted to fit the transfer characteristic and the output characteristic when Vce is large.
The saturation region parameters of NMOS transistor M1 and the device parameters of PNP transistor QP1 are adjusted to fit the transfer characteristic curve when Vce of SA-LIGBT is large, and the output characteristic curve of SA-LIGBT. In one embodiment of the present application, the saturation region parameters of the NMOS transistor M1 adjusted in step S460 include at least one of a substrate charge effect coefficient A0, a gate bias coefficient Ags, and a carrier saturation velocity Vsat. In one embodiment of the present application, the device parameters of the PNP transistor QP1 adjusted in step S460 include at least one of the transmission saturation current Is, the forward current emission coefficient Nf, the forward amplification Bf, the roll-off angle Ikf at high current, and the index parameter Nkf of the forward amplification roll-off at high current.
Further, for the embodiment in which the drain resistor Rd1 is provided in the model between the drain of the NMOS transistor M1 and the common terminal of the controlled current source G2 and the emitter of the NPN triode QN1, the step S460 is followed (before the step S470) by the step S462 of adjusting the drain resistor Rd1 to fit the linear region portion of the output characteristic curve.
Further, for embodiments in which the controlled current source G1 is disposed in the model between the emitter of PNP triode QP1 and the collector of PNP triode QP1, step S464, after step S462 (before step S470), further comprises adjusting parameters of controlled current source G1 to fit the self-heating effect of SA-LIGBT.
S470, adjusting the temperature coefficient to fit the temperature characteristic curve of the SA-LIGBT.
And adjusting the temperature coefficients corresponding to the parameters involved in the steps to fit the temperature characteristic curve of the SA-LIGBT.
S480, parameters of the controlled current source G2 are adjusted to fit the switching characteristics of the SA-LIGBT.
In one embodiment of the present application, after step S464, a step of determining whether the fitting accuracy of steps S420, S430, S440, S450, S460, S462, S464 meets the requirement (i.e. whether the model simulation data is better fitted with the actual test data) is further included, if the curve fitted in any of steps S420 to S464 does not meet the accuracy requirement, the parameters related to the step are adjusted again, and step S470 is not executed until the curves of the steps meet the requirement. Specifically, after step S464, step S420 may be returned to determine whether the fitted curve of each step meets the precision requirement, if the fitted curve of any step does not meet the precision requirement, the parameters related to the step are adjusted again to meet the precision requirement, then the next step of fitted curve is continuously verified to verify whether the fitted curve of step S464 meets the precision requirement, and after the fitted curve of step S464 is verified, step S420 is returned again until all the fitted curves meet the precision requirement.
In one embodiment of the present application, after step S470 and before step S480, a step of determining whether the fitting accuracy of the temperature characteristic curve meets the requirement is further included, and if the fitting accuracy does not meet the requirement, returning to step S470.
Fig. 5 is a flow chart of a method of modeling an anode shorted lateral insulated gate bipolar transistor model in another embodiment. An example of an IGBT model built according to the modeling method described above is provided below:
.subckt ligbt c g e w=380E-6 l=0.5E-6multi=2 dtemp=0 as=1e-12
+ad=1e-12ps=1e-6pd=1e-6
.param
+cgdo_o=1.291507E-10 cgdl_o=4.490555E-9 ckappad_o=3.941095
+......
.param
+rd_tfac='1+tcrd1*(temper-25)+tcrd2*(temper-25)*(temper-25)'
+......
cgd_macro g c q='(cgdo_o*v(g,c)+cgdl_o*(v(g,c)-vgc_overlap-ckappad_o/2*(-1+sqrt(1-4*
vgc_overlap/ckappad_o))))*w*multi'
q2 c b2 d qvn1 m=multi dtemp=dtemp
r2 c b2 r='rpw0/*rp_tfac'm=multi dtemp=dtemp
q1 e b1 c pnp1 m=multi dtemp=dtemp
rd1 d d1 r='rcdw1*(crd*abs(v(d,d1))*(1/(1+prwge1*abs(v(g,e))))+1)/pwr(w*1E6,wrd)*rd_tfac'
m=multi dtemp=dtemp
m1 d1 g e e msub w=w l=l as=as ad=ad ps=ps pd=pd m=multi dtemp=dtemp
rb1 b1 d r='rbw1*(1+prwbd2*abs(v(b1,d))+prwge2*abs(v(g,e))+prwge3*abs(v(g,e)*
v(g,e)))*rb_tfac'm=multi dtemp=dtemp
rth t1 0rth m=multi dtemp=dtemp
cth t1 0cth m=multi dtemp=dtemp
grth2 0t1 vccs cur='abs(i(q1)*v(c,e))'m=multi dtemp=dtemp
grth1 c e vccs cur='(pwr((1+v(t1,0)/t0),-k)-1)*(-i(q1))'m=multi dtemp=dtemp
gsen 0a cur='(i(m1))'m=multi dtemp=dtemp
rt1 a 0'pwr(ttail,max(1,((i(m1)*ttail))/(0.01+v(a,0))))'m=multi dtemp=dtemp
ct1 a 0cap1 m=multi dtemp=dtemp
gfsen d e cur='(cap1*(abs(v(a,0)))/tt)-i(m1)'m=multi dtemp=dtemp
.model msub nmos
*****Flag Parameter***
+level=54 version=4.5 binunit=2
*****Capacitance Parameter***
+xpart=1 cgso=1.68E-10 cgdo=0
+......
.model pnp1 pnp
*****Flag Parameter***
+level=1 tlev=0 tlevc=1
*****Capacitance Parameter***
+cje=2.076341E-14 vje=0.843227 mje=0.493539
+cjc=3.428023E-14 vjc=0.558045 mjc=0.339586
+......
.model qvn1 npn
*****Flag Parameter***
+level=1tlev=0tlevc=1
*****DC Model Parameter***
+is=7.54897E-16 bf=1.577878 nf=0.984025
+vaf=243 ikf=6.3E-3 nkf=0.6
+......
.ends ligbt
Fig. 6 is a current-voltage characteristic fitting curve of the IGBT device using the above model at normal temperature (25 degrees celsius), where Ids tends to be 0 when Vgs is 3V and 0V, respectively. Fig. 7 is a graph showing the current-voltage characteristic fitting of the above model to the IGBT device under low temperature (minus 40 degrees celsius) and fig. 8 is a graph showing the high temperature (180 degrees celsius) conditions. In fig. 6 to 8, solid lines are model simulation data, dots are actual test data for the device, d corresponds to the collector C (collector) of the IGBT, and S corresponds to the emitter E (emitter) of the IGBT. Fig. 9 is a transient characteristic test circuit and a simulation fit curve of test data and a model (actual measurement and fitting conditions of a tail current under transient characteristics of a device), in fig. 9, a resistor is denoted by R1, a power supply is denoted by DC, and a ground wire is denoted by GND1.
It should be understood that, although the steps in the flowcharts of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the flowcharts of this application may include a plurality of steps or stages that are not necessarily performed at the same time but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternately with at least a portion of the steps or stages in other steps or others.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
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| CN202210927589.4A CN117556761B (en) | 2022-08-03 | 2022-08-03 | Anode short-circuited lateral insulated gate bipolar transistor simulation circuit and simulation method thereof |
| PCT/CN2023/109757 WO2024027574A1 (en) | 2022-08-03 | 2023-07-28 | Shorted anode lateral insulated gate bipolar transistor model and modeling method therefor |
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| CN202210927589.4A CN117556761B (en) | 2022-08-03 | 2022-08-03 | Anode short-circuited lateral insulated gate bipolar transistor simulation circuit and simulation method thereof |
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|---|---|---|---|---|
| CN110504307A (en) * | 2019-08-28 | 2019-11-26 | 重庆邮电大学 | A SA-LIGBT device with gated collector |
| CN110571264A (en) * | 2019-09-17 | 2019-12-13 | 重庆邮电大学 | A SA-LIGBT device with multi-channel current plug |
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| CN103633087B (en) * | 2013-12-19 | 2016-08-17 | 电子科技大学 | A kind of strong anti-breech lock controlled LIGBT device with ESD defencive function |
| CN111769159B (en) * | 2020-07-09 | 2024-05-28 | 重庆邮电大学 | A SA-LIGBT device with polysilicon electron channel |
| CN113690310A (en) * | 2021-07-14 | 2021-11-23 | 广东美的白色家电技术创新中心有限公司 | LIGBT, preparation method, intelligent power module, drive circuit and electrical appliance |
| CN113935268B (en) * | 2021-11-22 | 2024-06-11 | 电子科技大学 | Anode short-circuit transverse insulated gate bipolar transistor equivalent circuit model and simulation method |
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|---|---|---|---|---|
| CN110504307A (en) * | 2019-08-28 | 2019-11-26 | 重庆邮电大学 | A SA-LIGBT device with gated collector |
| CN110571264A (en) * | 2019-09-17 | 2019-12-13 | 重庆邮电大学 | A SA-LIGBT device with multi-channel current plug |
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