CN117501604A - A charger for wide input/output voltage regulation - Google Patents

Abstract

A charger for wide input/output voltage regulation. The charger includes: a low-frequency half-bridge switching device circuit, a high-frequency half-bridge switching device circuit, and a controller for receiving an output DC voltage reference. The controller is configured to determine a DC bus voltage reference and determine a switching frequency based on the DC bus voltage reference. The controller is used to determine whether the switching frequency is higher than a threshold frequency, and if so, perform pulse power transmission control; otherwise, perform frequency conversion modulation control. The controller is configured to receive an output charging current and determine whether the output charging current is below a current threshold, and if so, disable the low-frequency half-bridge switching device circuit. The charger can also be called a high-efficiency single-stage resonant AC/DC converter, which provides wide input AC voltage regulation and wide output DC voltage regulation.

Description

A charger for wide input/output voltage regulation

Technical field

The present invention relates to the field of alternating current (AC) to direct current (DC) converters. Specifically, the present invention relates to a charger for wide input/output voltage regulation.

Background technique

As demand increases for more powerful smartphones, tablets, and laptops with larger screens and fifth generation (5G) features, next-generation alternating current (AC) to direct current (DC) ) A huge market has been established for adapters for quickly charging larger lithium (Li)-ion batteries. Fast charging means higher power density and smaller size. Traditional solutions use two-stage AC/DC converters, but these converters have their own limitations. In traditional two-stage AC/DC converters, high efficiency is achieved due to an increase in the number of semiconductors, improvements in magnetic component design, and reduction in switching frequency. However, the above factors lead to a decrease in power density because the input energy is processed in two steps. This further increases the cost of power conversion compared to low power level applications.

Currently, various attempts are made to design a low-cost, small-sized, and high-efficiency AC/DC converter. For example, traditional single-stage AC/DC converters use a diode bridge in the input stage and combine asymmetric duty cycle (or asymmetric pulse width modulation (APWM)) with DC bus voltage regulation and A control technology that combines pulse frequency modulation (PFM) with output voltage regulation. This control technique solves high DC bus voltage stress, but the duty cycle decreases as the input voltage amplitude increases, resulting in more losses. This means that to achieve higher duty cycles, the DC bus voltage must increase, and as the input voltage increases, an increase in DC bus voltage results in reduced efficiency. Therefore, conventional single-stage AC/DC converters along with APWM control technology are only suitable for low input grid voltages because of the high duty cycle at the operating point. In addition, conventional single-stage AC/DC converters exhibit gain-flat characteristics, making it difficult to provide wide output voltage regulation. Furthermore, the traditional single-stage AC/DC converter includes a diode bridge at the input stage. The diode bridge itself causes additional conduction losses and reduces efficiency. Thereafter, another conventional single-stage AC/DC converter was proposed using the addition of an inductor-inductor-capacitor (LLC) resonant converter to create a third harmonic injection resonant tank. The third harmonic injection resonant tank partially solves the technical challenge of wide output voltage regulation by making the gain flat characteristic curve of a conventional single-stage AC/DC converter slightly sharper. However, other traditional single-stage AC/DC converters also have some limitations, such as using more magnetic components which results in more losses, bulky size and high cost. Therefore, there are technical problems with inefficient AC/DC converters. Inefficient AC/DC converters have low input and output voltage regulation, high cost, and high conduction losses, resulting in low power density and peak efficiency.

Therefore, based on the above discussion, there is a need to overcome the above disadvantages associated with conventional single-stage AC/DC converters.

Contents of the invention

The present invention provides a charger for wide input/output voltage regulation. The present invention provides a solution to the existing problems of low-efficiency AC/DC converters. Inefficient AC/DC converters have low input and output voltage regulation, high cost, and high conduction losses, thus exhibiting low power density and peak efficiency. It is an object of the present invention to provide a solution that at least partially overcomes the problems encountered in the prior art and to provide an improved charger for wide input/output voltage regulation.

The object of the invention is achieved by the solutions provided in the appended independent claims. Advantageous implementations of the invention are further defined in the dependent claims.

In one aspect, the invention provides a charger for wide input/output voltage regulation. The charger includes: a low-frequency half-bridge switching device circuit, a high-frequency half-bridge switching device circuit, and a controller for receiving an output DC voltage reference. The controller is further configured to determine a DC bus voltage reference and determine a switching frequency based on the DC bus voltage reference. The controller is also used to determine whether the switching frequency is higher than a threshold frequency. If so, perform pulse power transfer (PPT) control. If not, perform variable frequency modulation (VFM) control. The controller is further configured to receive the output charging current and determine whether the output charging current is below a current threshold, and if so, disable the low-frequency half-bridge switching device circuit.

The disclosed charger may also be referred to as a high-efficiency single-stage resonant AC/DC converter that provides a wide range of input AC voltage regulation (e.g., 85-265Vac) and a wide range of output DC voltage regulation (e.g., 5-20Vdc) . The disclosed charger also regulates power as low as 1 Watt (W) to 75W in PPT mode and up to 150W in average current mode (ACM) or VFM mode without using The third harmonic injection resonant tank used in conventional AC/DC converters requires additional components. Since the low-frequency half-bridge switching device circuit is used to replace the traditional input diode bridge, the conduction loss is reduced, so the disclosed charger implements a bridgeless solution. In addition, the charger offers low cost, small size, high power density and peak efficiency. Therefore, the charger can be used as a smartphone or laptop charger, or even for general household appliances such as smart television (TV) and vacuum cleaners.

In one implementation, the controller is further configured to determine the PPT mode duty cycle if the switching frequency is higher than the threshold frequency. The controller is also used to determine whether the PPT mode duty cycle is equal to 1. If so, perform variable frequency modulation (VFM) control, otherwise perform pulse power transfer (PPT) control.

By executing the controller in VFM control mode or PPT control mode according to the switching frequency, threshold frequency and duty cycle, the charger achieves controlled PFC duty cycle, high power density, high peak efficiency and uniform flow through the switching device circuit. The root mean square (RMS) current is small.

In another implementation, the controller is further configured to: if the output charging current is lower than the current threshold, set the gate of the low-frequency half-bridge switching device circuit to a low level.

This facilitates setting the gate of the low-frequency half-bridge switching device circuit low under extreme light load conditions (e.g., power <10W) in order to block reverse power flow, which further prevents overproduction under extreme light load conditions power.

In another implementation, the controller is further configured to set the high-frequency duty cycle to a constant value.

Fixing the duty cycle to a constant value ensures that the precise energy required is produced under extreme light load conditions while keeping the DC bus voltage low.

In another implementation manner, the controller is also used to: set the switch of the low-frequency half-bridge switching device circuit according to the frequency of the power grid.

In another implementation, the controller is further configured to: set the switch of the low-frequency half-bridge switching device circuit to be turned off during the zero-crossing region, and to set the switch to turn off at each half of the grid frequency after the zero-crossing region. Complementary conduction during the cycle.

This is advantageous because it allows the charger to operate in discontinuous conduction mode (DCM) and continuous conduction mode (DCM) respectively and ensures zero voltage switching at all operating points ( zero-voltage switching (ZVS).

In another implementation, the controller is further configured to disable the VFM control loop and set the switching frequency to the highest allowed frequency when performing pulse power transfer (PPT) control.

In another implementation, the controller is also used to adjust the switching frequency step by step as the output load and output voltage of the charger change.

This facilitates changing the switching frequency in steps as the charger output load and output voltage change to reduce switching losses and obtain sufficient gain.

In another implementation, the controller is further configured to linearly adjust the DC bus voltage according to the output power and voltage.

The DC bus voltage is linearly adjusted according to the output power and voltage, reducing switching losses.

In another implementation, the charger further includes an AND gate. The AND gate is used to combine the high-frequency PWM signal and the pulse PWM signal during the PPT mode to provide the combined PWM signal to the high-frequency half-bridge switching device circuit.

The AND gate is used to generate a high-frequency PWM signal (i.e., combined PWM signal), which is used to regulate the switching of the high-frequency half-bridge switching device circuit during PPT mode.

In another implementation, the charger further includes a bridgeless rectifier stage. The bridgeless rectifier stage includes a boost inductor and a DC bus capacitor coupled to the switching resonant stage.

The DC bus capacitor acts as a power decoupler, so the charger requires no additional components to remove low-frequency ripple (e.g., 100Hz).

In another implementation, the switching resonant stage includes: a resonant inductor, a resonant capacitor, and a high-frequency transformer connected to the output synchronous rectification switching device.

In another implementation, the controller further includes: a modulation controller for integrating a power factor correction (power factor correction, PFC) stage + LLC stage. Output stage regulation uses a variable frequency modulation (VFM) controller in normal operation and a pulse power transfer (PPT) controller in PPT operating mode to simultaneously achieve wide AC input voltage and wide DC Output voltage regulation.

The modulation controller enables the charger to achieve wide input AC voltage regulation (e.g., 85-265Vac) and wide output DC voltage regulation (e.g., 5-20Vdc). Additionally, the modulation controller enables the charger to have increased power factor (eg, 95%) and reduced total harmonic distortion (eg, less than 10%).

In another implementation, the modulation controller includes a PFC stage. The PFC stage has an outer loop for DC bus voltage control, an inner current loop, and a zero-crossing compensation algorithm for generating the converter duty cycle.

The zero-crossing compensation algorithm maintains the converter gain in the zero-crossing region, which is incorporated into the ACM control that regulates the DC bus voltage and produces the output PFC duty cycle (called HF duty cycle in this case) .

It should be understood that all the aforementioned implementations can be combined together.

It should be noted that all devices, elements, circuits, units and arrangements described in this application may be implemented in software or hardware elements or any type of combination thereof. All steps performed by various entities described in this application and functions described to be performed by various entities are intended to mean that the corresponding entities are used to perform the corresponding steps and functions. Although in the description of the following specific embodiments, specific functions or steps to be performed by external entities are not reflected in the description of the specific detailed elements of the entities that perform specific steps or functions, it should be clear to those skilled in the art that these methods and functions can be performed by Implemented by corresponding hardware or software elements or any combination thereof. It will be understood that the features of the invention are susceptible to being combined in various combinations without departing from the scope of the invention as defined by the appended claims.

Other aspects, advantages, features and objects of the invention will become apparent from the accompanying drawings and the detailed description of illustrative implementations, taken in conjunction with the following appended claims.

Description of the drawings

The above summary and the following detailed description of illustrative embodiments may be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the invention, exemplary structures of the invention are shown in the drawings. However, the invention is not limited to the specific methods and tools disclosed herein. Furthermore, those skilled in the art will appreciate that the drawings are not drawn to scale. Where possible, identical components are designated by the same numbers.

Embodiments of the invention will now be described, by way of example only, with reference to the following figures, in which:

Figure 1 is a circuit diagram of a charger according to an embodiment of the present invention;

Figure 2 is a block diagram of various exemplary components of a controller according to an embodiment of the invention;

Figure 3 is a graphical representation of a pulse power transfer (PPT) control technology of a controller according to an embodiment of the present invention;

Figure 4 shows a control technique used by a controller according to an embodiment of the present invention;

Figure 5 is a flowchart of control techniques performed by a controller during normal operation and PPT operating modes according to an embodiment of the present invention;

Figure 6A shows measured efficiency curves obtained over an output voltage range and a low input AC voltage according to an embodiment of the invention;

Figure 6B shows measured efficiency curves obtained over an output voltage range and a high input AC voltage according to an embodiment of the invention;

Figure 7 shows the performance of a converter in terms of power factor (PF) load resistance according to an embodiment of the present invention;

Figure 8 shows changes in the measured total harmonic distortion value of the converter as the number of harmonics increases at high input AC voltage according to an embodiment of the present invention;

Figure 9 is a circuit diagram of a charger according to another embodiment of the present invention.

In the drawings, underlined numbers are used to represent the item in which the underlined number exists or an item adjacent to the underlined number. The ununderlined number relates to the item identified by the line that associates the ununderlined number with the item. When a number is ununderlined and has an associated arrow, the ununderlined number is used to identify the general item to which the arrow points.

Detailed ways

The following detailed description illustrates embodiments of the invention and the manner in which these embodiments may be implemented. Although some modes for carrying out the invention have been disclosed, those skilled in the art will recognize that other embodiments for implementing or practicing the invention may exist.

Figure 1 is a circuit diagram of a charger according to an embodiment of the present invention. Referring to Figure 1, a circuit diagram of charger 100 is shown. The charger 100 includes: a low-frequency half-bridge switching device circuit 102, a high-frequency half-bridge switching device circuit 104, a controller 106, a bridgeless rectifier stage 108 and a switching resonant stage 110. The bridgeless rectifier stage 108 includes a boost inductor 112 and a DC bus capacitor 114 . Switching resonant stage 110 includes: resonant inductor 116, resonant capacitor 118 and high frequency transformer 120. The high frequency transformer 120 is connected to the output synchronous rectification switching device circuit 122 before being connected to the output capacitor 124 for powering the output load 126 . An input electromagnetic interference (EMI) filter 128 is also shown. Charger 100, controller 106, switching resonant stage 110, boost inductor 112, DC bus capacitor 114, resonant inductor 116, resonant capacitor 118, high frequency transformer 120, output synchronous rectification switching device circuit 122 and output capacitor 124 Each of is represented by a dashed box and is for illustrative purposes only and does not form part of the circuit.

Charger 100 is used for wide input/output voltage regulation. The charger 100 may also be called a single-stage resonant alternating current (AC) to direct current (DC) converter. The charger 100 is designed to use a new control technology. The new control technology uses a mixture of average current mode (ACM), variable frequency modulation (VFM) and pulse power transfer (PPT) control modulation. This new control technology provides the benefits of wide input and wide output voltage regulation, with high efficiency due to the use of zero voltage switching (ZVS), which enables an increase in power density and switching frequency, thereby reducing the size of the charger 100 smaller. This new control technology is described in detail in the following manner.

The charger 100 includes: a low-frequency half-bridge switching device circuit 102, a high-frequency half-bridge switching device circuit 104, and a controller 106. The low-frequency half-bridge switching device circuit 102 includes two low-frequency metal oxide semiconductor field effect transistor (MOSFET) switches (also represented as S _a and S _b ), which are used for low frequency (eg, , 50Hz) switching element. Each low-frequency MOSFET switch (i.e., _Sa and _Sb ) has a gate terminal (also denoted as _gsa and _gsb ), a drain terminal, and a source terminal. Similarly, the high-frequency half-bridge switching device circuit 104 includes two high-frequency MOSFET switches (also represented as S ₁ and S ₂ ) that function as high-frequency (eg, above 200 kHz) switching elements. Each high-frequency MOSFET switch (i.e., S ₁ and S ₂ ) has a gate terminal (also denoted as g _s1 and g _s2 ), a drain terminal, and a source terminal. Additionally, each high-frequency MOSFET switch (i.e., S ₁ and S ₂ ) may also be referred to as a gallium-nitride (GaN) transistor. The controller 106 is used to control the functions of the low-frequency half-bridge switching device circuit 102 (ie, S _a and S _b ) and the high-frequency half-bridge switching device circuit 104 (ie, S ₁ and S ₂ ). The controller 106 is also used to control ACM, VFM and PPT modulation. Alternatively, the controller 106 is configured to perform a new control technique as detailed in FIG. 2 .

Controller 106 is configured to receive an output DC voltage reference and determine a DC bus voltage reference. To control various operating modes of charger 100 (i.e., single-stage resonant AC/DC converter), controller 106 is configured to: receive an output DC voltage reference (also denoted as V _oref ), and generate The voltage reference (i.e., V _oref ) determines the DC bus voltage reference (also expressed as V _busref ).

The controller 106 is also used to: determine the switching frequency according to the DC bus voltage reference, and determine whether the switching frequency is higher than the threshold frequency. If so, perform pulse power transfer (PPT) control; if not, perform frequency conversion modulation ( variable frequency modulation (VFM) control. The controller 106 is used to determine the switching frequency (also denoted f _sw ) based on the DC bus voltage reference (ie, V _busref ). The controller 106 is also used to determine whether the switching frequency (ie, f _sw ) is above a threshold frequency (also denoted f _th ). In one case, if the switching frequency (ie, f _sw ) is higher than the threshold frequency (ie, f _th ), the controller 106 is configured to perform PPT control as described in detail in FIGS. 2 and 4 . Otherwise, the controller 106 is configured to perform VFM control as described in detail in FIGS. 2 and 4 .

The controller 106 is also configured to receive the output charging current and determine whether the output charging current is below the current threshold, and if so, disable the low-frequency half-bridge switching device circuit 102 . In addition, the controller 106 is configured to: receive the output charging current (which may also be expressed as i _o ), and determine whether the output charging current (i.e., i _o ) is lower than the current threshold. In one case, if the output charging current (ie, i _o ) is below the current threshold, the controller 106 is configured to disable the low frequency half-bridge switching device circuit 102 (ie, Sa _and S _b ).

According to an embodiment, the charger 100 also includes a bridgeless rectifier stage 108 . The bridgeless rectifier stage 108 includes a boost inductor 112 and a DC bus capacitor 114 coupled to the switched resonant stage 110 . In addition to the low-frequency half-bridge switching device circuit 102 (i.e., S _a and S _b ), the high-frequency half-bridge switching device circuit 104 (i.e., S ₁ and S ₂ ), and the controller 106 , the charger 100 also includes a bridgeless rectifier Level 108. The bridgeless rectifier stage 108 includes a boost inductor 112 (also denoted L _b ) and a DC bus capacitor 114 (also denoted C _b ). DC bus capacitor 114 (ie, C _b ) is coupled to switching resonant stage 110 and serves as a power decoupler.

According to an embodiment, the switching resonant stage 110 includes a resonant inductor 116 , a resonant capacitor 118 and a high frequency transformer 120 connected to the output synchronous rectification switching device circuit 122 . The switching resonant stage 110 includes a resonant inductor 116 (also denoted as L _r ), a resonant capacitor 118 (also denoted as C _r ), a high-frequency transformer 120 (also denoted as T ₁₂ ), and an output synchronous rectification. , SR) switching device circuit 122. Output synchronous rectification switching device circuit 122 includes two output synchronous rectification MOSFET switches (also denoted SR ₁ and SR ₂ ).

In one implementation, charger 100 (ie, a single-stage resonant AC/DC converter) is configured to receive input power from an AC source (also represented as Vac) through input EMI filter 128 . The input EMI filter 128 may be implemented as a single-stage or two-stage common mode (CM) filter or a differential filter (DF). Input EMI filter 128 includes two output terminals, such as a first output terminal (eg, a positive terminal) and a second output terminal. The first output terminal of the input EMI filter 128 is connected at point A to a bridgeless rectifier stage 108 (also referred to as an input stage) including a boost inductor 112 (i.e., L _b ), which is connected to Midpoint B of the high-frequency half-bridge switching device circuit 104 (ie, S ₁ and S ₂ ). Midpoint B is connected to a switched resonant stage 110 including a resonant inductor 116 (ie, L _r ) and a resonant capacitor 118 (ie, C _r ). One terminal of the resonant inductor 116 (ie, L _r ) is connected to the midpoint B, and the other terminal is connected to one terminal of the resonant capacitor 118 (ie, C _r ). The other terminal of resonant capacitor 118 (i.e., C _r ) is connected to the primary winding of high frequency transformer 120 (i.e., T ₁₂ ), and the secondary winding is connected to the output SR switching device circuit 122 (i.e., SR ₁ and SR ₂ ), The output SR switching device circuit 122 is further connected to an output capacitor 124 (also denoted C ₀ ). Output capacitor 124 (ie, C ₀ ) is used to power output load 126 (also denoted as R ₀ ). Additionally, a second output terminal (eg, the negative terminal) of the input EMI filter 128 is connected to the midpoint C of the low-frequency half-bridge switching device circuit 102 (ie, _Sa and _Sb ).

Figure 2 is a block diagram of various exemplary components of a controller in accordance with an embodiment of the present invention. Figure 2 is described in conjunction with elements from Figure 1. Referring to Figure 2, a block diagram of controller 106 (Figure 1) is shown. Controller 106 includes: modulation controller 202 for power factor correction (PFC) stage 204 and switching resonant stage 110, variable frequency modulation (VFM) controller 206, and pulse power transfer. PPT) controller 208. PFC stage 204 is represented by a dashed box and is for illustrative purposes only and does not form part of the circuit.

Initially, the controller 106 is configured to receive an output DC voltage reference (ie, V _oref ). The controller 106 is configured to determine the DC bus voltage reference (ie, V _busref ) based on the received output DC voltage reference (ie, V _oref ).

According to an embodiment, the controller 106 further includes a modulation controller 202 for integrating the PFC stage 204 + LLC stage. The output stage is regulated using a variable frequency modulation (VFM) controller 206 in normal operation and a pulse power transfer (PPT) controller 208 in PPT operating mode to simultaneously achieve a wide AC input voltage ( 85-265Vrms) and wide DC output voltage (5-20Vdc) regulation. Alternatively, the controller 106 includes a modulation controller 202 (which may also be referred to as PWM modulation) for the PFC stage 204 and the switching resonant stage 110 (which may also be referred to as an inductor-inductor-capacitor (LLC)). controller), VFM controller 206, and PPT controller 208. Modulation controller 202 (which may also be referred to as an average current mode (ACM) controller) regulates the DC bus voltage (which may also be referred to as V _b ) input Required PFC stage 204. VFM controller 206 is used to: regulate the output voltage while generating a switching frequency (i.e., f _sw ) from 75 Watt (W) to 150 W during normal operating mode. ACM and VFM Control Technology Provides voltage regulation of 11-20V (power >20W) for low AC input voltages (120Vac) and only 20V (power >60W) for high AC input voltages (230Vac), regardless of the switching frequency (i.e., f _sw ) The set threshold frequency (ie, f _th ) is not exceeded. The PPT controller 208 provides wide output voltage regulation from 5Vdc to 20Vdc and extreme light load control from 1W to 75W.

According to an embodiment, the modulation controller 202 includes a PFC stage. The PFC stage has an outer loop for DC bus voltage control, an inner current loop, and a zero-crossing compensation algorithm for generating the converter duty cycle (HF duty cycle). Modulation controller 202 includes a PFC stage 204, an outer loop for DC bus voltage control, an inner current loop, and a converter (i.e., single stage resonant AC/DC converter) duty cycle (or high frequency duty cycle) Zero-crossing compensation algorithm. Depending on the converter gain, the converter (i.e., single-stage resonant AC/DC converter) duty cycle saturates between 0.2 and 0.8. The zero-crossing compensation algorithm is used to maintain the converter (i.e., single-stage resonant AC/DC converter) gain near the zero-crossing region by saturating the duty cycle to a limit with 0.2 ≤ duty cycle ≤ 0.8, clamp and turning off the low frequency half-bridge switching device circuit 102 (ie, _Sa and _Sb ) to stop reverse power flow and change the duty cycle of the clamping region to prevent current spikes.

According to an embodiment, the controller 106 is further configured to: determine the PPT mode duty cycle (d1) if the switching frequency (f _sw ) is higher than the threshold frequency (f _th ), and determine whether the PPT mode duty cycle (d1 ) is equal to 1. If yes, perform variable frequency modulation (VFM) control, otherwise perform pulse power transfer (PPT) control. The controller 106 is also configured to determine whether the switching frequency (ie, f _sw ) generated by the VFM controller 206 is above a threshold frequency (ie, f _th ), such as 500 kHz. In one case, if the switching frequency (i.e., f _sw ) is higher than the threshold frequency (i.e., f _th ), the controller 106 is also used to: determine the converter PPT mode duty cycle (d1), and check the converter PPT mode Whether the duty cycle (d1) is equal to or greater than 1. If the converter PPT mode duty cycle (d1) is equal to or greater than 1, the controller 106 is configured to perform VFM control, otherwise perform PPT control. In another case, if the generated switching frequency (ie, f _sw ) is less than the threshold frequency (ie, f _th ), the controller 106 is configured to perform VFM control. Alternatively, if the generated switching frequency (i.e., f _sw ) is less than the threshold frequency (i.e., f _th ), the VFM control operation is continued, which may be referred to as a converter (i.e., a single-stage resonant AC/DC converter) Normal mode operation. In this case, the ACM control maintains the DC bus voltage within the specified limit of 300-430 Vdc by using the current inner loop of the PFC stage 204 which derives the PFC duty cycle (ie, high frequency (HF) duty cycle) within the value. The PFC duty cycle (i.e., HF duty cycle) saturates between 0.2 and 0.8 before being substituted into the zero-crossing compensation algorithm. The zero-crossing compensation algorithm keeps the converter (i.e., single-stage resonant AC/DC converter) gain along the zero-crossing region and allows the converter to operate in discontinuous conduction mode (DCM) in the zero-crossing region. The PFC duty cycle after the zero-crossing compensation algorithm is compared with the switching frequency (i.e., f _sw ) or the carrier waveform to generate the HF pulse width modulation (pulse) used to control the HF switches (i.e., S ₁ and S ₂ ) width modulation (PWM) signal, and the pulse PWM signal of the PPT mode is set to a high level when connected to the AND gate 210, as described in detail in FIG. 4 .

According to an embodiment, the controller 106 is further configured to disable the VFM control loop and set the switching frequency (f _sw ) to the highest allowed frequency when performing pulse power transfer (PPT) control. In this case, when the switching frequency (i.e., f _sw ) is higher than the threshold frequency (f _th ), the PPT controller 208 disables the VFM controller 206 and fixes the switching frequency (i.e., f _sw ) to the highest allowed frequency (e.g., , 500kHz) and start running.

According to an embodiment, the charger 100 further includes an AND gate 210 . The AND gate 210 is used to combine the high-frequency PWM signal and the pulse PWM signal during the PPT control mode to provide the combined PWM signal to the high-frequency half-bridge switching device circuit 104 . During the PPT control mode, the PPT controller 208 is enabled and the pulse frequency (ie, f _pulse ) is set to approximately 30 kHz. The pulse frequency (ie, f _pulse ) is compared with the PPT mode duty cycle (ie, d1 ) of the PPT controller 208 to generate a pulse PWM signal (eg, 30 kHz), which is then ANDed using AND gate 210 High frequency PWM signals are multiplied. The resulting PWM signal (ie, the high frequency PWM signal multiplied by the pulsed PWM signal) is used to control the high frequency half-bridge switching device circuit 104 (ie, S ₁ and S ₂ ) as described in detail in FIG. 3 .

According to an embodiment, the controller 106 is also configured to adjust the switching frequency step by step as the output load 126 and the output voltage of the charger 100 change. The switching frequency (ie, f _sw ) changes to a lower value as the output load 126 of FIG. 1 (ie, R ₀ ) and the output voltage (ie, V ₀ ) as shown in Table 1 increase. Alternatively, as the output load 126 (ie, R ₀ ) and the output voltage (ie, V ₀ ) increase/decrease, the switching frequency (ie, f _sw ) decreases/increases in steps. The increase in the output load 126 (i.e., R ₀ ) and the output voltage (i.e., V ₀ ) means that the switching frequency (i.e., f _sw ) changes to a lower value, thus making the switching losses low and increasing the output load 126 (i.e., V 0 ) , R ₀ ) and the output voltage (i.e., V ₀ ) increase to provide appropriate or sufficient gain for the converter (i.e., single-stage resonant AC/DC converter).

Table 1 can be used as a lookup table for fixing the switching frequency (ie, f _sw ) after disabling the VFM controller 206 based on the converter load gain in PPT control mode.

Table 1: Lookup table for fixing f _sw according to converter load gain in PPT mode

i _o v _o fixed f _sw 0-3A 5V 500kHz 3-6A 11V 400kHz 3-6A 12V 400kHz 3-5A 15V 350kHz

According to an embodiment, the controller 106 is further configured to linearly adjust the DC bus voltage according to the output power and voltage. The DC bus voltage (i.e., V _b ) decreases linearly with the output power, i.e., the input AC current reference (i.e., i _{ac_ref} ) decreases by decreasing the DC bus voltage reference (i.e., V _busref ), which also causes the output voltage (i.e., V ₀ ) decreases.

According to an embodiment, the controller 106 is further configured to set the switches of the low-frequency half-bridge switching device circuit 102 according to the grid frequency. The controller 106 is used to control the low-frequency switches (ie, _Sa and _Sb ) of the low-frequency half-bridge switching device circuit 102 according to the grid frequency (eg, 50Hz/60Hz).

According to an embodiment, the controller 106 is further configured to: set the switches of the low-frequency half-bridge switching device circuit 102 to be turned off during the zero-crossing region, and to be complementary-conducting during each half-cycle of the grid frequency after the zero-crossing region. Pass. During the zero-crossing region when the converter (i.e., a single-stage resonant AC/DC converter) is allowed to operate in DCM, the controller 106 is configured to: turn off the low frequency half-bridge switching device circuit 102 (i.e., S _a and S _b ) . Furthermore, the controller 106 is configured to complementary conduct the low-frequency half-bridge switching device circuit 102 during each half-cycle of the grid frequency after the zero-crossing region during continuous conduction mode (CCM) operation of the converter. (i.e. S _a and S _b ).

According to an embodiment, the controller 106 is further configured to set the gate of the low-frequency half-bridge switching device circuit 102 to a low level if the output charging current ( _io ) is lower than the current threshold (i _th ). In addition, the gates (i.e., g _sa and g _sb ) of the low frequency switches (i.e., _Sa and S _b ) of the low frequency half-bridge switching device circuit 102 operate under extreme light loads with power <10 W or when the output load current (i.e., i _o ) is less than the threshold current (i _th ), for example, it turns off at 2A. By doing so, the body diodes of the low frequency switches (i.e., _Sa and _Sb ) of the low frequency half-bridge switching device circuit 102 block reverse power flow to prevent excessive power generation under extreme light load conditions.

According to an embodiment, the controller 106 is further configured to set the HF duty cycle to a constant value. Under extreme light load conditions, the ACM controller is disabled except for turning off the gates (i.e., g _sa and g _sb ) of the low frequency switches (i.e., _Sa and S _b ) of the low frequency half-bridge switching device circuit 102 , The high frequency duty cycle is changed to a constant value (for example, 15%). Fixing the high-frequency duty cycle at a constant value (i.e., 15%) ensures that the precise energy required under extreme light load conditions is generated while keeping the DC bus voltage low. This control technique enables power regulation as low as 1W, thus making the charger 100 (i.e., a single-stage resonant AC/DC converter) suitable for charger applications and ensuring regulation with the minimum load required (i.e., 1W).

Therefore, since the low-frequency switches (i.e., S _a and S _b ) of the low-frequency half-bridge switching device circuit 102 and the high-frequency GaN switches (i.e., S ₁ and S ) of the high-frequency half-bridge switching device circuit 104 are used at all operating points, respectively ₂ ) zero voltage switching (zerovoltage switching, ZVS), and zero current switching (ZCS) of the output synchronous rectification MOSFET switches (ie, SR ₁ and SR ₂ ) of the output synchronous rectification switching device circuit 122, charger 100 (i.e., single-stage resonant AC/DC converter) achieves high efficiency. The low-frequency switches (ie, _Sa and _Sb ) of the low-frequency half-bridge switching device circuit 102 are used to replace the input diodes (eg, _D1 and _D2 ) of the conventional single-stage AC/DC converter to further reduce losses. Similarly, the output synchronous rectification MOSFET switches (ie, SR ₁ and SR ₂ ) of the output synchronous rectification switching device circuit 122 are used to replace the output rectification diodes (eg, D ₀₁ and D ₀₂ ) of a conventional single-stage AC/DC converter. The ZVS and ZCS characteristics of charger 100 enable increased switching frequency (ie, f _sw ) while having smaller reactive component sizes. Due to the use of ACM control technology, wide gain at the input end is achieved. In ACM control technology, different input and DC bus voltage combinations (for example, 120Vac/340Vdc to 230Vac/405Vdc) change the duty cycle over a wide range. This way, the duty cycle follows the shape of the input current. When the switching frequency (i.e., f _sw ) is less than the set threshold frequency (i.e., f _th ) of 500 kHz, DC bus voltage regulation pushes the converter gain to the desired level that is easily regulated by the VFM control stage. In addition, PPT control technology further enhances converter regulation, providing wide output voltage regulation from 5V to 20V and power regulation from 1W to 75W. When the switching frequency (i.e., f _sw ) is greater than the threshold frequency (i.e., f _th ), the PPT control technique is used. The ACM control technique is applied to the converter using a PWM drive signal when the switching frequency (i.e., f _sw ) is less than the threshold frequency (i.e., f _th ) during normal mode operation. The PWM drive signal follows the sinusoidal waveform of the input current, therefore, the converter achieves a power factor of more than 95% and a total harmonic distortion value of less than 10%. Due to these conditions, the converter acts as a resistor from a grid perspective and a single input current sensor is required. This further reduces the root mean square (RMS) current flow through the low-frequency switches (i.e., S _a and S _b ) as well as the high-frequency switches (i.e., S ₁ and S ₂ ), and the converter also exhibits low cost. In this way, charger 100 (i.e., single-stage resonant AC/DC converter) exhibits wide input and wide output voltage regulation, high efficiency due to ZVS, and high efficiency due to combining the bridgeless PFC totem pole (i.e., PFC stage 204) with The integration of the switching resonant stage 110 (or LLC power stage) results in high power density. Since mobile phone or laptop batteries are charged at a constant current and gradually increasing power at the beginning, and then at a constant voltage and gradually decreasing power, wide output voltage regulation and power levels ≥1W are required. Therefore, the charger 100 can be used as a smartphone or laptop charger, as well as for general household electronic devices such as smart TVs and vacuum cleaners. The reason is that the charger 100 exhibits low cost, small size, and high efficiency.

Figure 3 is a graphical representation of a pulse power transfer (PPT) control technique of a controller according to an embodiment of the present invention. Figure 3 is described in conjunction with elements from Figures 1 and 2. Referring to FIG. 3 , a graphical representation 300 including a first waveform 302 , a second waveform 304 , a third waveform 306 , a fourth waveform 308 and a fifth waveform 310 is shown.

The first waveform 302 represents the high frequency (i.e., g s1 and g s2 ) applied to the gate terminals (i.e., g _s1 and g _s2 ) of the high frequency switches (i.e., S ₁ and S ₂ ) of the high frequency half-bridge switching device circuit 104 in the normal operating mode. high frequency, HF) PWM signal. The first waveform 302 may also be referred to as an HF gate signal. The second waveform 304 represents a low frequency (LF) pulse PWM signal (eg, 30 kHz). The third waveform 306 represents the resultant gate signal of the high frequency switches (ie, S ₁ and S ₂ ) of the high frequency half-bridge switching device circuit 104 in PPT mode. The composite gate signal is obtained by multiplying the first waveform 302 and the second waveform 304, that is, multiplying the HF PWM signal and the LF pulse PWM signal. The fourth waveform 308 represents the boost inductor current (ie, i _Lb ) flowing through the boost inductor 112 (ie, L _b ). The fifth waveform 310 represents the output voltage (ie, V ₀ ) of the converter (ie, a single-stage resonant AC/DC converter).

During the PPT control mode of the converter, the PPT controller 208 is enabled and the pulse frequency (ie, f _pulse ) is set to approximately 30 kHz, as shown in the second waveform 304 . The pulse frequency (ie, f _pulse ) is compared with the PPT mode duty cycle (ie, d1 ) of the PPT controller 208 to generate a pulse PWM signal (eg, 30 kHz), which is then ANDed using AND gate 210 The high frequency PWM signals represented by first waveform 302 are multiplied. The resulting PWM signal represented by third waveform 306 (ie, the high frequency PWM signal multiplied by the pulsed PWM signal) is used to control the high frequency switches (ie, S ₁ and S ₂ ) of the high frequency half-bridge switching device circuit 104 . When the pulse PWM signal _represented by the _second waveform 304 is low level, the high-frequency switch ( That is, S ₁ and S ₂ ).

Figure 4 shows in detail the control technique used by the controller according to an embodiment of the invention. Figure 4 is described in conjunction with elements from Figures 1, 2 and 3. Referring to Figure 4, a control technique 400 used by controller 106 (Figure 1) of charger 100 is shown.

When the switching frequency (ie, f _sw ) is less than the threshold frequency (ie, f _th ), the controller 106 is configured to perform VFM control or normal operation mode. In VFM control, in the outer loop of the PFC stage 204 of the ACM controller (or modulation controller 202), the measured DC bus voltage (i.e., V _b ) is compared with a constant DC bus reference value (i.e., V _busref ) are compared to generate an error signal. The generated error signal is applied to a low-bandwidth (8-10Hz) voltage proportional-integral (PI) controller. The output of the voltage PI controller is divided by the RMS square of the input AC voltage (i.e., Vac) and then multiplied by the measured AC voltage (i.e., Vac) to generate the input reference current (i _{ac_ref} ). The inner loop of the ACM controller (i.e., modulation controller 202) is a fast current loop with bandwidth >1 kHz that compares the input reference current (i _{ac_ref} ) to the measured input AC current (i.e., i _ac ) to determine An error signal is generated that is fed into the PI controller, thereby generating the output PFC duty cycle (i.e., HF duty cycle). Depending on the converter gain, the converter duty cycle (ie, HF duty cycle) saturates between 0.2 and 0.8. A zero-crossing compensation algorithm is used to compensate the PFC duty cycle (i.e., HF duty cycle) around the zero-crossing region. The zero-crossing compensation algorithm maintains the converter gain near the zero-crossing region. In addition, the controller 106 is configured to turn off the low-frequency (LF) switches (ie, _Sa and _Sb ) of the low-frequency half-bridge switching device circuit 102 to prevent reverse power flow. The generated PFC duty cycle (i.e., HF duty cycle) combines the CCM and DCM mode duty cycles before and after the zero-crossing region, respectively. The output voltage loop with >2kHz bandwidth of the VFM controller 206 is used to: regulate the output voltage using the VFM control and then compare it to the unique converter duty cycle (or HF duty cycle) to generate the HF PWM signal while pulsing the PWM The signal remains at a high signal level. The HF PWM signal and the pulse PWM signal pass through the AND gate 210 . Since the pulsed PWM signal is high level, only the HF PWM signal controls the high-frequency switches (ie, S ₁ and S ₂ ) of the high-frequency half-bridge switching device circuit 104 . Additionally, the controller 106 is configured to: turn off the low frequency switches (i.e., S _a and S _b ) of the low frequency half-bridge switching device circuit 102 during DCM operation and during each half cycle of the grid frequency (i.e., 50 Hz/60 Hz) Complementary conduction.

Furthermore, the magnitude of the inductor current (i.e., i _Lb ) is below zero during normal operating mode. Therefore, the boost inductor 112 (ie, L _b ) should be small enough to have a negative current value. The inductance value of boost inductor 112 (ie, L _b ) is calculated using equation (1).

Among them, V _ac , V _b , _Pac and f _sw are the root mean square (RMS) value of the input voltage, DC bus voltage, input power and switching frequency respectively.

Since ZVS is guaranteed at all operating points, the efficiency is high and therefore negative values of the inductor current (i.e., i _Lb ) can make the converter suitable for higher power levels. Another advantage is that the switching resonant stage 110 (or resonant tank) can be made to operate with a large margin below the resonant frequency and still maintain ZVS on the switch without causing any problems on the primary side of the converter (i.e., bridgeless rectification stage 108) and the secondary side (i.e., switching resonant stage 110) produce higher conduction losses. Compared to conventional single-stage AC/DC converters, the behavior of the switching resonant stage 110 (i.e., resonant tank) operating below the resonant frequency without hard switching enables the converter to meet wide input grid requirements with high efficiency Not much will change. Due to the wide duty cycle variation, different combinations of input voltages (i.e., Vac) of the switching resonant stage 110 (i.e., resonant tank) controlled by the DC bus voltage (120Vac/340Vdc to 230V ac/405Vdc) at the resonant frequency Operation below and above the region enables wide input voltage regulation and high efficiency.

When the switching frequency (ie, f _sw ) is greater than the threshold frequency (ie, f _th ), the controller 106 is configured to perform PPT control in the form of a mathematical expression, as shown by the dashed box 402 in FIG. 4 .

if f _sw >f _th

Enable C _pv1

Disable C _pv2

Fixed f _sw = f _swmax

Finish

if d1≥1

Enable C _pv2

Disable C _pv1

Set d1=1

Finish

In this operating mode of the converter (i.e., single-stage resonant AC/DC converter), the ACM controller (i.e., modulation controller 202) still operates, however, the VFM controller 206 is disabled and the switching frequency (i.e., , f _sw ) is set to the highest allowed frequency (e.g., 500kHz). Furthermore, as the output load 126 (ie, R ₀ ) and the output voltage increase/decrease, and the DC bus voltage decreases linearly according to the output power and voltage, the switching frequency (ie, f _sw ) decreases/increases in steps. Enable the PPT voltage loop and set the pulse frequency (i.e., f _pulse ). The pulse frequency (ie, _fpulse ) is compared to the PPT mode duty cycle (ie, d1) to generate a pulsed PWM signal (eg, 30kHz). The high frequency PWM signal and the pulse PWM signal pass through the AND gate 210 to provide a combined PWM signal for the high frequency switches (ie, S ₁ and S ₂ ) of the high frequency half bridge switching device circuit 104 as shown in FIG. 3 . Furthermore, when the input current (i.e., i ₀ ) is less than the threshold current (i.e., i _t ), such as 2A, the low-frequency switches (i.e., S a and S b ) of the low-frequency half-bridge switching device circuit 102 operate under extreme light load conditions (i.e., S _a and S _b ). That is, it is turned off when the power is <10W). The ACM controller is disabled and the HF duty cycle is set to a constant value of 15%.

Additionally, the PPT controller 208 (FIG. 2) is capable of regulating the DC output voltage (eg, 5Vdc) as low as possible at both low and high input AC voltages while maintaining high efficiency for both input AC voltages. Alternatively, the charger 100 using PPT control technology (ie, a single-stage resonant AC/DC converter) achieves wide output voltage regulation (eg, 5-20Vdc).

Figure 5 is a flowchart of control techniques performed by a controller during normal operation and PPT operating modes in accordance with an embodiment of the present invention. Figure 5 is described in conjunction with elements from Figures 1, 2, 3 and 4. Referring to FIG. 5 , a flow diagram 500 of a control technique used by the controller 106 of the charger 100 ( FIG. 1 ) is shown. Controller 106 is configured to perform operations 502 to 518.

In operation 502, flowchart 500 is initiated, indicated by "START".

In operation 504, the controller 106 determines an output DC voltage reference (ie, _Voref ).

In operation 506, the controller 106 determines a DC bus voltage reference (ie, _Vbusref ).

In operation 508, the controller 106 determines whether the switching frequency (ie, f _sw ) is above a threshold frequency (ie, f _th ). In one case, the controller 106 is configured to perform operation 510 if the switching frequency (ie, f _sw ) is above the threshold frequency (ie, f _th ), otherwise the controller 106 is configured to perform operation 512 .

In operation 510, the controller 106 is configured to execute the PPT control mode.

In operation 512, the controller 106 is configured to execute the VFM control mode.

In operation 514, the controller 106 determines the converter PPT mode duty cycle (d1). If the converter PPT mode duty cycle (d1) is equal to or greater than 1, the controller 106 is configured to perform operation 512, otherwise, the controller 106 is configured to perform operation 516.

In operation 516, the controller 106 determines whether the input current (ie, i ₀ ) is below a threshold current (ie, i _th ). If the input current (ie, i ₀ ) is lower than the threshold current (ie, i _th ), the controller 106 is configured to perform operation 518 , otherwise the controller 106 is configured to perform operation 508 again.

In operation 518, the controller 106 operates to turn off the low frequency switches (ie, _Sa and _Sb ) of the low frequency half-bridge switching device circuit 102 and set the HF duty cycle to a constant value of 15%.

Figure 6A shows the measured efficiency curves obtained over the output voltage range and low input AC voltage. Figure 6A is described in conjunction with elements of Figures 1, 2, 3, 4 and 5. Referring to Figure 6A, a graphical representation 600A is shown. Graphical representation 600A shows the measured efficiency of charger 100 (i.e., single-stage resonant AC/DC converter) obtained over a range of output voltages (e.g., 5-20Vdc) and low input AC voltages (e.g., 120Vac) curve.

Graphical representation 600A includes: X-axis 602 and Y-axis 604. The X-axis 602 represents the output power range in Watts (W) and the Y-axis 604 represents the measured efficiency range in Percent (%). Additionally, graphical representation 600A includes: first curve 606, second curve 608, third curve 610, fourth curve 612, and fifth curve 614.

The first curve 606 shows the measured efficiency range at an output voltage of 5Vdc. Similarly, the second curve 608, the third curve 610, the fourth curve 612, and the fifth curve 614 show the measured efficiency ranges at 11 Vdc, 12 Vdc, 15 Vdc, and 20 Vdc output voltages, respectively. Furthermore, the shaded part (e.g., the left part of the dotted line) represents the measured efficiency curve of the converter (i.e., single-stage resonant AC/DC converter) in the PPT control mode, and the shaded part (e.g., the right part of the dotted line) represents the conversion The measured efficiency curve of the converter (i.e., single-stage resonant AC/DC converter) in normal operating mode.

Figure 6B shows measured efficiency curves obtained over an output voltage range and a high input AC voltage according to an embodiment of the present invention. Figure 6B is described in conjunction with elements of Figures 1, 2, 3, 4 and 5. Referring to Figure 6B, a graphical representation 600B is shown. Graphical representation 600B shows the measured efficiency of charger 100 (i.e., single-stage resonant AC/DC converter) obtained over a range of output voltages (e.g., 5-20Vdc) and a high input AC voltage (e.g., 230Vac) curve.

Graphical representation 600B includes: X-axis 616 and Y-axis 618. The X-axis 616 represents the output power range in Watts (W) and the Y-axis 618 represents the measured efficiency range in Percent (%). Additionally, graphical representation 600B includes a first curve 620 , a second curve 622 , a third curve 624 , a fourth curve 626 , and a fifth curve 628 .

The first curve 620 shows the measured efficiency range at an output voltage of 5Vdc. Similarly, the second, third, fourth, and fifth curves 622, 624, 626, and 628 illustrate the measured efficiency ranges at 11 Vdc, 12 Vdc, 15 Vdc, and 20 Vdc output voltages, respectively. Furthermore, the shaded part (e.g., the left part of the dotted line) represents the measured efficiency curve of the converter (i.e., single-stage resonant AC/DC converter) in the PPT control mode, and the shaded part (e.g., the right part of the dotted line) represents the conversion The measured efficiency curve of the converter (i.e., single-stage resonant AC/DC converter) in normal operating mode.

In addition, Table 2 shows the DC bus voltage settings for low and high input AC voltages and the peak efficiency at different power levels, where the corresponding output voltage is 5-20Vdc. Figures 6A and 6B show measured efficiency curves for low input AC voltage (eg, 120Vac) and high input AC voltage (eg, 230Vac), respectively, at full load of 150W, 20Vdc. The peak efficiencies at low input and high input AC voltage are 95.44% and 95.18% respectively, which are similar efficiencies compared to traditional single-stage AC/DC converters.

Table 2: DC bus voltage settings for low and high input AC voltage, including measured efficiency

Figure 7 shows the performance of a converter in terms of power factor (PF) load resistance according to an embodiment of the present invention. Figure 7 is described in conjunction with elements from Figures 1, 2, 3, 4 and 5. Referring to Figure 7, a graphical representation 700 is shown. Graphical representation 700 illustrates the performance of a converter (ie, a single-stage resonant AC/DC converter) with respect to PF load resistance.

Graphical representation 700 includes: X-axis 702 and Y-axis 704. The X-axis 702 represents the output power range in Watts (W), and the Y-axis 704 represents PF. Additionally, graphical representation 700 includes a first curve 706 , a second curve 708 , and a shaded portion 710 .

The first curve 706 represents the behavior of power factor at low input AC voltage (eg, 120 Vac_rms). Additionally, the first curve 706 indicates that the PF is greater than 96% at full power load (eg, 150W). At full power load, the converter (i.e., single-stage resonant AC/DC converter) achieves low total harmonic distortion, THD (e.g., <10%), high PF (e.g., >96%), high power density, and High peak efficiency (e.g., >95%). The second curve 708 represents the behavior of power factor at high input AC voltage (eg, 230 Vac_rms). At high input AC voltage, the PF decreases slightly as the power is reduced. However, below 75W power, THD requirements are not required in the Class D requirements as shown by shaded portion 710. When the power is ≥75W, the converter exits PPT mode and still meets IEC Class D requirements.

Figure 8 shows changes in measured total harmonic distortion values of a converter as the number of harmonics increases at high input AC voltages according to an embodiment of the present invention. Figure 8 is described in conjunction with elements from Figures 1, 2, 3, 4 and 5. Referring to Figure 8, a bar graph representation 800 is shown. Bar graph representation 800 shows the measured total harmonic distortion of a converter (i.e., a single-stage resonant AC/DC converter) at a high input AC voltage (e.g., 230 Vac_rms) with a frequency of 50 Hz and a power load of 150 W. The value changes as the harmonic number increases.

Bar graph representation 800 includes: X-axis 802 and Y-axis 804. The X-axis 802 represents the harmonic number, and the Y-axis 804 represents the total harmonic distortion (THD) value. Additionally, the bar graph representation 800 represents the measured THD value for each harmonic up to the 39th harmonic. This shows that the converter (i.e., single-stage resonant AC/DC converter) achieves the required THD value to meet Class D requirements with a large margin at high input AC voltages. The converter also achieves the required THD value to meet Class D requirements at low input AD voltages with a greater margin than at high input AC voltages.

Figure 9 is a circuit diagram of a charger according to another embodiment of the present invention. Figure 9 is described in conjunction with elements from Figure 1. Referring to Figure 9, a circuit diagram of charger 900 is shown. Charger 900 is represented by a dashed box for illustrative purposes only and does not form part of the circuit.

Charger 900 is similar to charger 100 (FIG. 1), except that charger 900 uses a pair of diodes 902 (also denoted D ₁ and D ₂ ) and another pair of diodes 904 (also denoted D ₀₁ and D ₀₂ ). A pair of diodes 902 (i.e., D ₁ and D ₂ ) replaces the low frequency half-bridge switching device circuit 102 (i.e., _Sa and S _b ), while another pair of diodes 904 (i.e., D ₀₁ and D ₀₂ ) replaces the output synchronous rectification switching device circuit 122 (ie, SR ₁ and SR ₂ of charger 100 ).

The control technology of VFM control and PPT control is also applicable to different chargers 900. The difference is that the inductor current amplitude cannot go below zero because a pair of diodes 902 (i.e., D ₁ and D ₂ ) prevents reverse power flow.

Similar to the charger 100, the charger 900 can be used as a smartphone or laptop charger, as well as for general household electronic devices such as smart TVs and vacuum cleaners.

Modifications may be made to the embodiments of the invention described above without departing from the scope of the invention as defined by the appended claims. Expressions such as "comprises," "includes," "incorporated," "is/for" and the like used to describe and claim the present invention are intended to be construed in a non-exclusive manner, allowing for items, components or elements not expressly described also exists. References to the singular shall also be construed as referring to the plural. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described as "exemplary" is not necessarily to be construed as more preferred or advantageous than other embodiments, and/or to exclude the combination of features of other embodiments. As used herein, the word "optionally" means "provided in some embodiments and not provided in other embodiments." It is to be understood that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention that are, for clarity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as any other described embodiment of the invention.

Claims (14)

1. A charger (100, 900) for wide input/output voltage regulation, the charger (100, 900) comprising: a low frequency half-bridge switching device circuit (102), a high frequency half-bridge switching device circuit (104), and a controller (106), wherein the controller (106) is configured to:

receiving an output DC voltage reference;

determining a DC bus voltage reference;

determining a switching frequency from the DC bus voltage reference;

determining whether the switching frequency is above a threshold frequency,

if so, the first and second data are not identical,

pulse power transfer (pulse power transfer, PPT) control is performed and, if not,

performing variable frequency modulation (variable frequency modulation, VFM) control;

receiving an output charging current;

determining whether the output charging current is below a current threshold,

if so, the first and second data are not identical,

the low frequency half-bridge switching device circuit (102) is disabled.

2. The charger (100, 900) of claim 1 wherein the controller (106) is further configured to: if the switching frequency is higher than the threshold frequency,

determining a PPT mode duty cycle;

determining whether the PPT mode duty cycle is equal to 1, if so,

variable frequency modulation (variable frequency modulation, VFM) control is performed, otherwise pulse power transmission (pulse power transfer, PPT) control is performed.

3. The charger (100, 900) of claim 1 or 2, wherein the controller (106) is further configured to: -setting the gate of the low frequency half-bridge switching device circuit (102) to a low level when the output charging current is below the current threshold.

4. A charger (100, 900) according to claim 1, 2 or 3, wherein the controller (106) is further configured to: the high frequency duty cycle is set to a constant value.

5. The charger (100, 900) of any of the preceding claims, wherein the controller (106) is further configured to: the switching of the low frequency half-bridge switching device circuit (102) is set according to the grid frequency.

6. The charger (100, 900) of claim 5 wherein said controller (106) is further configured to: the switches of the low frequency half-bridge switching device circuit (102) are arranged to be turned off during a zero crossing and to be complementarily turned on within each half period of the grid frequency after the zero crossing.

7. The charger (100, 900) of any of the preceding claims, wherein the controller (106) is further configured to: the VFM control loop is disabled and the switching frequency is set to the highest allowed frequency while the pulsed power transfer PPT control is performed.

8. The charger (100, 900) of any of the preceding claims, wherein the controller (106) is further configured to: the switching frequency is adjusted stepwise as the output load and output voltage of the charger (100, 900) change.

9. The charger (100, 900) of claim 8 wherein said controller (106) is further configured to: the DC bus voltage is linearly adjusted according to the output power and voltage.

10. The charger (100, 900) of any of the preceding claims, wherein the charger (100, 900) further comprises an and gate (210), the and gate (210) being configured to: the high frequency PWM signal and the pulsed PWM signal are combined during PPT mode to provide a combined PWM signal to the high frequency half-bridge switching device circuit (104).

11. The charger (100, 900) of any of the preceding claims, wherein the charger (100, 900) further comprises a bridgeless rectifier stage (108), the bridgeless rectifier stage (108) comprising: a boost inductor (112) and a DC bus capacitor (114) coupled with the switching resonant stage (110).

12. The charger (100, 900) of claim 11 wherein said switching resonant stage (110) includes: a resonant inductor (116), a resonant capacitor (118), and a high frequency transformer (120) connected to an output synchronous rectification switching device circuit (122).

13. The charger (100, 900) of any of the preceding claims, wherein the controller (106) further comprises: modulation controller (202) for integrated power factor correction (power factor correction, PFC) stage+llc stage, output stage regulation using variable frequency modulation controller (206) in normal operation and pulsed power transfer controller (208) in PPT mode of operation, respectively, to achieve both wide AC input voltage and wide DC output voltage regulation.

14. The charger (100, 900) of claim 13 wherein the modulation controller (202) includes a PFC stage (204) having an outer loop for DC bus voltage control, an inner loop of current, and a zero crossing compensation algorithm for generating a converter duty cycle.