CN117501453B - Fixed charge development method, method for manufacturing thin film transistor, and thin film transistor - Google Patents

Abstract

The invention provides a fixed charge display method, a thin film transistor manufacturing method and a thin film transistor. The method for generating a fixed charge is a method for generating a fixed charge in an insulating film on a back channel side in a semiconductor element having a channel layer including an oxide semiconductor, wherein a metal film is formed on a surface of the insulating film after the insulating film is formed, and the insulating film is ion-implanted through the metal film, whereby the fixed charge is generated in the insulating film.

Description

Fixed charge development method, method for manufacturing thin film transistor, and thin film transistor

Technical Field

The invention relates to a fixed charge display method, a method for manufacturing a thin film transistor and a thin film transistor.

Background Art

In recent years, development of thin film transistors (TFTs) using oxide semiconductors such as In-Ga-Zn-O (indium gallium zinc oxide (IGZO)) for channel layers has been actively pursued.

As such a thin film transistor, for example, Patent Document 1 discloses a thin film transistor using aluminum oxide with a low film density (2.70 g/cm ³ to 2.79 g/cm ³ ) as an insulating film constituting a gate insulating layer or a channel protection layer in contact with a channel layer. It is also described that in the thin film transistor, by using aluminum oxide with a low film density as an insulating film, the negative fixed charge density in the insulating film can be increased, thereby shifting the threshold voltage of the thin film transistor in a positive direction and improving reliability.

Prior art literature

Patent Literature

Patent Document 1: Japanese Patent Application Publication No. 2011-222767

Summary of the invention

Problem to be solved by the invention

However, in the thin film transistor disclosed in Patent Document 1, negative fixed charges are expressed by reducing the film density, in other words, by deteriorating the film quality. Therefore, there is a possibility that reliability may be reduced due to an increase in leakage current or environmental changes.

The present invention has been made in view of such problems, and a main object of the present invention is to efficiently generate necessary fixed charges in an insulating film on the back channel side used in a semiconductor element while suppressing degradation of film quality.

Technical means of solving problems

That is, the fixed charge manifestation method of the present invention is a method for manifesting fixed charges in an insulating film on the back channel side of a semiconductor element having a channel layer including an oxide semiconductor, and the method is characterized in that after the insulating film is formed on a substrate, a metal film is formed on the surface of the insulating film, and ions are implanted into the insulating film through the metal film, thereby manifesting fixed charges in the insulating film.

In such a structure, since ions are implanted into the insulating film via the metal film, the defects generated by the ion implantation are distributed not entirely in the insulating film but also in the metal film, thereby reducing the degradation of the film quality caused by the defects in the insulating film. Furthermore, by adjusting the thickness of the metal film or the range of the implanted ions during ion implantation and adjusting the distribution of defects formed in the insulating film, fixed charges can be manifested in the insulating film, and the fixed charge density can be easily adjusted. Furthermore, since the film quality of the entire insulating film is not changed but only the film quality of the surface layer is changed by ion implantation, partial functions can be added while basically maintaining the original insulating properties of the insulating film.

Preferably, in the fixed charge developing method, an average range of ions based on the ion implantation is larger than a thickness of the metal film and smaller than a sum of a thickness of the metal film and a thickness of the insulating film.

In this way, even if defects caused by ion implantation are distributed in the metal film, most of them can be distributed in the insulating film, so that fixed charges can be efficiently expressed in the insulating film.

Furthermore, in the fixed charge developing method, preferably, the sum of the average range of the ions and the standard deviation thereof is smaller than the sum of the thickness of the metal film and the thickness of the insulating film.

In this way, the distribution of defects formed in the insulating film can be increased, and the fixed charge density of the insulating film can be increased.

As a specific form of the insulating film that significantly exerts the effect of the fixed charge developing method, a silicon oxide film or a silicon nitride oxide film can be cited.

Specific forms of the metal film that significantly exert the effect of the fixed charge developing method include aluminum, aluminum alloys, molybdenum, molybdenum alloys, titanium, or titanium alloys.

Specific forms of ions implanted by the ion implantation that significantly exert the effect of the fixed charge development method include at least one selected from atomic ions of O, N, C, etc., molecular ions of _O2 , _N2 , C2 _{, etc.} , and rare gas ions of Ar, etc.

In addition, the manufacturing method of the thin film transistor of the present invention is a method for manufacturing a top-gate thin film transistor, and the manufacturing method of the thin film transistor is characterized in that it includes: a process of forming a fixed charge layer having a fixed charge on the surface of a substrate; a process of forming a channel layer including an oxide semiconductor on the surface of the fixed charge layer; and a process of forming a gate insulating layer on the surface of the channel layer, and the process of forming the fixed charge layer includes: a process of forming a first insulating film on the surface of the substrate; a process of forming a metal film on the surface of the first insulating film; and a process of ion implantation into the first insulating film via the metal film.

In the case of such a method for manufacturing a thin film transistor, since ion implantation is performed into the first insulating film via the metal film, a part of the defects generated by the ion implantation can be distributed in the metal film, and the degradation of the film quality caused by the defects in the first insulating film can be reduced. In addition, by adjusting the thickness of the metal film or the range of the implanted ions during ion implantation and adjusting the distribution of defects formed in the first insulating film, the fixed charge density in the first insulating film can be easily adjusted. Thus, the electrical characteristics of the thin film transistor can be controlled by fixed charges, and a thin film transistor with high mobility and easy to operate at a positive threshold voltage can be manufactured.

In addition, since the fixed charge layer for controlling the threshold voltage is provided on the back channel side, the generation of leakage current due to the distribution of implanted ions in the first insulating film can be suppressed, thereby enabling the manufacture of a stable thin film transistor.

Preferably, in the method for manufacturing the thin film transistor, the step of forming the fixed charge layer includes the step of forming a second insulating film on the surface of the metal film after ion implantation into the first insulating film.

By forming such a second insulating film, diffusion of impurities from the metal film to the channel layer can be prevented, thereby manufacturing a thin film transistor with more stable characteristics.

Furthermore, preferably, in the method for manufacturing a thin film transistor, the second insulating film is a stacked film of a silicon nitride film and a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film.

In this manner, the second insulating film functions as an oxygen supply source to the lower portion of the oxide semiconductor, namely, the channel layer, and thus a thin film transistor having more stable characteristics can be manufactured.

Preferably, the second insulating film has a thickness of 50 nm or more and 200 nm or less.

In this manner, an electric field can be efficiently applied from the fixed charge layer to the channel layer.

In addition, the thin film transistor of the present invention is a top-gate thin film transistor in which a fixed charge layer having a fixed charge, a channel layer including an oxide semiconductor, and a gate insulating layer are stacked in sequence on a substrate, and the thin film transistor is characterized in that the fixed charge layer includes an insulating film formed on the substrate, and a metal film formed on the surface of the insulating film, elements added by ion implantation are distributed in the insulating film and the metal film, and the maximum value of the distribution of the elements in the insulating film is greater than the average value of the distribution of the elements in the metal film.

If this thin film transistor is used, the same effects as those of the fixed charge developing method and the thin film transistor manufacturing method can be achieved.

Effects of the Invention

According to the present invention thus constituted, necessary fixed charges can be efficiently generated in the insulating film on the back channel side used in the semiconductor element while suppressing degradation of the film quality.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view schematically showing the structure of a thin film transistor manufactured by the fixed charge developing method according to this embodiment.

FIG. 2 is a diagram illustrating the distribution of implanted ions and defect distribution by ion implantation.

FIG. 3 is a diagram schematically showing a manufacturing process of the thin film transistor according to the embodiment.

FIG. 4 is a diagram schematically showing a manufacturing process of a thin film transistor according to another embodiment.

FIG. 5 is a diagram schematically showing the structure of an evaluation sample used in Examples.

FIG. 6 is a diagram showing simulation results in Example 1, and is a diagram showing the relationship between the energy of implanted ions and the implantation depth.

FIG. 7 is a graph showing the measurement results in Example 1, and is a graph showing the relationship between the ion implantation amount and the fixed charge density.

Explanation of symbols

100: Thin Film Transistor

1: Substrate

2: Fixed charge layer

21: First insulating film

22: Metal film

23: Second insulating film

3: Channel layer (active layer)

4: Gate insulation layer

5: Gate electrode layer

6: Insulation layer

7: Source electrode

8: Drain electrode

DETAILED DESCRIPTION

Hereinafter, a thin film transistor 100 manufactured by the fixed charge developing method of the present invention and an embodiment of a manufacturing method thereof will be described.

＜1. Thin-film transistor＞

The thin film transistor 100 of this embodiment is a so-called top-gate TFT, and is a thin film transistor using an oxide semiconductor in a channel. Specifically, as shown in FIG1 , it has a substrate 1, a fixed charge layer 2, a channel layer (active layer) 3, a gate insulating layer 4, a gate electrode layer 5, an insulating layer 6, a source electrode 7, and a drain electrode 8, which are stacked in sequence from the substrate 1 side. Each part is described in detail below.

(1) Substrate

The substrate 1 includes any material that can transmit light, and may include, for example, plastic (synthetic resin) such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), acrylic, polyimide, or glass.

(2) Fixed charge layer

The fixed charge layer 2 has positive fixed charges. The fixed charge layer 2 of this embodiment is formed by stacking a plurality of films, and specifically, is a fixed charge layer in which a first insulating film 21 , a metal film 22 , and a second insulating film 23 are stacked in this order from the substrate 1 side.

The first insulating film 21 may include any insulating material having high insulating properties, such as silicon oxide film or silicon oxynitride film, but is not limited thereto. Furthermore, the first insulating film 21 may also be a diffusion prevention film formed in advance on the surface of the substrate 1 .

The metal film 22 may include any metal material, such as aluminum, aluminum alloy, molybdenum, molybdenum alloy, titanium or titanium alloy, but is not limited thereto. The thickness of the metal film is preferably less than 30 nm, more preferably less than 10 nm, but is not limited thereto because it also depends on the metal material or ion implantation conditions.

The second insulating film 23 is preferably an insulating material containing oxygen, for example, a stacked film of a silicon nitride film and a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. From the perspective of effectively applying an electric field to the channel layer 3 via the second insulating film 23, the thickness of the second insulating film 23 is preferably, for example, not less than 50 nm and not more than 200 nm, but is not limited thereto.

(3) Channel layer

The channel layer 3 is formed by applying a gate voltage between the source electrode 7 and the drain electrode 8 to allow current to pass. The channel layer 3 includes an oxide semiconductor, for example, an oxide of at least one element selected from In, Ga, Zn, Sn, Al, Ti, etc. as a main component. As specific examples of materials constituting the channel layer 3, for example, oxide materials with In ₂ O ₃ as the main component, In-Ga-Zn-O (IGZO), In-Al-Mg-O, In-Al-Zn-O or In-Hf-Zn-O, etc. can be cited. The channel layer 3, for example, includes an amorphous (amorphous) oxide semiconductor film. The channel layer 3 of this embodiment is a single-layer structure, but is not limited to this, and can also be a stacked structure composed of multiple layers with different compositions or crystallinity. The thickness of the channel layer 3 is preferably, for example, greater than 30 nm and less than 100 nm, and more preferably greater than 30 nm and less than 50 nm.

The channel layer 3 is formed in a manner covering a portion of the surface of the substrate 1. In addition, a source region layer S and a drain region layer D are formed on the surface of the substrate 1 in a manner sandwiching the channel layer 3 from both sides and electrically connected to the channel layer 3. The source region layer S and the drain region layer D are electrically connected to the source electrode 7 and the drain electrode 8, respectively, via a contact hole H formed along the stacking direction. Furthermore, the contact hole H is filled with a metal such as molybdenum.

(4) Gate insulation layer

The gate insulating layer 4 is formed to cover the surface of the channel layer 3, the source region layer S, and the drain region layer D. The gate insulating layer 4 includes any insulating material such as an oxide film, a nitride film, and a nitride oxide film having high insulating properties. The gate insulating layer 4 may be, for example, an insulating film including one or more oxides selected from SiO _x , SiN _x , SiON, Al ₂ O ₃ , Y ₂ O ₃ , Ta ₂ O ₅ , Hf _2, etc. The gate insulating layer 4 may be a gate insulating layer having a single-layer structure or a stacked structure of two or more layers of these conductive films.

(5) Gate electrode layer

The gate electrode layer 5 is a gate electrode layer for controlling the carrier density in the channel layer 3 by applying a gate voltage to the thin film transistor 100. The gate electrode layer 5 is formed on the surface of the gate insulating layer 4 in a manner of being located directly above the channel layer 3. More specifically, the gate electrode layer 5 is formed in a manner in which the positions of its two end faces along the intralayer direction (direction orthogonal to the stacking direction) coincide with the positions of the two end faces of the channel layer 3. The gate electrode layer 5 includes any metal material having high conductivity, for example, it may include one or more metals selected from Si, Al, Mo, Cr, Ta, Ti, Pt, Au, Ag, etc., and may also include alloys such as Al alloys, Ag alloys, Mo alloys, and Ti alloys.

(6) Insulation layer

The insulating layer 6 insulates the gate electrode layer 5 from the source electrode 7 and the drain electrode 8 and includes, for example, a silicon oxide film containing fluorine. The insulating layer 6 is formed to cover the entire surface (upper surface and side surfaces) of the gate electrode layer 5 and the surface of the gate insulating layer 4 .

(7) Source electrode, drain electrode

The source electrode 7 and the drain electrode 8 are formed separately from each other in a manner that partially covers the surface of the channel layer 3. The source electrode 7 and the drain electrode 8, like the gate electrode layer 5, contain a material having high conductivity so as to function as an electrode. The source electrode 7 and the drain electrode 8 may be a single-layer structure containing a single material, or a stacked structure in which a plurality of layers containing different materials are stacked. The source electrode 7 and the drain electrode 8 are electrically connected to the source region layer S and the drain region layer D, respectively, via a contact hole H that penetrates the insulating layer 6 and the gate insulating layer 4 along the stacking direction.

(8) Fixed charges in the fixed charge layer

Furthermore, in the thin film transistor 100 of this embodiment, positive fixed charges formed (developed) by ion implantation exist in the first insulating film 21 near the interface with the metal film 22 .

In the thin film transistor 100 of the present embodiment, by adjusting the relationship between the thickness d _i of the first insulating film 21, the thickness d _M of the metal film 22, the average range R _p of implanted ions (for example, atomic ions such as O, N, C, molecular ions such as O ₂ , N ₂ , C ₂ , rare gas ions such as Ar), and their standard deviation ΔR _p , the distribution of implanted ions and the distribution of defects in the first insulating film 21 are adjusted, and the positive fixed charge density in the fixed charge layer 2 is adjusted.

Specifically, the fixed charge layer 2 of the present embodiment is configured to satisfy both the following conditions (A) and (B).

(A) The average range _Rp of ions implanted by ion implantation is greater than the thickness _dM of the metal film 22 ( _Rp > _dM ).

(B) The average range _Rp of ions implanted by ion implantation is smaller than the sum of the thickness _dM of the metal film and the thickness _dI of the first insulating film 21 ( _dM + _dI > _Rp ).

Furthermore, the fixed charge layer 2 of the present embodiment is configured to satisfy the following condition (C).

(C) The sum of the average range _Rp of the ions and its standard deviation _ΔRp is smaller than the sum of the thickness _dM of the metal film 22 and the thickness d _i of the first insulating film 21 ( _dM +d _i > _Rp + _ΔRp )

The average ion range _Rp is the depth position of the maximum value of the distribution of the implanted ions in the depth direction (stacking direction) in the film, and the standard deviation _ΔRp at this time is an indicator showing the spread of the distribution toward the inner side (intra-layer direction).

Furthermore, implanted ions and defects caused by ion implantation are distributed in both the first insulating film 21 and the metal film 22. As shown in FIG. 2 , the distribution of implanted ions increases from the metal film 22 toward the first insulating film 21, and becomes the largest in the first insulating film 21. In addition, the distribution of defects caused by ion implantation also increases from the metal film 22 toward the first insulating film 21, and becomes the largest in the first insulating film 21 (more specifically, near the interface with the metal film 22). Furthermore, the depth at which the distribution of implanted ions becomes the largest is greater than the depth at which the distribution of defects becomes the largest.

In addition, from the perspective of element distribution, in the thin film transistor 100 of the present embodiment, the element added by ion implantation is distributed in both the first insulating film 21 and the metal film 22. Specifically, in the film thickness direction, the maximum value of the distribution of the element in the first insulating film 21 is greater than the average value of the distribution of the element in the metal film 22. In the present embodiment, the distribution of the element increases from the metal film 22 toward the first insulating film 21, and becomes the largest in the first insulating film 21.

<2. Method for manufacturing thin film transistor>

Next, a method for manufacturing the thin film transistor 100 having the above structure is described with reference to FIG3. The method for manufacturing the thin film transistor 100 of this embodiment includes a fixed charge layer forming step, a channel layer forming step, a gate insulating layer forming step, a gate electrode forming step, a source region/drain region forming step, an insulating layer forming step, and a source electrode/drain electrode forming step. Each step is described below.

(1) Fixed Charge Layer Formation Step

A fixed charge layer 2 is formed on a substrate 1. The process includes a first insulating film forming process, a metal film forming process, a first ion implantation process, and a second insulating film forming process in sequence.

(1-1) First Insulating Film Formation Step

First, a first insulating film 21 such as a silicon oxide film or a silicon oxynitride film is formed on the substrate 1. The first insulating film 21 is formed to cover the entire surface of the substrate 1 by a known method such as plasma chemical vapor deposition (CVD).

(1-2) Metal Film Formation Step

Next, the metal film 22 is formed on the surface of the first insulating film 21. The metal film 22 is formed so as to cover the entire surface of the first insulating film 21 by a known method such as vacuum deposition.

(1-3) First ion implantation step

Next, as shown in FIG. 3( a ), ion implantation is performed into the first insulating film 21 through the formed metal film 22. The ion implantation can be performed by a known ion implantation method. The ion implantation step is performed by implanting ions into the entire surface of the first insulating film 21 when viewed from the stacking direction. The types of ions implanted are, for example, atomic ions of O, N, C, etc., molecular ions of O ₂ , N ₂ , C _2, etc., and rare gas ions of Ar, etc., but are not limited thereto. The ion energy is, for example, 5 keV to 30 keV, but is not limited thereto. In addition, the ion implantation amount (dose) is, for example, 1×10 ¹³ ions/cm ² to 1×10 ¹⁵ ions/cm ² , but is not limited thereto. The ion energy and the ion implantation amount are set so that the average range R _p of the ions and the standard deviation ΔR _p thereof satisfy the conditions (A) and (B), preferably further satisfy the condition (C). As a result, positive fixed charges are formed in the first insulating film 21.

(1-4) Second Insulating Film Formation Step

After the first ion implantation step, as shown in FIG3(b), a second insulating film 23 such as a stacked film of a silicon nitride film and a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film is formed on the metal film 22. The second insulating film 23 can also be formed by a known method such as vacuum evaporation to cover the entire surface of the metal film 22.

(2) Channel layer formation process

Next, a channel layer 3 is formed on the fixed charge layer 2 (specifically, on the second insulating film 23). The channel layer 3 can be formed by a known method. For example, the channel layer 3 can be formed by sputtering a conductive oxide sintered body such as InGaZnO as a target using plasma to cover the entire surface of the second insulating film 23. In addition, the present invention is not limited to this, and the channel layer 3 including an oxide semiconductor can also be formed by other methods.

(3) Gate Insulation Layer Formation Step

Next, gate insulating layer 4 made of any insulating material such as oxide film, nitride film, oxynitride film, etc. is formed on channel layer 3. Here, gate insulating layer 4 is formed to cover the entire surface of channel layer 3 by a known method such as plasma CVD.

(4) Gate Electrode Formation Step

Next, the gate electrode layer 5 is formed on the gate insulating layer 4. The gate electrode layer 5 can be formed by a known method such as a vacuum deposition method.

(5) Source Region/Drain Region Formation Step

Next, as shown in FIG3(c), a source region layer S and a drain region layer D are formed so as to sandwich the channel layer 3. The above steps include a resist patterning step, an etching step, and a second ion implantation step.

(5-1) Resist Patterning Step

First, a photoresist R is applied on the gate electrode layer 5 , and then exposed and developed. The photoresist R selectively remains only on the portion that will eventually become the channel layer 3 on the gate electrode layer 5 .

(5-2) Etching process

Next, portions of the gate electrode layer 5 that are not protected by the photoresist R are removed by etching, thereby patterning the gate electrode layer 5 .

(5-3) Second ion implantation step

Next, ion implantation is performed into the region outside the gate electrode layer 5 in the channel layer 3 through the gate insulating layer 4, thereby forming a source region layer S and a drain region layer D on both sides of the channel layer 3. In the ion implantation step, the stacked photoresist R and the gate electrode layer 5 are used as masks. The ion implantation in the step can be performed by any known method.

(6) Insulation layer forming process

After the second ion implantation step, as shown in FIG3(d), the photoresist R is removed to form an insulating layer 6. The insulating layer 6 is formed to cover the entire surface of the gate insulating layer 4 and the gate electrode layer 5. The insulating layer 6 can be formed by any method such as plasma CVD.

(7) Source Electrode/Drain Electrode Formation Step

Then, as shown in FIG3(e), a source electrode 7 and a drain electrode 8 are formed on the gate insulating layer 4. The source electrode 7 and the drain electrode 8 can be formed by a known method such as radio frequency (RF) magnetron sputtering. The source electrode 7 and the drain electrode 8 are connected to the source region layer S and the drain region layer D respectively through a contact hole H formed along the stacking direction by etching or the like.

Through the above operations, the thin film transistor 100 of this embodiment can be obtained.

<3. Effects of the present embodiment>

According to the manufacturing method of the thin film transistor 100 of the present embodiment, since ion implantation is performed on the first insulating film 21 via the metal film 22, the defects generated by the ion implantation can be distributed not entirely in the first insulating film 21 but also in the metal film 22, thereby reducing the degradation of the film quality caused by the defects in the first insulating film 21. In addition, by adjusting the thickness of the metal film 22 or the range of the implanted ions during ion implantation and adjusting the distribution of the defects formed in the first insulating film 21, positive fixed charges can be expressed in the first insulating film 21, and the fixed charge density can be easily adjusted. In addition, since the film quality of the entire first insulating film 21 is not changed but only the film quality of the surface layer is changed by ion implantation, partial functions can be added while the original insulating properties of the first insulating film 21 are basically maintained.

It should be noted that the fixed charge developing method of the present invention is not limited to the above-described embodiment.

For example, in the above embodiment, the method for manufacturing the thin film transistor 100 is described as an example of the fixed charge developing method, but the present invention is not limited thereto. In other embodiments, the fixed charge developing method of the present invention can be used in a method for manufacturing a semiconductor element other than a thin film transistor.

In addition, in a method of manufacturing the thin film transistor 100 according to another embodiment, as shown in FIG. 4 , after forming the metal film 22 on the first insulating film 21 and before forming the second insulating film 23 , the first insulating film 21 and the metal film 22 may be patterned.

In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present invention. For example, it can be understood by those skilled in the art that the above-described multiple exemplary embodiments are specific examples of the following forms.

(Form 1) A method for developing fixed charges, which is a method for developing fixed charges in an insulating film on the back channel side of a semiconductor element having a channel layer including an oxide semiconductor. In the method, after the insulating film is formed on a substrate, a metal film is formed on the surface of the insulating film, and ions are implanted into the insulating film through the metal film, thereby developing fixed charges in the insulating film.

(Form 2) The fixed charge developing method according to Form 1, wherein an average range of ions based on the ion implantation is greater than a thickness of the metal film and less than a sum of a thickness of the metal film and a thickness of the insulating film.

(Form 3) A fixed charge development method according to Form 2, wherein a sum of an average range of the ions and a standard deviation thereof is smaller than a sum of a thickness of the metal film and a thickness of the insulating film.

(Form 4) The fixed charge developing method according to any one of Forms 1 to 3, wherein the insulating film is a silicon oxide film or a silicon oxynitride film.

(Form 5) The fixed charge developing method according to any one of Forms 1 to 4, wherein the metal film includes aluminum, an aluminum alloy, molybdenum, a molybdenum alloy, titanium, or a titanium alloy.

(Form 6) The fixed charge developing method according to any one of Forms 1 to 5, wherein the type of ions implanted by the ion implantation is one or more selected from atomic ions such as O, N, and C, molecular ions such as _O2 , _N2 , and _C2 , or rare gas ions such as Ar.

(Form 7) A method for manufacturing a thin film transistor, which is a method for manufacturing a top-gate thin film transistor, the method for manufacturing a thin film transistor comprising: a process of forming a fixed charge layer having a fixed charge on a surface of a substrate; a process of forming a channel layer comprising an oxide semiconductor on a surface of the fixed charge layer; and a process of forming a gate insulating layer on a surface of the channel layer, the process of forming the fixed charge layer comprising: a process of forming a first insulating film on a surface of the substrate; a process of forming a metal film on a surface of the first insulating film; and a process of implanting ions into the first insulating film via the metal film.

(Form 8) The method for manufacturing a thin film transistor according to Form 7, wherein the step of forming the fixed charge layer includes the step of forming a second insulating film on the surface of the metal film after ion implantation into the first insulating film.

(Form 9) The method for manufacturing a thin film transistor according to Form 8, wherein the second insulating film is a stacked film of a silicon nitride film and a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film.

(Form 10) The method for manufacturing a thin film transistor according to Form 8 or 9, wherein a thickness of the second insulating film is greater than or equal to 50 nm and less than or equal to 200 nm.

(Form 11) A thin film transistor is a top-gate thin film transistor in which a fixed charge layer having a fixed charge, a channel layer including an oxide semiconductor, and a gate insulating layer are stacked in sequence on a substrate, wherein the fixed charge layer includes an insulating film formed on the substrate, and a metal film formed on the surface of the insulating film, and elements added by ion implantation are distributed in the insulating film and the metal film, and a maximum value of the distribution of the elements in the insulating film is greater than an average value of the distribution of the elements in the metal film.

Example

<Example: Relationship between the thickness of the metal layer, the amount of ion implantation, and the fixed charge density>

The relationship between the thickness of the metal layer during ion implantation and the amount of ion implantation and the fixed charge density was evaluated by experiments.

(1) Evaluation samples

In the embodiment, as shown in FIG. 5 , two evaluation samples were prepared: an evaluation sample in which a thermal silicon oxide film and a metal layer were stacked on a silicon substrate (a sample with a metal layer), and an evaluation sample in which only a thermal silicon oxide film was stacked on a silicon substrate (a sample without a metal layer). In each evaluation sample, an n-type silicon substrate was used, and the resistivity was 1Ωcm to 10Ωcm. In addition, in each evaluation sample, the film thickness of the thermal silicon oxide film was set to 100nm. In addition, in the sample with a metal layer, an Al-Si alloy film with a film thickness of about 10nm was formed as the metal layer.

(2) Ion implantation

Then, for each prepared evaluation sample, ion implantation is performed by changing the ion implantation amount and the type of ions implanted. The ion implantation amount (dose) is set to 1×10 ¹³ ions/cm ² to 1×10 ¹⁵ ions/cm ² . In addition, the implantation ion type for the sample with a metal layer is set to N ⁺ , and the implantation ion type for the sample without a metal layer is set to N ⁺ , O ⁺ , and Ar ⁺ . In addition, for any evaluation sample, the implanted ion energy is set to 10 keV. Furthermore, the relationship between the ion energy of the implanted ions (N ⁺ , O ⁺ , Ar ⁺ ) and the implantation depth is calculated using simulation software (SRIM2013), and the results are shown in FIG6 . In the simulation, the object of ion implantation is set to a silicon oxide film (film thickness 100 nm) on a Si substrate, and the energy of the implanted ions is set to 5 keV to 30 keV.

(3) Evaluation of fixed charge density

Then, the fixed charge density of the thermal silicon oxide film in each evaluation sample after ion implantation was measured by the capacitance-voltage (C-V) method. In addition, for the sample without a metal layer, an electrode in contact with the thermal silicon oxide film was formed. The results are shown in FIG7 .

As shown in FIG7 , with respect to the fixed charge density of the thermally oxidized silicon film measured before ion implantation (about 3×10 ¹¹ /cm ² ), in the sample with a metal layer in which ions were implanted (ion species: N ⁺ ) via an Al film (10 nm) as a metal layer, a balance between the implanted ions and the defects was achieved and no significant change in the fixed charge was observed. On the other hand, in the sample without a metal layer in which the thickness of the metal layer was sufficiently reduced (here, 0 nm), an increase in positive fixed charge was observed after ion implantation. It is generally known that defects in silicon oxide show positive fixed charge, so it is believed that by reducing the thickness of the metal layer, the number of defects generated in the silicon oxide film during ion implantation increases, thereby increasing the positive charge. Based on the results, it can be confirmed that by changing the thickness of the metal layer during ion implantation, positive fixed charge is manifested in the silicon oxide film and its fixed charge density can be controlled.

In addition, according to the depth distribution of implanted ions shown in Fig. 6, light elements penetrate deeper than heavy elements, and penetrate deeply in the order of N ⁺ , O+, and Ar ⁺ . In Fig. 7, it can be considered that the reason is that the fixed charge density of the silicon oxide film is different depending on the type of implanted ions.

Based on the above results, it can be confirmed that the positive fixed charge density (or charge amount) formed in the silicon oxide film can be controlled by the thickness of the metal layer and the type and amount of ions injected. In addition, it can be confirmed that by making the thickness of the silicon oxide film sufficiently larger than the ion injection depth, additional functions can be added without damaging the function as an insulating film.

Industrial Applicability

According to the fixed charge developing method of the present invention, necessary fixed charges can be efficiently generated in an insulating film on the back channel side used in a semiconductor element while suppressing degradation of film quality.

Claims (11)

1. A method for developing fixed charges, which is a method for developing fixed charges in an insulating film on the back channel side of a top-gate semiconductor element having a channel layer including an oxide semiconductor and a gate insulating layer, wherein: After the insulating film is formed on a substrate, a metal film is formed on a surface of the insulating film, and ions are implanted into the insulating film through the metal film, thereby generating fixed charges in the insulating film. 2 . The fixed charge developing method according to claim 1 , wherein an average range of ions based on the ion implantation is greater than a thickness of the metal film and smaller than a sum of a thickness of the metal film and a thickness of the insulating film. 3 . The fixed charge developing method according to claim 2 , wherein a sum of an average range of the ions and a standard deviation thereof is smaller than a sum of a thickness of the metal film and a thickness of the insulating film. 4 . The fixed charge developing method according to claim 1 , wherein the insulating film is a silicon oxide film or a silicon oxynitride film. 5 . The fixed charge developing method according to claim 1 , wherein the metal film comprises aluminum, an aluminum alloy, molybdenum, a molybdenum alloy, titanium or a titanium alloy. The fixed charge developing method according to claim 1 , wherein the ion species implanted by the ion implantation is at least one selected from O, N, C atomic ions, O ₂ , N ₂ , C ₂ molecular ions, or Ar rare gas ions. 7. A method for manufacturing a thin film transistor, which is a method for manufacturing a top-gate thin film transistor, the method for manufacturing a thin film transistor comprising: A step of forming a fixed charge layer having fixed charges on the surface of the substrate; forming a channel layer including an oxide semiconductor on a surface of the fixed charge layer; and forming a gate insulating layer on the surface of the channel layer, The process of forming the fixed charge layer comprises: forming a first insulating film on the surface of the substrate; forming a metal film on a surface of the first insulating film; and A step of implanting ions into the first insulating film via the metal film. 8 . The method for manufacturing a thin film transistor according to claim 7 , wherein the step of forming the fixed charge layer includes the step of forming a second insulating film on a surface of the metal film after ion implantation into the first insulating film. 9 . The method for manufacturing a thin film transistor according to claim 8 , wherein the second insulating film is a stacked film of a silicon nitride film and a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. 10 . The method for manufacturing a thin film transistor according to claim 8 , wherein a thickness of the second insulating film is greater than or equal to 50 nm and less than or equal to 200 nm. 11. A thin film transistor, which is a top-gate thin film transistor in which a fixed charge layer having fixed charges, a channel layer including an oxide semiconductor, and a gate insulating layer are sequentially stacked on a substrate, wherein: The fixed charge layer includes an insulating film formed on the substrate and a metal film formed on a surface of the insulating film. Elements added by ion implantation are distributed in the insulating film and the metal film. A maximum value of distribution of the element in the insulating film is greater than an average value of distribution of the element in the metal film.