CN222547914U

CN222547914U - Semiconductor devices and HEMT devices

Info

Publication number: CN222547914U
Application number: CN202420467798.XU
Authority: CN
Inventors: F·尤科纳洛; A·康斯坦特; C·特林加利; M·E·卡斯塔尼亚
Original assignee: Italian Semiconductor International Co
Current assignee: Italian Semiconductor International Co
Priority date: 2023-03-10
Filing date: 2024-03-11
Publication date: 2025-02-28
Anticipated expiration: 2034-03-11

Abstract

The utility model relates to a semiconductor device and a HEMT device. The HEMT device comprises a semiconductor body with a semiconductor heterostructure; a control region comprising a semiconductor material, the control region being located on the semiconductor body, the control region having a top surface and a plurality of lateral sides; a control terminal of a conductive material, which extends on the top surface of the control region and contacts the top surface of the control region; a passivation layer of a non-conductive material, the passivation layer extending on the semiconductor body, partially on the top surface of the control region and on the plurality of lateral sides of the control region, the passivation layer being arranged laterally and being at a certain distance from the control terminal; and a plurality of spacer regions of a non-conductive material, the plurality of spacer regions extending between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions. The utility model is used in the field of integrated circuits, and the technical effect is that the leakage of the gate is reduced.

Description

Semiconductor device and HEMT device

Technical Field

The present disclosure relates to High Electron Mobility Transistor (HEMT) devices with reduced gate leakage.

Background

It is well known that the possibility of HEMT devices, commonly referred to as Heterostructure Field Effect Transistors (HFETs), operating at high voltages due to their high breakdown voltage and high carrier density and mobility are widely used in high power and fast switching applications.

In HEMT devices, a semiconductor heterostructure (typically based on AlGaN/GaN layers) allows spontaneous generation of so-called two-dimensional electron gas (2 DEG) in the device, forming a channel path for charge. The spontaneous channel may be modulated by applying a suitable voltage at the gate region above the channel path.

AlGaN/GaN HEMTs are typically depletion mode. For practical applications, however, enhancement mode (normally-off) devices are preferred to achieve safe operation and simplified drive circuitry.

Several implementations have been proposed of normally-off HEMTs based on AlGaN/GaN layers, including forming recessed gate transistors, performing fabrication steps such as incorporating fluorine plasma under the gate, or forming the gate region of pGaN. The last solution is for example used in products available on the market and considered hereinafter.

For example, fig. 1 shows a HEMT device 1 formed on a semiconductor body 2, where the semiconductor body 2 comprises a substrate layer 3, a first layer 4 and a second layer 6 (hereinafter also referred to as channel layer 4 and barrier layer 6).

The substrate layer 3 may include a silicon substrate and a gallium nitride (GaN) buffer layer, which are not separately shown in fig. 1.

The channel layer 4 is a first semiconductor material such as, for example, a first semiconductor alloy of a group III-V element of the periodic table, for example, the channel layer 4 may be gallium nitride (GaN).

The barrier layer 6 covers the channel layer 4 and is in direct contact with the channel layer 4 and is a second semiconductor material, such as, for example, a second semiconductor alloy of a group III-V element of the periodic table that is different from the first semiconductor alloy. For example, the barrier layer 6 may be aluminum gallium nitride (AlGaN).

The channel layer 4 and the barrier layer 6 are for example N-type.

A gate region 7 of conductive material extends over the barrier layer 6. The gate region 7 is formed, for example, of a third semiconductor material, such as, for example, a third semiconductor alloy of an element of groups III-V of the periodic table, where in more detail the gate region 7 is formed of gallium nitride (pGaN) of the P conductivity type.

The passivation layer 8 covers the top surface of the barrier layer 6, as well as the lateral surfaces ("sidewalls"), transverse to the gate region 7 and partially covers the top surface of the gate region 7. The passivation layer 8 is formed of a layer of non-conductive material, for example an oxide such as Al ₂O₃.

A first insulating layer 9, for example of silicon oxide, extends over the passivation layer 8.

An opening 11 extends through the first insulating layer 9 and the passivation layer 8 on top of the gate region 7, and a gate metal region 10, e.g. TiN/AlCu/TiN, extends in the opening 11 in direct electrical contact with the gate region 7 and extends partly over the first insulating layer 9.

A second insulating layer 12, for example of silicon oxide, extends over the first insulating layer 9 and the gate metal region 10.

In fig. 1, a field plate 13 of electrically conductive material extends over the first insulating layer 9, transversely to the gate metal region 10 and below the second insulating layer 12. The field plate 13 is optional and may be formed from the same metal layer as the gate metal region 10.

A source metal region 15, for example Ti/AlCu/TiN, extends over the barrier layer 6 and is in direct electrical contact with the barrier layer 6, the source metal region 15 also extending laterally to the second insulating layer 12 and over the second insulating layer 12. In the HEMT device 1, the source metal region 15 has a portion extending above the gate metal region 10 and above the field plate region 13, and has a shielding function.

A drain metal region 16, for example Ti/AlCu/TiN, extends over the barrier layer 6 and is in direct electrical contact with the barrier layer 6, and in addition the drain metal region 16 extends laterally to the second insulating layer 12 and extends partially over the second insulating layer 12 (on the opposite side of the gate region 7 relative to the source metal region 15).

In HEMT transistors of this type, etching of the layers above the semiconductor body 2 is critical and may affect the electrical properties of the device, such as the threshold voltage.

In fact, the threshold voltage of the HEMT device is affected by any gate leakage that occurs, in particular, on the sidewalls of the gate region 7 and may shift during stress conditions, typically, the negative shift in threshold voltage results from the high drain gate region 7. On the other hand, the low drain gate region 7 causes a positive shift in threshold voltage. In commercial devices, it is desirable to trade off between positive and negative offset.

The gate leakage exhibits bulk (bulk) and parasitic contributions during device operation (i.e., when the control voltage applied to the gate terminal is greater than zero).

In particular, parasitic contributions originate on the top surface of the gate region 7 (i.e. on the portion where no schottky contact is present between the gate metal region 10 and the gate region 7) and on the sidewalls of the gate region 7.

Parasitic gate leakage through the top surface of the pGaN material is due to the presence of electron surface states caused by polarized net charges, which is inherent when stacking GaN-AlGaN-pGaN layers for HEMT transistors of the type under consideration.

Instead, parasitic gate leakage through the sidewalls of the gate region 7 depends on the process and is in particular due to etching conditions in terms of the chemistry and the power employed for the pGaN layer when forming the gate region 7. In detail, damage caused by etching may cause formation of vacancies, such as nitrogen vacancies, resulting in capturing a high concentration of electrons at the sidewalls of the gate region 7. Thereby forming a current leakage path from the lower edge of the gate metal region 10 along the sidewalls of the gate region 7 to the barrier layer 6 and the channel layer 4 (i.e., to the channel region of the HEMT device 1 in the operating state of the HEMT device 1). In other words, pGaN etching may cause depletion of the surface side of the gate region 7, and thus, when a 2DEG is formed at the interface between the channel layer 4 and the barrier layer 6 (when the HEMT device 1 is on), an inversion channel is formed on the sidewall of the gate region 7.

The bulk gate leakage contribution is mainly affected by the damage to the gate region 7 during formation of the gate metal region 10 by etching, e.g. due to partial removal or roughness of the pGaN material, and the concentration of dopant ions (such as magnesium) defining the p-type doping of the GaN material forming the gate region 7.

Surface passivation of the barrier layer 6 and gate region 7 by atomic layer deposition ("ALD") of ammonium hydroxide resistant material, such as Al ₂O₃ or AlN, as done by the passivation layer 8, is a known solution that attempts to compensate for the presence of electronic surface states and defects caused by pGaN etching.

Disclosure of utility model

Applicant has demonstrated that the deposition of such layers is not always sufficiently effective to significantly reduce gate leakage. Furthermore, in some cases, such surface passivation may be arranged to introduce deleterious effects, thereby affecting other electrical characteristics of the transistor, namely the dielectric parameters (e.g., thickness and material) of the passivation layer 8 affecting the gate leakage and on-resistance Ron of the device in an opposite manner, and thus, such that an optimum value of gate leakage reduction may result in deterioration of the on-resistance Ron.

It is therefore an object of the present disclosure to overcome the disadvantages and limitations of the prior art.

According to the present disclosure, a HEMT device is provided comprising a semiconductor body having a semiconductor heterostructure, a control region comprising a semiconductor material, the control region being located on the semiconductor body, the control region having a top surface and a plurality of lateral sides, a control terminal of a conductive material, the control terminal extending on and in contact with the top surface of the control region, a passivation layer of a non-conductive material, the passivation layer extending on the semiconductor body, partially on the top surface of the control region, and on the plurality of lateral sides of the control region, the passivation layer being laterally disposed and a distance from the control terminal, and a plurality of spacer regions of a non-conductive material, the plurality of spacer regions extending between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions.

Preferably, the plurality of spacer regions are thicker than the passivation layer.

Preferably, the control terminal includes a narrow portion extending between the plurality of spacer regions and an upper portion extending over the plurality of spacer regions.

Preferably, the HEMT device further comprises an insulating structure extending over the passivation layer, wherein a control opening extends in the insulating structure and through the passivation layer and at least partially accommodates the control terminal and the plurality of spacer regions, the control opening having lateral sides, the plurality of spacer regions extending over the plurality of lateral sides of the control opening.

Preferably, the insulating structure comprises a first insulating layer extending over a passivation layer, and a second insulating layer extending over the first insulating layer, and wherein the control opening extends through the first insulating layer and the passivation layer and accommodates the plurality of spacer regions and at least partially accommodates the control terminal, the second insulating layer extending over the control terminal.

Preferably, the insulating structure comprises a first insulating layer extending over a passivation layer and a second insulating layer extending over the first insulating layer, and wherein the control opening extends through the first insulating layer, the second insulating layer and the passivation layer and accommodates the plurality of spacer regions and the control terminal.

Preferably, the HEMT device further comprises a field plate, and the field plate is located between the first insulating layer and the second insulating layer.

Preferably, the HEMT device further comprises a first current conducting terminal and a second current conducting terminal, the first current conducting terminal and the second current conducting terminal being located partially between the first insulating layer and the second insulating layer, the first current conducting terminal and the second current conducting terminal being in contact with the semiconductor body.

Preferably, the HEMT device further comprises a first current conducting terminal and a second current conducting terminal, the first and second current conducting terminals being located partially above the first and second insulating layers, the first and second current conducting terminals being in contact with the semiconductor body, the first current conducting terminal being located partially above the control terminal and the field plate.

Preferably, the insulating structure and the plurality of spacer regions are of different, selectively etchable materials.

Preferably, the insulating structure is silicon oxide and the plurality of spacer regions is silicon nitride.

Preferably, the control region includes a channel modulation region and an interlayer region covering the channel modulation region.

According to the present disclosure there is also provided a device comprising a semiconductor heterostructure, a control region on the heterostructure, the control region having a first surface and a plurality of sides, terminals on and in contact with the first surface of the control region, a passivation layer on the heterostructure, the first surface of the control region and the plurality of sides of the control region, the passivation layer having a second surface transverse to the first surface, and a plurality of non-conductive spacer regions between the terminals and the passivation layer, the second surface of the passivation layer being in contact with the plurality of spacer regions.

Preferably, the device further comprises a first insulating layer on the passivation layer, a second insulating layer on the first insulating layer, the first insulating layer and the second insulating layer contacting the plurality of spacer regions at the second surface, and a field plate between the first insulating layer and the second insulating layer.

The utility model has the technical effect of reducing the gate leakage of the HEMT device.

Drawings

For an understanding of the present disclosure, embodiments thereof will now be described, purely by way of non-limiting example, with reference to the accompanying drawings, in which:

Fig. 1 is a cross-section of a known HEMT device;

fig. 2 is a cross-section of a HEMT device according to an embodiment;

Fig. 3A-3F are cross-sections of a semiconductor wafer in subsequent manufacturing steps of the HEMT device of fig. 2;

fig. 4 is a cross-section of a HEMT device according to another embodiment;

Fig. 5A-5C are cross-sections of a semiconductor wafer in a subsequent manufacturing step of the HEMT device of fig. 4, and

Fig. 6 and 7 are cross-sections of HEMT devices according to various embodiments.

Detailed Description

The following description refers to the arrangement shown in the drawings, and thus, expressions such as "above," "below," "upper," "lower," "top," "bottom," "right," "left," etc., are relative to the drawings and should not be construed as limiting.

Fig. 2 shows a HEMT device 50 comprising a semiconductor body 52 here formed by a substrate layer 53, a channel layer 54 and a barrier layer 56.

The substrate layer 53 may include a silicon substrate and a gallium nitride (GaN) buffer layer, which are not separately shown in fig. 2.

The channel layer 54 is a first semiconductor material, such as a first semiconductor alloy of elements of groups III and V of the periodic table, for example, the channel layer 54 may be gallium nitride (GaN).

The barrier layer 56 covers the channel layer 54 and is in direct contact with the channel layer 54 and is a second semiconductor material, such as a second semiconductor alloy of a periodic table group III-V element, different from the first semiconductor alloy. For example, the barrier layer 56 may be aluminum gallium nitride (AlGaN).

The channel layer 54 and the barrier layer 56 are, for example, N-type.

A gate region 57 of conductive material extends over the barrier layer 56 and contacts the barrier layer 56. The gate region 57 is a control region, and specifically a channel modulation region.

In a manner not shown, the gate region 57 is strip-shaped and extends along a first horizontal axis Y of the cartesian reference system XYZ. The gate region 57 is formed of a conductive material, typically a doped third semiconductor material, such as a third semiconductor alloy of a group III-V element of the periodic table, in particular, where the gate region 57 is formed of P conductivity type gallium nitride (pGaN).

The gate region 57 is used to modulate the thickness of the channel formed at the interface between the channel layer 54 and the barrier layer 56 based on the voltage applied thereto, as known to those skilled in the art.

Passivation layer 58 covers the top surface of barrier layer 56, as well as the lateral surfaces (also indicated as sidewalls of gate region 57), and partially covers the top surface of gate region 57. Similar to the gate region 57, the passivation layer 58 also extends along the first horizontal axis Y for the entire length of the gate region 57.

Passivation layer 58 is a non-conductive material, e.g., an oxide such as Al ₂O₃、AlN、SiN、HfO₂、SiO₂, alSiO, with a thickness between 2nm and 10nm, e.g., 5nm.

A first insulating layer 66, such as silicon oxide, extends over passivation layer 58.

A gate opening 67 extends through the first insulating layer 66 and the passivation layer 58 on top of the gate region 57.

Spacer region 62 extends in gate opening 67, on a lateral side of gate opening 67, on a top surface of gate region 57, and is in direct contact with the top surface of gate region 57.

The spacer region 62 is here band-shaped and extends along the first horizontal axis Y. In effect, spacer region 62 laterally defines a spacer opening 71 that is narrower than gate opening 67.

The spacer region 62 is here a dielectric material such as silicon nitride ("SiN"), for example Si ₃N₄ in its stable configuration. The dielectric material of the spacer region 62 may be an oxide, but is typically a different material than the first insulating layer 66.

A control terminal (hereinafter indicated as gate metal region 68, e.g., a multilayer of TiN/AlCu/TiN) is in direct electrical contact with a central portion of the gate region 57, extending in the spacer opening 71, over the spacer region 62 and partially over the first insulating region 66.

In effect, the gate metal region 68 includes a narrow portion 68A extending between the spacer regions 62 and an upper portion 68B extending over the spacer regions 62.

In other words, in the embodiment of fig. 2, spacer region 62 extends below gate metal region 68 and is adjacent to two opposite sides of narrow portion 68A.

Other materials such as Ti, ta, tiW, taW may be used in place of TiN for the alloy of gate metal region 68.

The narrowed portion 68A of the gate metal region 68 and the gate region 57 form a schottky contact.

A second insulating layer 69, such as silicon oxide, extends over the first insulating layer 66 and the gate metal 68.

The first insulating layer 66 and the second insulating layer 69 form insulating structures 66, 69. The insulating structures 66, 69 have first and second current conducting openings, hereinafter indicated as source opening 82 and drain opening 83, respectively, extending on different sides of the gate region 57. The source opening 82 and the drain opening 83 extend through the entire thickness of the insulating structures 66, 69 and expose the barrier layer 56.

In fig. 2, a field plate 70 extends on the first insulating layer 66, on the side below the second insulating layer 69, but at a distance from the gate metal region 68. The field plate 70 is optional and may be formed from the same metal layer as the gate metal region 68.

A first current conducting terminal (hereinafter indicated as source metal region 72 of e.g. Ti/AlCu/TiN) extends in the source opening 82 and is here in direct electrical contact with the barrier layer 56. In the HEMT device 50, the source metal region 72 has a portion that also extends over the second insulating layer 69, over the gate metal 68, and over the field plate 70, and has a shielding function.

Source metal region 72 may be electrically connected to field plate 70.

A second current conducting terminal (hereinafter indicated as drain metal region 73 of e.g. Ti/AlCu/TiN) extends in the drain opening 83 and is here in direct electrical contact with the barrier layer 56. Drain metal region 73 is located on the opposite side of gate region 57 from source metal region 72.

The HEMT device 50 of fig. 2 has improved performance in reducing lateral gate leakage from the pGaN sidewalls of the gate region 57.

In more detail, with the structure of fig. 2, spacer region 62 is interposed between gate metal region 68 and passivation layer 58, separating them and preventing any current leakage path from the lower edge of gate metal region 68 along the top surface and sidewalls of gate region 57 to the channel region of HEMT device 50 formed during operation.

Thus, during device operation, the gate current is forced to flow only in a local (here central) portion of the upper surface of the gate region 57, i.e. only at the schottky contact between the gate metal region 68 and the gate region 57.

The HEMT device 50 thus allows a good compromise to be obtained between gate current, threshold voltage and on-resistance.

HEMT device 50 may be fabricated as shown in fig. 3A-3F, with fig. 3A-3F showing the wafer prior to dicing and using the same reference numerals as the areas of the same name in fig. 2.

Fig. 3A shows a wafer 80 comprising a layer stack comprising a substrate layer 53, a channel layer 54 and a barrier layer 56. The gate region 57 has been formed on the barrier layer 56, for example, by epitaxial growth of p-doped GaN material using MOCVD (metal organic chemical vapor deposition) and defined by its photolithography, using a standard etching process.

In fig. 3B, a passivation layer 58 is formed on the exposed gate region 57 and the blocking layer 56, and then a first insulating layer 66 is formed.

For example, passivation layer 58 is thermally deposited or plasma deposited in an H ₂ O-based environment at 300 ℃ using ALD (atomic layer deposition) techniques, for example, to a thickness of 5 nm.

The first insulating layer 66 may be deposited, for example, by PECVD (plasma enhanced chemical vapor deposition) in an SiH ₄ -based environment to a thickness of, for example, 260 nm.

In fig. 3C, first insulating layer 66 and passivation layer 58 are etched using a mask (not shown) to form gate openings 67, thereby exposing the top surfaces of gate regions 57. The etch to form gate opening 67 may be, for example, a time etch in CF ₄ or an endpoint detection using a process to remove first insulating layer 66, as well as a BCl ₃ etch to remove passivation layer 58.

Depending on the width of the gate region 57, the gate opening 67 may have a width along the second horizontal axis X of the cartesian reference system XYZ, for example between 0.9 μm and 5.5 μm.

In fig. 3D, a sacrificial layer 81 of dielectric material is formed on the first insulating layer 66 and in the gate opening 67, on the portion of the gate region 57 exposed by the gate opening 67.

The sacrificial layer 81 is deposited, for example, by PECVD, to a thickness of 300 nm.

In fig. 3E, sacrificial layer 81 is anisotropically (dry) etched without a mask (e.g., in a CF ₄ environment) until it reaches a central portion of the top surface of gate region 57, thereby defining spacer openings 71 within gate openings 67 and forming spacer regions 62. The sacrificial layer 81 is also removed from the top of the first insulating layer 66 (outside the gate opening 67).

Accordingly, the spacer region 62 may have a width of about 300nm near the bottom of the gate region 57, and the spacer opening 71 may have a width between 0.3 μm and 5 μm near the bottom of the gate region 57.

In this embodiment, the spacer region 62 has the same thickness as the portion of the first insulating layer 66 above the gate region 57, but this is not critical.

In fig. 3F, a gate metal layer is deposited and defined to form a gate metal region 68 (extending in spacer opening 71 and partially over first insulating region 66) and a field plate 70 (extending laterally thereto).

Then, in a manner not shown, a second insulating layer 69 is deposited, and then the second insulating layer 69 is defined (using a mask not shown) together with the first insulating layer 66 and the passivation layer 58 to form a source opening 82 and a drain opening 83. Thereafter, a source/drain metal layer is deposited and defined to form source metal regions 72 and drain metal regions 73.

A final fabrication step is then performed, including depositing an outer passivation layer (not shown), forming open contacts (not shown), and dicing the wafer 80, thereby obtaining the HEMT device 50 of fig. 2.

In effect, in the process described above, spacer region 62 is formed after forming gate opening 67 to prevent lateral leakage from gate region 57, thereby isolating gate metal region 68 from passivation layer 58.

Fig. 4 shows a HEMT device 100 in which the source and drain metal regions are formed before the gate metal region.

In detail, in fig. 4, wherein regions common to the HEMT device 50 of fig. 2 have been indicated with the same reference numerals, the source opening, here indicated by 82', and the drain opening, here indicated by 83', extend only through the first insulating layer 66. In addition, a gate opening, here indicated by 67', extends through the first insulating layer 66 and the second insulating layer 69.

Similarly, in this embodiment, the spacer openings, here indicated by 71', and the spacer regions, here indicated by 62', extend through the entire insulating structure 66, 69.

The shielding region 86 may be electrically coupled to other regions in the substrate 52 by forming one or more vias through the first insulating layer 66 and the second insulating layer 69 in locations not shown in fig. 4.

The HEMT device 100 may be fabricated as shown in fig. 5A-5C.

In detail, in fig. 5A, after the first insulating layer 66 (fig. 3B) is formed, the first insulating layer 66 is defined to form the source opening 82 'and the drain opening 83'. The source metal region 72', the drain metal region 73' and the field plate 70 are then formed by depositing and defining the same metal layer or stack of layers, such as Ti/AlCu/TiN.

In fig. 5B, a second insulating layer 69 (along with first insulating layer 66 and passivation layer 58) is deposited and etched to form gate openings 67'.

Then, in fig. 5C, similar to fig. 3D, a sacrificial layer 81 is deposited on the second insulating layer 69 and in the gate opening 67'.

After blanket etching and final fabrication steps of the sacrificial layer 81, for the embodiment of fig. 2, the HEMT device 100 of fig. 4 is obtained.

In particular, as shown in fig. 4, when forming a gate metal region, here indicated by 68', in the spacer opening 71' (e.g., by depositing and defining a metal layer or stack, such as Ti/AlCu/TiN), the shielding region 86 may be formed from the same metal layer as the gate metal 68 '.

Fig. 6 relates to a different embodiment, wherein regions common to the HEMT device 50 of fig. 2 have been designated with the same reference numerals. In fig. 6, the HEMT device 200 has a gate region 57' including a channel modulation region 90 (of pGaN material) and an interlayer region 59.

The channel modulation region 90 has the same structure and electrical characteristics as the gate region 57 of fig. 2.

An interlayer region 59 of conductive material (e.g., a metal such as TiN) extends along a second horizontal axis X of the cartesian reference system XYZ on top of the channel modulation region 90 and may be narrower than the channel modulation region 90.

Further, interlayer region 59 is in direct electrical contact with gate metal region 68 at spacer opening 71 and extends under spacer region 62.

Similar to passivation layer 58, passivation layer 58' covers the portion of the top surface of inter-layer region 59 under first insulating layer 66, the lateral surfaces of inter-layer region 59, the edges of the top surface of channel modulation region 90, the sidewalls of channel modulation region 90, and the top surface of barrier layer 56.

Thus, also in the HEMT device 200 of fig. 6, the passivation layer 58 'extends at a distance from the gate region 57'.

The interlayer region 59 serves to facilitate the turning on of the channel modulation region 90 and to form a barrier to the diffusion of contaminants of the upper layers.

Fig. 7 relates to another embodiment wherein the HEMT device 300 includes an interlayer region 59 (as described with reference to fig. 6) and wherein the source and drain metal regions are formed before the gate metal region (as described with reference to fig. 4). In fig. 7, regions common to the HEMT device 100 of fig. 4 and regions common to the HEMT device 200 of fig. 6 have been designated with the same reference numerals.

The interlayer region 59 has similar locations and features as the corresponding region shown in fig. 6.

Finally, it is apparent that numerous variations and modifications may be made to the HEMT device and process described and illustrated herein, all of which fall within the scope of the present disclosure as defined.

In summary, example embodiments of the disclosure are as follows.

Example 1. A HEMT device (50; 100;200; 300) includes:

A semiconductor body (52) having a semiconductor heterostructure (54, 56);

a control region (57; 57 ') comprising a semiconductor material arranged on the semiconductor body (52), the control region (57; 57') having a top surface and lateral sides;

A control terminal (68; 68 ') of electrically conductive material extending over and in contact with the top surface of the control region (57; 57'), and

A passivation layer (58; 58 ') of non-conductive material extending over the semiconductor body (52), partially over a top surface of the control region (57; 57 ') and over lateral sides of the control region (57; 57 ');

The passivation layer (58; 58 ') is arranged laterally and at a distance from the control terminal (68; 68').

Example 2. The HEMT device of example 1, further comprising a spacer region (62; 62 ') of non-conductive material extending between the control terminal (68; 68 ') and the passivation layer (58; 58 ').

Example 3. HEMT device according to the previous example, wherein the control terminal (68; 68 ') comprises a narrow portion (68A) extending between the spacer regions (62; 62') and an upper portion (68B) extending over the spacer regions.

Example 4. The HEMT device of example 2 or 3, further comprising an insulating structure (66, 69) extending over the passivation layer (58; 58 '), wherein a control opening (67; 67 ') extends in the insulating structure (66, 69) and through the passivation layer (58; 58 ') and at least partially accommodates the control terminal (68; 68 ') and the spacer region (62; 62 '), the control opening having a lateral side, the spacer region (62; 62 ') extending on the lateral side of the control opening (67; 67 ').

Example 4bis. The HEMT device according to any preceding example, further comprising a first current conducting opening (82; 82 ') at least partially accommodating a first current conducting terminal (72; 72') of a conductive material, and

A second current conducting opening (83; 83 ') at least partially receiving a second current conducting terminal (73; 73') of electrically conductive material.

Example 5. HEMT device according to the previous example, wherein the insulating structure (66, 69) comprises a first insulating layer (66) extending over the passivation layer (58; 58 ') and a second insulating layer (69) extending over the first insulating layer, and wherein the control opening (67) extends through the first insulating layer (66) and the passivation layer (58; 58') and accommodates the spacer region (62) and at least partially accommodates the control terminal (68), the second insulating layer (69) extending over the control terminal (68).

Example 6. The HEMT device of example 4, wherein the insulating structure (66, 69) comprises a first insulating layer (66) extending over the passivation layer (58; 58 ') and a second insulating layer (69) extending over the first insulating layer (66), and wherein the control opening (67') extends through the first and second insulating layers (66, 69) and the passivation layer (58; 58 ') and accommodates the spacer region (62') and the control terminal (68).

Example 7. The HEMT device of any of examples 4-6, wherein the insulating structure (66, 69) and the spacer region (62; 62') are different, selectively etchable materials.

Example 8. HEMT devices according to the previous examples wherein the insulating structure (66, 69) is silicon oxide and the spacer region (62; 62') is silicon nitride.

Example 9. The HEMT device according to any of the preceding examples, wherein the control region (57') comprises a channel modulation region (90) and an interlayer region (59) covering the channel modulation region.

Example 10. A process for manufacturing a HEMT device (50; 100;200; 300), the process comprising:

forming a control region (57; 57 ') on the semiconductor body (52) with the semiconductor heterostructure (54, 56), the control region (57; 57 ') comprising semiconductor material and being arranged on the semiconductor body (52), the control region (57; 57 ') having a top surface and lateral sides;

Forming a passivation layer (58; 58 ') of non-conductive material on the semiconductor body (52), partly on the top surface of the control region (57; 57 ') and on the lateral sides of the control region (57; 57 ')

On the top surface of the control region (57; 57 ') and in contact therewith, transversely and at a distance from the passivation layer (58; 58 '), a control terminal (68; 68 ') of electrically conductive material is formed.

Example 11. The process according to the preceding example further comprises forming a spacer region (62; 62 ') of non-conductive material extending between the control terminal (68; 68') and the passivation layer (58; 58 ') prior to forming the control terminal (68; 68').

Example 12. The process according to the preceding example, wherein:

forming the passivation layer (58; 58') and forming the spacer region (62) includes:

Forming a portion of a passivation layer (58; 58 ') covering a top surface of the gate region (57; 57');

Forming an insulating layer (66; 69) over the passivation layer (58; 58');

Forming a control opening (67; 67') in the insulating layer (66; 69), including selecting

Removing said portion of the passivation layer (58; 58') and

Transverse to the control opening (67; 67'); on the sides, spacer regions (62;

62'), and

Forming the control terminals (68; 68 ') includes forming a portion of the control terminals in the control openings (67; 67 '), between the spacer regions (62; 62 '), and on.

Example 13. According to the process of the foregoing example,

Wherein forming the spacer region (62; 62') comprises:

Forming a sacrificial layer (81) on the insulating layer (66; 69) and in the control opening (67; 67'), and

The sacrificial layer (81) is removed from the insulating layer (66; 69) and the control opening (67; 67'), except on the lateral sides of the control opening.

Example 14. The process according to the previous example, wherein the insulating layer is a first insulating layer (66), the process further comprising:

after forming the control terminal (68), forming a second insulating layer (69);

Forming first and second current conducting openings (82, 83) through the first and second insulating layers (66, 69) and the passivation layer (58; 58 ') on first and second sides of the control region (57; 57'), respectively, and

A first current-conducting terminal (72) extending at least partially in the first current-conducting opening (82) and a second current-conducting terminal (73) extending at least partially in the second current-conducting opening (83) are formed, the first and second current-conducting terminals (72, 73) being in contact with the semiconductor body (52).

Example 15. The process of example 13, further comprising a first insulating layer (66), wherein the insulating layer is a second insulating layer (69), the control opening (67') extending through both the first and second insulating layers (66, 69), the process further comprising:

After forming the first insulating layer (66), forming first and second current conducting openings (82 ', 83') through the first insulating layer (66) and the passivation layer (58; 58 ') on the first and second sides, respectively, of the control region (57; 57')

A first current-conducting terminal (72 ') extending at least partially in the first current-conducting opening (82 ') and a second current-conducting terminal (73 ') extending at least partially in the second current-conducting opening (83) are formed, the first and second current-conducting terminals being in contact with the semiconductor body (52).

A HEMT device (50; 100;200; 300) may be summarized as including a semiconductor body (52) having a semiconductor heterostructure (54, 56), a control region (57; 57 ') disposed on the semiconductor body (52) comprising a semiconductor material, the control region (57; 57 ') having a top surface and lateral sides, a control terminal (68; 68 ') of a conductive material extending over and in contact with the top surface of the control region (57; 57 '), and a passivation layer (58; 58 ') of a non-conductive material extending over the semiconductor body (52), partially over the top surface of the control region (57; 57 ') and over the lateral sides of the control region (57; 57 '), the passivation layer (58; 58 ') being disposed laterally and at a distance from the control terminal (68; 68 ').

The HEMT device can also include a spacer region (62; 62 ') of non-conductive material extending between the control terminal (68; 68 ') and the passivation layer (58; 58 ').

Wherein the control terminal (68; 68 ') may include a narrow portion (68A) extending between the spacer regions (62; 62') and an upper portion (68B) extending over the spacer regions.

The HEMT device may further comprise an insulating structure (66, 69) extending over the passivation layer (58; 58 '), wherein a control opening (67; 67 ') extends in the insulating structure (66, 69) and through the passivation layer (58; 58 ') and at least partially accommodates the control terminal (68; 68 ') and the spacer region (62; 62 '), the control opening having lateral sides, the spacer region (62; 62 ') extending on the lateral sides of the control opening (67; 67 ').

Wherein the insulating structure (66, 69) may comprise a first insulating layer (66) extending over the passivation layer (58; 58 '), and a second insulating layer (69) extending over the first insulating layer (66), and wherein the control opening (67) may extend through the first insulating layer (66) and the passivation layer (58; 58') and accommodate the spacer region (62) and at least partially accommodate the control terminal (68), the second insulating layer (69) extending over the control terminal (68).

Wherein the insulating structure (66, 69) may comprise a first insulating layer (66) extending over the passivation layer (58; 58 ') and a second insulating layer (69) extending over the first insulating layer (66), and wherein the control opening (67') may extend through the first and second insulating layers (66, 69) and the passivation layer (58; 58 ') and accommodate the spacer region (62') and the control terminal (68).

Wherein the insulating structure (66, 69) and the spacer region (62, 62') may be of different, selectively etchable materials.

Wherein the insulating structure (66, 69) may be silicon oxide and the spacer region (62, 62') may be silicon nitride.

Wherein the control region (57') may include a channel modulation region (90) and an interlayer region (59) covering the channel modulation region.

A process for fabricating a HEMT device (50; 100;200; 300) may be summarized as including forming a control region (57; 57) on a semiconductor body (52) having a semiconductor heterostructure (54, 56), the control region (57; 57 ') comprising semiconductor material and being arranged on the semiconductor body (52), the control region (57; 57') having a top surface and lateral sides, forming a passivation layer (58; 58 ') of non-conductive material on the semiconductor body (52), partially on the top surface of the control region (57; 57') and on the lateral sides of the control region (57; 57 '), and forming a control terminal (68; 68') of conductive material on and in contact with the top surface of the control region (57; 57 '), laterally and at a distance from the passivation layer (58; 58').

The process may further include, prior to forming the control terminal (68; 68 '), forming a spacer region (62; 62') of non-conductive material extending between the control terminal (68; 68 ') and the passivation layer (58; 58').

Forming the passivation layer (58; 58 ') and forming the spacer region (62) may include forming a portion of the passivation layer (58; 58') covering a top surface of the gate region (57; 57 '), forming an insulating layer (66; 69) over the passivation layer (58; 58'), forming a control opening (67; 67 ') in the insulating layer (66; 69) including selectively removing the portion of the passivation layer (58; 58'), and forming a spacer region (62; 62 ') on a lateral side of the control opening (67; 67'), and forming the control terminal (68; 68 ') may include forming a portion of the control terminal in the control opening (67; 67'), between the spacer regions (62; 62 '), and over the spacer region (62; 62').

Wherein forming the spacer region (62; 62 ') may include forming a sacrificial layer (81) on the insulating layer (66; 69) and in the control opening (67; 67 '), and removing the sacrificial layer (81) from the insulating layer (66; 69) and the control opening (67; 67 '), except on lateral sides of the control opening.

Wherein the insulating layer is a first insulating layer (66), the process may further comprise forming a second insulating layer (69) after forming the control terminal (68), forming first and second current conducting openings (82, 83) through the first and second insulating layers (66, 69) and the passivation layer (58; 58 ') on first and second sides of the control region (57; 57'), respectively, and forming a first current conducting terminal (72) extending at least partially in the first current conducting opening (82) and a second current conducting terminal (73) extending at least partially in the second current conducting opening (83), the first and second current conducting terminals (72, 73) being in contact with the semiconductor body (52).

The process may further comprise a first insulating layer (66), wherein the insulating layer is a second insulating layer (69), the control opening (67 ') extending through the first and second insulating layers (66, 69), the process further comprising, after forming the first insulating layer (66), forming first and second current conducting openings (82 ',83 ') through the first insulating layer (66) and the passivation layer (58; 58 '), respectively, on first and second sides of the control region (57; 57 '), and forming first current conducting terminals (72 ') extending at least partially in the first current conducting openings (82 ') and second current conducting terminals (73 ') extending at least partially in the second current conducting openings (83 '), the first and second current conducting terminals being in contact with the semiconductor body (52).

The various embodiments described above may be combined to provide further embodiments. Aspects of the embodiments can be modified if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A HEMT device, the HEMT device comprising:

a semiconductor body having a semiconductor heterostructure;

A control region comprising a semiconductor material, the control region being located on the semiconductor body, the control region having a top surface and a plurality of lateral sides;

A control terminal of electrically conductive material extending over and in contact with a top surface of the control region;

A passivation layer of non-conductive material extending over the semiconductor body, partially over the top surface of the control region and over the plurality of lateral sides of the control region, the passivation layer being arranged laterally and at a distance from the control terminals, and

A plurality of spacer regions of non-conductive material extending between the control terminal and the passivation layer, the passivation layer not overlapping the plurality of spacer regions.

2. The HEMT device of claim 1, wherein the plurality of spacer regions have a thickness greater than the passivation layer.

3. The HEMT device of claim 2, wherein the control terminal comprises a narrow portion extending between the plurality of spacer regions and an upper portion extending over the plurality of spacer regions.

4. The HEMT device of claim 2, further comprising an insulating structure extending over the passivation layer, wherein a control opening extends in the insulating structure and through the passivation layer and at least partially accommodates the control terminal and the plurality of spacer regions, the control opening having lateral sides, the plurality of spacer regions extending over the plurality of lateral sides of the control opening.

5. The HEMT device of claim 4, wherein the insulating structure comprises:

A first insulating layer extending over the passivation layer, an

A second insulating layer extending over the first insulating layer, and

Wherein the control opening extends through the first insulating layer and the passivation layer and accommodates the plurality of spacer regions and at least partially accommodates the control terminal, the second insulating layer extending over the control terminal.

6. The HEMT device of claim 4, wherein the insulating structure comprises:

A first insulating layer extending over the passivation layer, an

A second insulating layer extending over the first insulating layer, and

Wherein the control opening extends through the first insulating layer, the second insulating layer, and the passivation layer and accommodates the plurality of spacer regions and the control terminal.

7. The HEMT device of claim 6, further comprising a field plate located between the first insulating layer and the second insulating layer.

8. The HEMT device of claim 7, further comprising a first current conducting terminal and a second current conducting terminal, the first current conducting terminal and the second current conducting terminal being partially located between the first insulating layer and the second insulating layer, the first current conducting terminal and the second current conducting terminal being in contact with the semiconductor body.

9. The HEMT device of claim 7, further comprising a first current conducting terminal and a second current conducting terminal, the first and second current conducting terminals are partially over the first and second insulating layers, the first and second current conducting terminals are in contact with the semiconductor body, the first current conducting terminal being located partially above the control terminal and the field plate.

10. The HEMT device of claim 6, wherein the insulating structure and the plurality of spacer regions are different, selectively etchable materials.

11. The HEMT device of claim 10, wherein the insulating structure is silicon oxide and the plurality of spacer regions are silicon nitride.

12. The HEMT device of claim 11, wherein the control region comprises a channel modulation region and an interlayer region that covers the channel modulation region.

13. A semiconductor device, comprising:

A semiconductor heterostructure;

A control region on the heterostructure, the control region having a first surface and a plurality of sides;

a terminal located on and in contact with the first surface of the control region;

A passivation layer on the heterostructure, on the first surface of the control region and on the plurality of sides of the control region, the passivation layer having a second surface transverse to the first surface, and

A plurality of non-conductive spacer regions between the terminals and the passivation layer, the second surface of the passivation layer being in contact with the plurality of spacer regions.

14. The semiconductor device according to claim 13, wherein the semiconductor device further comprises:

a first insulating layer on the passivation layer;

A second insulating layer on the first insulating layer, the first insulating layer and the second insulating layer being in contact with the plurality of spacer regions at the second surface, and

A field plate located between the first insulating layer and the second insulating layer.