CN117497412A - GaN-on-silicon HEMT device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a silicon-based gallium nitride HEMT device and a manufacturing method thereof, wherein P-GaN is arranged between a first ohmic metal corresponding to a drain electrode and a barrier layer, the P-GaN can increase the saturated output current of the device, the barrier layer is divided into a plurality of channels by etching the barrier layer, part of the barrier layer is etched, the rest of non-etched parts form the channels, the channels are not overetched, a gate electrode fully covers the channels, the device is changed into an enhanced device under the condition of not introducing other defects, and the C-doped GaN grows between a back barrier layer and a first buffer layer to prevent the bulk leakage current from entering a second buffer layer; and a back barrier layer is formed by growing AlGaN between the second buffer layer and the channel layer, so that a higher electron barrier is formed, electrons of the 2DEG are prevented from being captured and accumulated by deep-level impurities in the second buffer layer, the dynamic resistance of the device is reduced, and the occurrence of current collapse is avoided.

Description

GaN-on-silicon HEMT device and manufacturing method thereof

Technical field

The present invention relates to the technical field of semiconductor components, and in particular to a silicon-based gallium nitride HEMT device and a manufacturing method thereof.

Background technique

With the advancement and development of science and technology, high-frequency and high-power equipment such as smart grids, new energy vehicles, and military radars have put forward increasingly higher requirements for high-frequency and high-power devices. However, the original silicon-based materials and germanium-based materials are increasingly unable to meet the growing performance requirements due to their own material characteristics limitations. Therefore, it is necessary to use suitable semiconductor materials to develop higher frequency and higher power semiconductor devices. As a representative of the third generation semiconductor, gallium nitride (GaN), due to its excellent material properties, is suitable for preparing devices used in high-frequency, high-voltage and high-power scenarios. It can take advantage of the material advantages of gallium nitride and reduce the power consumption of power electronic devices. .

Traditional gallium nitride HEMT devices are depletion mode (normally open) devices, that is, their threshold voltage is negative when in the blocking state, which places high requirements on the drive circuit, so technicians usually use etching The barrier layer trench turns it into an enhancement device, which will introduce a large number of defects into the device and easily cause over-etching. On the other hand, GaN material will naturally appear as an N-type semiconductor during process growth, and its unintentional doping concentration is about 1×10e15 cm ^-3 ~ 1×10e16 cm ^-3 . Therefore, body leakage current will appear in the GaN buffer. In the layer, the main idea of the technical method to solve this excessive body leakage current is to realize a high-resistance GaN buffer layer. By controlling the ratio of Ga and N elements and the growth pressure for C doping, a high-resistance GaN buffer layer is obtained, and the device breakdown voltage exceeds 500V. However, C doping in principle introduces deep-level defects into the GaN buffer layer. When the device is in the on-state, the deep-level defects capture electrons and fail to release them in time, which increases the dynamic resistance of the device and causes current collapse.

Contents of the invention

The main purpose of the present invention is to provide a silicon-based gallium nitride HEMT device and a manufacturing method thereof, aiming to solve the problem of excessive defects introduced by existing silicon-based gallium nitride HEMT devices by etching barrier layer trenches, and at the same time, Using C-doped GaN as a buffer layer introduces deep-level defects, which increases the dynamic resistance of the device and easily causes current collapse.

In order to achieve the above objectives, the present invention provides a method for manufacturing a silicon-based gallium nitride HEMT device, which includes the following steps:

A substrate is provided, and a core layer, a first buffer layer and a second buffer layer are sequentially stacked on the substrate, wherein the substrate is an N-type Si substrate and the second buffer layer is C-doped. GaN buffer layer;

A layer of AlGaN is grown on the second buffer layer to form a back barrier layer, and a channel layer, an insertion layer and a barrier layer are sequentially stacked on the back barrier layer, wherein the channel layer is GaN Channel layer, the barrier layer is an AlGaN barrier layer;

Etching the outer edges of the channel layer, the barrier layer and the insertion layer to form an isolation region;

Deposit a layer of P-GaN on the barrier layer, and etch the P-GaN except for the first preset pattern to form a cap layer, wherein the first preset pattern is located on the barrier layer edge of one side;

A first ohmic metal is prepared on the cap layer, and a second ohmic metal is prepared on the other edge of the barrier layer, and a passivation layer is deposited on the barrier layer, wherein the passivation layer covering the first ohmic metal and the second ohmic metal;

Etching the passivation layer to form a gate contact area connected to the barrier layer, and etching along the second preset pattern on the barrier layer to form a channel area connected to the insertion layer, so as to causing the barrier layer to form a multi-stage channel, wherein the second preset pattern is provided corresponding to the gate contact area;

Deposit a gate dielectric on the passivation layer, and prepare a gate electrode on the gate dielectric, wherein the gate dielectric covers the channel area, and the gate electrode fully covers multiple sections of the channel. cover;

Deposit an oxide layer on the gate dielectric and prepare a source electrode and a drain electrode to obtain the silicon-based gallium nitride HEMT device, wherein the source electrode is in contact with the second ohmic metal, and the drain electrode is in contact with the second ohmic metal. The first ohmic metal contact.

Preferably, the step of providing a substrate and sequentially stacking and depositing a nucleation layer, a first buffer layer and a second buffer layer on the substrate includes:

Provides N-type Si substrates heavily doped with (111) crystal orientation;

Epitaxially grow a layer of AlN with a thickness of 0.1nm to 0.3nm on the substrate to form the nucleation layer;

Epitaxially growing AlGaN with a thickness of 0.5 μm to 2 μm on the nucleation layer to form the first buffer layer, wherein the Al concentration of AlGaN increases from the nucleation layer to a direction away from the nucleation layer;

C-doped GaN with a thickness of 2 μm to 4 μm is grown on the first buffer layer to form the second buffer layer.

Preferably, the step of growing a layer of AlGaN on the second buffer layer to form a back barrier layer, and sequentially stacking a channel layer, an insertion layer and a barrier layer on the back barrier layer includes:

Grow AlGaN with a thickness of 1 μm to 2 μm on the second buffer layer to form the back barrier layer;

Grow GaN with a thickness of 0.3 μm to 1 μm on the back barrier layer to form the channel layer;

Grow AlN with a thickness of 0.8nm to 1.2nm on the channel layer to form the insertion layer;

AlGaN with a thickness of 20 nm to 30 nm is grown on the insertion layer to form the barrier layer.

Preferably, the step of preparing a first ohmic metal on the cap layer and preparing a second ohmic metal on the other edge of the barrier layer, and depositing a passivation layer on the barrier layer includes :

Depositing ohm metal on the barrier layer, wherein the ohm metal is a stacked structure composed of Ti, Al, Ni and Ag, and the ohm metal covers the barrier layer and the cap layer;

The first ohmic metal and the second ohmic metal are formed from the ohm metal except the third preset pattern and the cap layer, wherein the third preset pattern is located away from the barrier layer One side edge of the cap layer;

SiN with a thickness of 75 nm to 125 nm is deposited on the barrier layer to form a passivation layer, where the passivation layer fills the isolation region.

Preferably, the passivation layer is etched to form a gate contact area connected to the barrier layer, and the barrier layer is etched along a second preset pattern to form a gate contact area connected to the insertion layer. The step of forming a channel region so that the barrier layer forms a multi-stage channel includes:

Etching the passivation layer at a first preset position of the passivation layer to form the gate contact area, wherein the gate contact area is rectangular;

Continue to etch downward along the gate contact area, and etch along a second preset pattern on the barrier layer to form the channel area, where the second preset pattern is a hexagon or an octagon.

Preferably, the steps of depositing a gate dielectric on the passivation layer and preparing a gate electrode on the gate dielectric include:

Deposit 1 nm to 10 nm thick HfO ₂ , La ₂ O ₃ or TiO ₂ on the passivation layer to form the gate dielectric;

Ni is deposited with a thickness of 1 μm to 2 μm on the gate dielectric to form the gate electrode, wherein the gate electrode fills the channel region and the gate contact region.

Preferably, the step of depositing an oxide layer on the gate dielectric and preparing a source electrode and a drain electrode to obtain the silicon-based gallium nitride HEMT device includes:

Deposit an oxide of 1 μm to 2 μm on the gate dielectric to form the oxide layer;

A drain trench connected to the first ohmic metal is etched at a position of the oxide corresponding to the first ohmic metal, and a drain trench connected to the second ohmic metal is etched at a position of the oxide corresponding to the second ohmic metal. The source groove of the second ohmic metal;

The source electrode is prepared in the source electrode trench, and the drain electrode is prepared in the drain electrode trench;

The silicon-based gallium nitride HEMT device is obtained.

Preferably, the steps of preparing the source electrode in the source trench and the drain electrode in the drain trench include:

Deposit a layer of metal on the oxide layer to form a metal layer, wherein the metal layer fills the source groove and the drain groove and is in contact with the first ohmic metal and the second ohmic metal. ;

The metal layer is etched so that the drain electrode is formed at a position of the metal layer corresponding to the drain groove, and the source electrode is formed at a position of the metal layer corresponding to the source groove.

Preferably, the metal layer is etched so that the drain electrode is formed at a position of the metal layer corresponding to the drain groove, and the source electrode is formed at a position of the metal layer corresponding to the source groove. The following steps also include:

A source field plate connected to the source electrode is prepared on the oxide layer, and the source field plate is located above the gate electrode.

The invention also provides a silicon-based gallium nitride HEMT device, which includes an N-type Si substrate, a core layer, a first buffer layer, a second buffer layer, a back barrier layer, and a channel layer that are stacked sequentially from bottom to top. , insertion layer and barrier layer, the channel layer, the barrier layer and the outer edge of the insertion layer form an isolation area, the barrier layer is provided with a first ohmic metal on both sides along the first direction. and a second ohmic metal. A cap layer is provided between the first ohmic metal and the barrier layer. A passivation layer is provided on the barrier layer. The passivation layer covers the first ohmic metal and the barrier layer. The second ohmic metal fills the isolation area, a gate groove connected to the insertion layer is opened on the passivation layer and the barrier layer, and the gate groove connects the barrier layer Divided into multiple channels along the second direction, the first direction is perpendicular to the second direction, a gate dielectric is provided on the passivation layer, the gate dielectric covers the gate trench, and the gate A gate electrode in contact with the gate dielectric is provided in the electrode groove, an oxide layer is provided on the gate dielectric, a source electrode in contact with the second ohmic metal and a source electrode in contact with the second ohmic metal are provided on the oxide layer. One ohm metal contact to the drain electrode.

In the technical solution of the present invention, by placing P-GaN between the first ohmic metal corresponding to the drain and the barrier layer, P-GaN has a conductance modulation effect similar to that in IGBT, increasing the saturation output current of the device, and at the same time Divide the barrier layer into multiple channels by etching the barrier layer, etching part of the barrier layer, and the remaining non-etched parts form channels without over-etching the channels, and then use the gate electrode to Multiple channels are fully covered, thereby turning the device into an enhancement mode device without introducing other defects. A second buffer layer is formed by growing C-doped GaN between the back barrier layer and the first buffer layer to prevent The body leakage current enters the second buffer layer; furthermore, a back barrier layer is formed by growing AlGaN between the second buffer layer and the channel layer, forming a higher electron barrier to prevent 2DEG electrons from being absorbed by the second buffer layer. The deep-level impurities in the IC are captured and accumulated, thereby reducing the dynamic resistance of the device and avoiding the occurrence of current collapse; at the same time, the gate electrode that fully covers the channel has stronger gate control capabilities and reduces the sub-threshold swing of the device. , when the device is turned on, due to the positive voltage applied to the gate, an inversion layer (i.e., electron accumulation layer) will be formed in the channel area, accumulating electrons and reducing the on-resistance of the device. When the device is turned off, the channel is pinched off, reducing the device leakage current.

Description of the drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without exerting creative efforts.

Figure 1 is a flow chart of a manufacturing method of a silicon-based gallium nitride HEMT device according to an embodiment of the present invention;

Figure 2 is a flow chart of step S500 of the manufacturing method of a GaN-on-silicon HEMT device according to an embodiment of the present invention;

Figure 3 is a flow chart of step S800 of the manufacturing method of a GaN-on-Si HEMT device according to an embodiment of the present invention;

Figure 4 is a schematic structural diagram of a silicon-based gallium nitride HEMT device according to an embodiment of the present invention;

Figure 5 is a schematic structural diagram corresponding to step S100 of a silicon-based gallium nitride HEMT device according to an embodiment of the present invention;

Figure 6 is a schematic structural diagram corresponding to step S500 of a silicon-based gallium nitride HEMT device according to an embodiment of the present invention;

Figure 7 is a schematic structural diagram of the silicon-based gallium nitride HEMT device corresponding to step S700 according to an embodiment of the present invention;

Figure 8 is a schematic top view of the structure corresponding to step S300 of a silicon-based gallium nitride HEMT device according to an embodiment of the present invention;

Figure 9 is a schematic top structural view of the silicon-based gallium nitride HEMT device corresponding to step S500 according to an embodiment of the present invention;

Figure 10 is a schematic top structural diagram of the silicon-based gallium nitride HEMT device corresponding to step S600 according to an embodiment of the present invention;

FIG. 11 is a schematic side view of a partial structure of a silicon-based gallium nitride HEMT device according to an embodiment of the present invention.

Explanation of reference numbers:

label name label name 1 GaN-on-silicon HEMT devices 31 first ohmic metal 10 substrate 32 Second ohmic metal 11 nucleation layer 40 passivation layer 12 first buffer layer 41 gate contact area 13 second buffer layer 42 channel region 20 back barrier layer 43 channel twenty one channel layer 50 gate dielectric twenty two Insert layer 60 gate electrode twenty three barrier layer 61 source electrode twenty four quarantine area 62 Drain electrode 30 cap layer 70 oxide layer

The realization of the purpose, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings.

Detailed ways

The technical solution in this embodiment will be clearly and completely described below with reference to the accompanying drawings in this embodiment. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back...) in this embodiment are only used to explain the relative relationship between components in a specific posture (as shown in the accompanying drawings). Positional relationship, movement conditions, etc., if the specific posture changes, the directional indication will also change accordingly.

In addition, descriptions such as "first", "second", etc. in the present invention are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

In the present invention, unless otherwise clearly stated and limited, the terms "connection", "fixing", etc. should be understood in a broad sense. For example, "fixing" can be a fixed connection, a detachable connection, or an integral body; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interactive relationship between two elements, unless otherwise clearly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on what a person of ordinary skill in the art can implement. When the combination of technical solutions is contradictory or cannot be realized, it should be considered that such a combination of technical solutions is possible. It does not exist and is not within the protection scope required by the present invention. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

The present invention proposes a silicon-based gallium nitride HEMT device and a manufacturing method thereof.

Please combine Figure 1 and Figure 4-Figure 11. The manufacturing method of the silicon-based gallium nitride HEMT device in this embodiment includes the following steps:

S100: Provide a substrate, and sequentially stack a core layer, a first buffer layer and a second buffer layer on the substrate, wherein the substrate is an N-type Si substrate, and the second buffer layer is C-doped GaN buffer layer;

By preparing the nucleation layer 11 and the first buffer layer 12 on the substrate 10, the quality of subsequent crystal growth can be improved, and the lattice mismatch between the substrate 10 and GaN can be reduced. At the same time, a C-doped GaN buffer layer is provided. The second buffer layer 13 blocks body leakage current and prevents current from still flowing after the device is turned off, thereby reducing the overall power consumption of the device;

S200: Grow a layer of AlGaN on the second buffer layer to form a back barrier layer, and sequentially stack a channel layer, an insertion layer and a barrier layer on the back barrier layer, wherein the channel layer is a GaN channel layer, and the barrier layer is an AlGaN barrier layer;

AlGaN alloy is composed of aluminum nitride (AlN) and gallium nitride (GaN). The aluminum (Al) atoms in AlGaN replace part of the nitrogen (N) atoms. Since Al atoms are larger than N atoms, this substitution causes the crystal lattice to be slightly deformed, forming an electron barrier. The back barrier layer 20 is formed by growing AlGaN between the second buffer layer 13 and the channel layer 21, forming a higher The electron barrier is used to prevent the electrons of 2DEG from being captured and accumulated by the deep level impurities in the second buffer layer 13, thereby reducing the dynamic resistance of the device and avoiding the occurrence of current collapse; an insertion layer 22 is prepared on the channel layer 21 to To expand the barrier depth of 2DEG, an AlGaN barrier layer 23 is prepared on the GaN channel layer 21. A built-in polarization electric field is induced through the AlGaN/GaN heterojunction due to the spontaneous polarization effect and the piezoelectric polarization effect, thus generating High-density, high-mobility 2DEG;

S300: Etch the outer edges of the channel layer, the barrier layer and the insertion layer to form an isolation region;

Etch all the outer peripheries of the channel layer 21, the barrier layer 23 and the insertion layer 22 to form an isolation region 24, and neutralize the 2DEG so that it does not participate in conduction;

S400: Deposit a layer of P-GaN on the barrier layer, and etch the P-GaN except for the first preset pattern to form a cap layer, wherein the first preset pattern is located on the barrier layer. one edge of the barrier;

The P-GaN cap layer 30 is used as the conductance of the source electrode 61 to modulate the PN junction to facilitate the subsequent preparation of the drain electrode 62;

S500: Prepare a first ohmic metal on the cap layer, prepare a second ohmic metal on the other edge of the barrier layer, and deposit a passivation layer on the barrier layer, wherein the passivation layer The chemical layer covers the first ohmic metal and the second ohmic metal;

By preparing the first ohmic metal 31 and the second ohmic metal 32 to achieve ohmic contact between the source electrode 61, the drain electrode 62 and the barrier layer 23, current can be effectively injected into the two-dimensional electron gas (2DEG) channel of the semiconductor, thereby The conduction state of the device is realized;

S600: Etch the passivation layer to form a gate contact area connected to the barrier layer, and etch along the second preset pattern on the barrier layer to form a channel area connected to the insertion layer , so that the barrier layer forms a multi-stage channel, wherein the second preset pattern is provided corresponding to the gate contact region;

First, the gate contact region 41 is etched on the passivation layer 40 to expose the bottom barrier layer 23 , and then a channel connected to the insertion layer 22 is etched on the barrier layer 23 below the gate contact region 41 Region 42 is used to divide the barrier layer 23 into multiple sections of channels 43, so that the subsequent gate electrode 60 can fully cover the channels 43;

S700: Deposit a gate dielectric on the passivation layer, and prepare a gate electrode on the gate dielectric, wherein the gate dielectric covers the channel area, and the gate electrode connects multiple sections of the channel full coverage;

The gate electrode 60 that fully covers the channel 43 has stronger gate control capability and reduces the sub-threshold swing of the device. When the device is turned on, due to the positive voltage applied to the gate, an inversion layer will be formed in the channel region 42 (i.e., electron accumulation layer), accumulates electrons, reduces the on-resistance of the device, pinches off the channel 43 in the off state, and reduces the leakage current of the device;

S800: Deposit an oxide layer on the gate dielectric and prepare a source electrode and a drain electrode to obtain the silicon-based gallium nitride HEMT device, wherein the source electrode is in contact with the second ohmic metal, and the drain electrode in contact with the first ohmic metal.

In the technical solution of the present invention, by disposing P-GaN between the first ohmic metal 31 corresponding to the drain and the barrier layer 23, P-GaN has a conductance modulation effect similar to that in IGBT, increasing the saturation output current of the device. , and at the same time, the barrier layer 23 is divided into a plurality of channels 43 by etching the barrier layer 23, etching part of the barrier layer 23, and the remaining non-etched parts form channels 43, without causing any damage to the channels 43. Over-etching, and then all the channels 43 are covered by the gate electrode 60, thereby turning the device into an enhancement mode device without introducing other defects. C-doped GaN is grown to form the second buffer layer 13 to prevent body leakage current from entering the second buffer layer 13; furthermore, AlGaN is grown between the second buffer layer 13 and the channel layer 21 to form the back barrier layer 20, forming The higher electron barrier prevents the electrons of 2DEG from being captured and accumulated by the deep level impurities in the second buffer layer 13, thereby reducing the dynamic resistance of the device and avoiding the occurrence of current collapse; at the same time, the channel 43 is fully covered The gate electrode 60 has stronger gate control capability, which reduces the sub-threshold swing of the device. When the device is turned on, due to the positive voltage applied to the gate, an inversion layer (i.e., electron accumulation layer) will be formed in the channel region 42. Accumulate electrons, reduce the on-resistance of the device, pinch off the channel 43 in the off state, and reduce the leakage current of the device.

Please refer to Figure 5. Further, step S100 includes:

S110: Provides N-type Si substrate with heavily doped (111) crystal orientation;

Silicon substrates 10 with different doping concentrations are selected according to the application requirements. The Si surface in the (111) crystal orientation is usually relatively flat, which reduces surface scattering and defects and helps improve carrier mobility;

S120: Epitaxially grow a layer of AlN with a thickness of 0.1nm to 0.3nm on the substrate to form the nucleation layer;

The lattice constant of AlN is very close to that of GaN, and the lattice mismatch between them is very small, which helps to reduce the lattice mismatch when growing GaN films on AlN. This lattice matching reduces the risk of interference at the interface. Therefore, AlN is grown on the Si substrate 10 as a buffer, thereby improving the quality of the GaN layer.

S130: Epitaxially grow AlGaN with a thickness of 0.5 μm to 2 μm on the nucleation layer to form the first buffer layer, wherein the Al concentration of AlGaN increases from the nucleation layer to the direction away from the nucleation layer. ;

The graded concentration AlGaN layer allows for gradual changes in the aluminum (Al) composition, thereby gradually adjusting the lattice constant. When the Al concentration in AlGaN gradually increases, its lattice constant gradually approaches that of gallium nitride (GaN) or aluminum nitride (AlN). This means that in the AlGaN layer, the change of lattice parameters is more gradual, reducing the sharp lattice mismatch with Si or GaN;

S140: Grow C-doped GaN with a thickness of 2 μm to 4 μm on the first buffer layer to form the second buffer layer.

By arranging the nucleation layer 11 and the first buffer layer 12 on the substrate 10 , the lattice mismatch between Si and GaN is reduced, thereby improving the molding quality of the subsequently grown GaN, and at the same time blocking body leakage current through the second buffer layer 13 , preventing current from still flowing after the device is turned off, thereby reducing the overall power consumption of the device.

In an embodiment, step S200 includes:

S210: Grow AlGaN with a thickness of 1 μm to 2 μm on the second buffer layer to form the back barrier layer;

A higher electron potential barrier is formed through the back barrier potential layer to prevent the electrons of 2DEG from being captured and accumulated by the deep level impurities in the second buffer layer 13, thereby reducing the dynamic resistance of the device and avoiding the occurrence of current collapse;

S220: Grow GaN with a thickness of 0.3 μm to 1 μm on the back barrier layer to form the channel layer;

Due to its excellent material properties, GaN is suitable for preparing devices used in high-frequency, high-voltage and high-power scenarios;

S230: Grow AlN with a thickness of 0.8nm to 1.2nm on the channel layer to form the insertion layer;

The energy gap of the AlN insertion layer 22 is usually larger than the energy gap of the GaN material. Since AlN has a larger energy gap, it forms a potential barrier on the GaN material. This potential barrier will capture and confine free electrons on the GaN surface. These free electrons are confined near the AlN/GaN interface and form 2DEG, thereby improving the flow of current and conductive properties;

S240: Grow AlGaN with a thickness of 20 nm to 30 nm on the insertion layer to form the barrier layer.

An AlGaN barrier layer 23 is prepared on the GaN channel layer 21, and a built-in polarization electric field is induced through the AlGaN/GaN heterojunction due to the spontaneous polarization effect and the piezoelectric polarization effect, thereby generating a high-density, high-mobility 2DEG.

Please combine Figure 6 and Figure 9. In one embodiment, step S500 includes:

S510: Deposit ohm metal on the barrier layer, where the ohm metal is a stacked structure composed of Ti, Al, Ni and Ag, and the ohm metal covers the barrier layer and the cap layer;

Deposit ohm metal on the barrier layer 23 so that the first ohmic metal and the second ohmic metal can be formed by subsequent etching at one time, thereby improving manufacturing efficiency;

S520: Use the ohm metal except the third preset pattern and the cap layer to form the first ohm metal and the second ohm metal, wherein the third preset pattern is located on the potential barrier The edge of one side of the layer away from the cap layer;

The first ohmic metal 31 and the second ohmic metal 32 are located on opposite sides of the barrier layer 23, so that the subsequently prepared source electrode 61 and the drain electrode 62 are located on opposite sides of the barrier layer 23, thereby forming a 2DEG so that electrons can be more Efficient transmission;

S530: Deposit SiN with a thickness of 75 nm to 125 nm on the barrier layer to form a passivation layer, where the passivation layer fills the isolation region. The passivation layer 40 fills the isolation region 24 and covers the barrier layer 23, the first ohmic metal 31 and the second ohmic metal 32. The passivation layer 40 protects the barrier layer 23, the insertion layer 22, the channel layer 21 and the back surface. The barrier layer 20, the first ohmic metal 31 and the second ohmic metal 32 protect them from damage and extend their service life.

Please refer to Figure 10. Further, step S600 includes:

S610: Etch the passivation layer at a first preset position of the passivation layer to form the gate contact area, where the gate contact area is rectangular;

Etch a rectangular gate contact region 41 on the passivation layer 40 to expose the barrier layer 23 below it and facilitate subsequent etching of the channel region 42;

S620: Continue to etch downward along the gate contact area, and etch along the second preset pattern on the barrier layer to form the channel area, where the second preset pattern is hexagonal or octagonal. shape.

Please combine Figure 10 and Figure 11. It can be understood that there is a channel area 42 at both ends of the barrier layer 23 to divide the remaining barrier layer 23 into multiple channels 43. It can be understood that conventional In the rectangular channel region 42, an electric field peak will be formed at the right angle in the direction of the drain electrode 62, which will reduce the withstand voltage of the device. In the hexagonal or octagonal channel region 42, an electric field peak will not be formed in the corners, so that Improve the withstand voltage of the device.

Referring to Figure 7, in one embodiment, step S700 includes:

S710: Deposit 1 nm to 10 nm thick HfO ₂ , La ₂ O ₃ or TiO ₂ on the passivation layer to form the gate dielectric;

HfO ₂ , La ₂ O ₃ and TiO ₂ all have higher dielectric constants, which can store more charges at smaller gate voltages, thereby achieving higher current switching performance;

S720: Deposit Ni with a thickness of 1 μm to 2 μm on the gate dielectric to form the gate electrode, wherein the gate electrode fills the channel region and the gate contact region.

Further, step S800 includes:

S810: Deposit an oxide of 1 μm to 2 μm on the gate dielectric to form the oxide layer;

The deposited oxide layer 70 isolates the gate electrode 60 from the external environment and protects the gate electrode 60;

S820: Etching to form a drain trench connected to the first ohmic metal at the position of the oxide corresponding to the first ohmic metal, and etching to form a connection at the position of the oxide corresponding to the second ohmic metal. to a source trench of said second ohmic metal;

S830: Prepare the source electrode in the source groove, and prepare the drain electrode in the drain groove;

S840: Obtain the silicon-based gallium nitride HEMT device.

The source electrode 61 and the drain electrode 62 respectively pass through the source groove and the drain groove and are in contact with the second ohmic metal 32 and the first ohmic metal 31 to form a complete circuit and obtain a silicon-based gallium nitride HEMT device.

Specifically, step S830 includes:

S831: Deposit a layer of metal on the oxide layer to form a metal layer, wherein the metal layer fills the source groove and the drain groove and is combined with the first ohmic metal and the second ohmic metal. metal contact;

S832: Etch the metal layer so that the drain electrode is formed on the metal layer corresponding to the drain groove, and the source electrode is formed on the metal layer corresponding to the source groove.

By depositing metal at one time and filling the source and drain trenches, and then etching the metal layer, the source electrode 61 and the drain electrode 62 can be simultaneously prepared in one process, thereby improving preparation efficiency.

In one embodiment, step S832 also includes:

S833: Prepare a source field plate connected to the source electrode on the oxide layer, and the source field plate is located above the gate electrode. Preparing a source field plate connected to the source electrode above the gate electrode can evenly distribute the electric field, reduce the concentration of the electric field, protect the gate electrode, weaken the electric field intensity experienced by the gate electrode, reduce the risk of breakdown, and improve the reliability of the device. sex.

The invention also provides a silicon-based gallium nitride HEMT device, which includes an N-type Si substrate 10, a core layer, a first buffer layer 12, a second buffer layer 13, and a back barrier layer 20 that are stacked sequentially from bottom to top. , the channel layer 21, the insertion layer 22 and the barrier layer 23. The outer edges of the channel layer 21, the barrier layer 23 and the insertion layer 22 form an isolation area 24. The barrier layer 23 is formed along the third A first ohmic metal 31 and a second ohmic metal 32 are respectively provided on both sides in one direction. A cap layer 30 is provided between the first ohmic metal 31 and the barrier layer 23. A cap layer 30 is provided on the barrier layer 23. There is a passivation layer 40 covering the first ohmic metal 31 and the second ohmic metal 32 and filling the isolation region 24 , the passivation layer 40 and the barrier layer 23 There is a gate groove connected to the insertion layer 22 . The gate groove divides the barrier layer 23 into a plurality of channels 43 along a second direction. The first direction is perpendicular to the second direction. , a gate dielectric 50 is provided on the passivation layer 40, the gate dielectric 50 covers the gate groove, and a gate electrode 60 in contact with the gate dielectric 50 is provided in the gate groove, so An oxide layer 70 is provided on the gate dielectric 50 , and a source electrode 61 in contact with the second ohmic metal 32 and a drain electrode 62 in contact with the first ohmic metal 31 are provided on the oxide layer 70 .

In the technical solution of the present invention, by disposing P-GaN between the first ohmic metal 31 corresponding to the drain and the barrier layer 23, P-GaN has a conductance modulation effect similar to that in IGBT, increasing the saturation output current of the device. , and at the same time, the barrier layer 23 is divided into a plurality of channels 43 by etching the barrier layer 23, etching part of the barrier layer 23, and the remaining non-etched parts form channels 43, without causing any damage to the channels 43. Over-etching, and then all the channels 43 are covered by the gate electrode 60, thereby turning the device into an enhancement mode device without introducing other defects. C-doped GaN is grown to form the second buffer layer 13 to prevent body leakage current from entering the second buffer layer 13; furthermore, AlGaN is grown between the second buffer layer 13 and the channel layer 21 to form the back barrier layer 20, forming The higher electron barrier prevents the electrons of 2DEG from being captured and accumulated by the deep level impurities in the second buffer layer 13, thereby reducing the dynamic resistance of the device and avoiding the occurrence of current collapse; at the same time, the channel 43 is fully covered The gate electrode 60 has stronger gate control capability, which reduces the sub-threshold swing of the device. When the device is turned on, due to the positive voltage applied to the gate, an inversion layer (i.e., electron accumulation layer) will be formed in the channel region 42. Accumulate electrons, reduce the on-resistance of the device, pinch off the channel 43 in the off state, and reduce the leakage current of the device.

The above are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the description and drawings of the present invention may be directly or indirectly used in other related technical fields. , are all similarly included in the scope of patent protection of the present invention.

Claims (10)

1. A method for manufacturing a silicon-based gallium nitride HEMT device, which is characterized by comprising the following steps: A substrate is provided, and a core layer, a first buffer layer and a second buffer layer are sequentially stacked on the substrate, wherein the substrate is an N-type Si substrate and the second buffer layer is C-doped. GaN buffer layer; A layer of AlGaN is grown on the second buffer layer to form a back barrier layer, and a channel layer, an insertion layer and a barrier layer are sequentially stacked on the back barrier layer, wherein the channel layer is GaN Channel layer, the barrier layer is an AlGaN barrier layer; Etching the outer edges of the channel layer, the barrier layer and the insertion layer to form an isolation region; Deposit a layer of P-GaN on the barrier layer, and etch the P-GaN except for the first preset pattern to form a cap layer, wherein the first preset pattern is located on the barrier layer edge of one side; A first ohmic metal is prepared on the cap layer, and a second ohmic metal is prepared on the other edge of the barrier layer, and a passivation layer is deposited on the barrier layer, wherein the passivation layer covering the first ohmic metal and the second ohmic metal; Etching the passivation layer to form a gate contact area connected to the barrier layer, and etching along the second preset pattern on the barrier layer to form a channel area connected to the insertion layer, so as to causing the barrier layer to form a multi-stage channel, wherein the second preset pattern is provided corresponding to the gate contact area; Deposit a gate dielectric on the passivation layer, and prepare a gate electrode on the gate dielectric, wherein the gate dielectric covers the channel area, and the gate electrode fully covers multiple sections of the channel. cover; Deposit an oxide layer on the gate dielectric and prepare a source electrode and a drain electrode to obtain the silicon-based gallium nitride HEMT device, wherein the source electrode is in contact with the second ohmic metal, and the drain electrode is in contact with the second ohmic metal. The first ohmic metal contact. 2. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein a substrate is provided, and a nucleation layer, a first buffer layer and a third buffer layer are sequentially deposited on the substrate. The steps for the second buffer layer include: Provides N-type Si substrates heavily doped with (111) crystal orientation; Epitaxially grow a layer of AlN with a thickness of 0.1nm to 0.3nm on the substrate to form the nucleation layer; Epitaxially growing AlGaN with a thickness of 0.5 μm to 2 μm on the nucleation layer to form the first buffer layer, wherein the Al concentration of AlGaN increases from the nucleation layer to a direction away from the nucleation layer; C-doped GaN with a thickness of 2 μm to 4 μm is grown on the first buffer layer to form the second buffer layer. 3. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein a layer of AlGaN is grown on the second buffer layer to form a back barrier layer, and the back barrier layer is formed on the second buffer layer. The steps of sequentially stacking the channel layer, the insertion layer and the barrier layer on the barrier layer include: Grow AlGaN with a thickness of 1 μm to 2 μm on the second buffer layer to form the back barrier layer; Grow GaN with a thickness of 0.3 μm to 1 μm on the back barrier layer to form the channel layer; Grow AlN with a thickness of 0.8nm to 1.2nm on the channel layer to form the insertion layer; AlGaN with a thickness of 20 nm to 30 nm is grown on the insertion layer to form the barrier layer. 4. The method for manufacturing a silicon-based gallium nitride HEMT device according to claim 1, wherein a first ohmic metal is prepared on the cap layer and on the other edge of the barrier layer. Preparing a second ohmic metal, and depositing a passivation layer on the barrier layer includes: Depositing ohm metal on the barrier layer, wherein the ohm metal is a stacked structure composed of Ti, Al, Ni and Ag, and the ohm metal covers the barrier layer and the cap layer; The first ohmic metal and the second ohmic metal are formed from the ohm metal except the third preset pattern and the cap layer, wherein the third preset pattern is located away from the barrier layer One side edge of the cap layer; SiN with a thickness of 75 nm to 125 nm is deposited on the barrier layer to form a passivation layer, where the passivation layer fills the isolation region. 5. The manufacturing method of a silicon-based gallium nitride HEMT device according to claim 1, wherein the etching of the passivation layer forms a gate contact area connected to the barrier layer, and the The step of etching the barrier layer along a second preset pattern to form a channel region connected to the insertion layer so that the barrier layer forms a multi-stage channel includes: Etching the passivation layer at a first preset position of the passivation layer to form the gate contact area, wherein the gate contact area is rectangular; Continue to etch downward along the gate contact area, and etch along a second preset pattern on the barrier layer to form the channel area, where the second preset pattern is a hexagon or an octagon. 6. The manufacturing method of a silicon-based gallium nitride HEMT device according to any one of claims 1 to 5, wherein a gate dielectric is deposited on the passivation layer, and a gate dielectric is deposited on the gate dielectric. The steps to prepare the gate electrode include: Deposit 1 nm to 10 nm thick HfO ₂ , La ₂ O ₃ or TiO ₂ on the passivation layer to form the gate dielectric; Ni is deposited with a thickness of 1 μm to 2 μm on the gate dielectric to form the gate electrode, wherein the gate electrode fills the channel region and the gate contact region. 7. The manufacturing method of a silicon-based gallium nitride HEMT device according to any one of claims 1 to 5, characterized in that: depositing an oxide layer on the gate dielectric and preparing a source electrode and a drain electrode, The steps of obtaining the silicon-based gallium nitride HEMT device include: Deposit an oxide of 1 μm to 2 μm on the gate dielectric to form the oxide layer; A drain trench connected to the first ohmic metal is etched at a position of the oxide corresponding to the first ohmic metal, and a drain trench connected to the second ohmic metal is etched at a position of the oxide corresponding to the second ohmic metal. The source groove of the second ohmic metal; The source electrode is prepared in the source electrode trench, and the drain electrode is prepared in the drain electrode trench; The silicon-based gallium nitride HEMT device is obtained. 8. The manufacturing method of a silicon-based gallium nitride HEMT device according to claim 7, wherein the source electrode is prepared in the source groove, and the leakage electrode is prepared in the drain groove. Extreme steps include: Deposit a layer of metal on the oxide layer to form a metal layer, wherein the metal layer fills the source groove and the drain groove and is in contact with the first ohmic metal and the second ohmic metal. ; The metal layer is etched so that the drain electrode is formed at a position of the metal layer corresponding to the drain groove, and the source electrode is formed at a position of the metal layer corresponding to the source groove. 9. The method for manufacturing a GaN-on-silicon HEMT device according to claim 8, wherein the metal layer is etched to form the metal layer at a position corresponding to the drain trench. Drain electrode. After the step of forming the source electrode on the metal layer corresponding to the position of the source groove, the step further includes: A source field plate connected to the source electrode is prepared on the oxide layer, and the source field plate is located above the gate electrode. 10. A silicon-based gallium nitride HEMT device, characterized in that it includes an N-type Si substrate, a core layer, a first buffer layer, a second buffer layer, a back barrier layer, and a trench, which are stacked sequentially from bottom to top. A channel layer, an insertion layer and a barrier layer. The outer edges of the channel layer, the barrier layer and the insertion layer form an isolation area. The barrier layer is provided with first elements on both sides along the first direction. Ohmic metal and a second ohmic metal, a cap layer is provided between the first ohmic metal and the barrier layer, a passivation layer is provided on the barrier layer, and the passivation layer covers the first ohmic metal. The metal and the second ohmic metal fill the isolation area, and a gate groove connected to the insertion layer is opened on the passivation layer and the barrier layer, and the gate groove connects the barrier layer to the barrier layer. The barrier layer is divided into multiple channels along a second direction, the first direction is perpendicular to the second direction, a gate dielectric is provided on the passivation layer, and the gate dielectric covers the gate trench, so A gate electrode in contact with the gate dielectric is provided in the gate trench, an oxide layer is provided on the gate dielectric, a source electrode in contact with the second ohmic metal and a source electrode in contact with the second ohmic metal are provided on the oxide layer. The first ohmic metal contacts the drain electrode.