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CN117457709A - Semiconductor device structure and preparation method thereof - Google Patents

Semiconductor device structure and preparation method thereof Download PDF

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Publication number
CN117457709A
CN117457709A CN202210854835.8A CN202210854835A CN117457709A CN 117457709 A CN117457709 A CN 117457709A CN 202210854835 A CN202210854835 A CN 202210854835A CN 117457709 A CN117457709 A CN 117457709A
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China
Prior art keywords
region
layer
forming
doped region
contact hole
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CN202210854835.8A
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Chinese (zh)
Inventor
韩天宇
李巍
贾鹏飞
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Wuxi China Resources Huajing Microelectronics Co Ltd
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Wuxi China Resources Huajing Microelectronics Co Ltd
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Priority to CN202210854835.8A priority Critical patent/CN117457709A/en
Priority to PCT/CN2023/107287 priority patent/WO2024017136A1/en
Publication of CN117457709A publication Critical patent/CN117457709A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations

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  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a semiconductor device structure and a preparation method thereof, wherein the semiconductor device structure comprises a substrate, a body region, a groove, a doped region, a grid structure, a source region, an interlayer dielectric layer, a contact hole and an upper conductive layer, wherein the body region is positioned in the substrate; the groove is arranged in the body region and the opening is upward; the doped region is positioned in the body region and is at a preset distance from the inner wall of the groove; the gate structure fills the trench; the source region is at least positioned on the upper surface layer of the body region at one side of the grid structure, and the source region and the doped region are positioned in the body region at the same side of the grid structure; the interlayer dielectric layer is positioned above the body region; the contact hole penetrates through the interlayer dielectric layer and the source region and is at a preset distance from the grid structure, the projection of the contact hole in the horizontal direction is intersected with the projection of the doped region in the horizontal direction, and the upper conductive layer fills the contact hole. According to the invention, the doped region which is a preset distance from the gate structure and has a concentration higher than that of the body region is formed in the body region, so that the anti-latch-up capability of the device is improved, and the gate threshold voltage of the device is ensured.

Description

Semiconductor device structure and preparation method thereof
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a semiconductor device structure and a preparation method thereof.
Background
Insulated Gate Bipolar Transistors (IGBTs) and power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are an important branch of power devices. The gate structure of the current mainstream power device basically adopts a trench structure, and the application of the trench structure can further improve the current capability of the power device and reduce the area of a chip, which is a future development trend, as shown in fig. 1 and fig. 2, is a schematic cross-sectional structure of an IGBT device and a schematic cross-sectional structure of a power MOSFET device, and includes a substrate 01, a body region 011, a trench 012, a gate dielectric layer 013, a gate conductive layer 014, a source region 015, a contact region 016, a buffer region 017, a collector region 018, an interlayer dielectric layer 02, a contact hole 021, a first metal layer 03 and a second metal layer 04.
Currently, the doping concentration of the body region in IGBT devices and power MOSFET devices is limited by the threshold voltage of the device, typically between 1×10 doping concentrations 13 cm -3 ～1×10 16 cm -3 In the turn-off process, current flows into the first metal layer from the body region below the source region, potential difference is generated by the current passing through the parasitic resistor, when the current is large, the potential difference value reaches the turn-on voltage of the PN junction between the source region and the body region, so that the parasitic NPN transistor is turned on, the control failure of the gate electrode in the power device on the power device is caused, the failure mode is also called latch-up, and the phenomenon which is common in the application failure of the power device, namely the latch-up resistance of the IGBT device and the power MOSFET device is poor at present.
Therefore, there is an urgent need to find a method for manufacturing a semiconductor device structure that improves the latch-up resistance of a power device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor device structure and a method for manufacturing the same, which are used for solving the problem of poor latch-up resistance of the power device in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing a semiconductor device structure, comprising the steps of:
providing a first conductive type substrate, and forming a second conductive type epitaxial layer on the upper surface of the substrate;
forming a patterned shielding layer on the upper surface of the epitaxial layer, forming grooves which are arranged at intervals and have upward openings in the epitaxial layer based on the patterned shielding layer, wherein the parts of the epitaxial layer, which are positioned on two sides of the grooves, are used as body regions;
ion implantation is carried out on the inner wall of the groove based on the shielding layer so as to form a second conductive type doped region in the body region of at least one side of the groove, and the doped region is spaced from the inner wall of the groove by a preset distance;
forming a gate structure in the trench, forming a source region of a first conductivity type on an upper surface layer of the body region on at least one side of the gate structure, wherein the source region and the doped region are located in the body region on the same side of the trench;
forming an interlayer dielectric layer above the source region, wherein the interlayer dielectric layer covers the exposed surface of the gate structure, a contact hole penetrating through the interlayer dielectric layer and the source region is formed in the interlayer dielectric layer, the contact hole and the gate structure are separated by a preset distance, and the projection of the contact hole in the horizontal direction is intersected with the projection of the doped region in the horizontal direction;
and forming an upper conductive layer filling the contact hole in the contact hole, wherein the upper conductive layer covers the upper surface of the interlayer dielectric layer.
Optionally, the lower surface of the doped region is spaced a preset distance from the lower surface of the body region.
Optionally, the ion implantation forming the doped region has an angle ranging from 30 ° to 60 °.
Optionally, after forming the contact hole, before forming the conductive layer, a step of forming a second conductivity type contact region in the body region below a bottom surface of the contact hole is further included.
Optionally, the doping concentration of the doped region is smaller than the doping concentration of the contact region, and the doping concentration of the body region is smaller than the doping concentration of the doped region.
Optionally, the doped region is in contact with the contact region.
Optionally, after forming the upper conductive layer, a step of forming a buffer region of the first conductivity type on the lower surface layer of the substrate is further included.
Optionally, after forming the upper conductive layer, a step of forming a buffer region of the first conductivity type on the lower surface layer of the substrate is further included.
Optionally, the step of forming a lower conductive layer on the lower surface of the buffer region is further included after forming the buffer region.
Optionally, the method further comprises the following steps: forming a second conductivity type collector region on the lower surface layer of the buffer region; and forming a lower conductive layer on the lower surface of the collector region.
The invention also provides a semiconductor device structure, comprising:
a first conductivity type substrate;
a second conductivity type body region on an upper surface of the substrate;
the grooves are arranged in the body region at intervals, and the openings of the grooves are upward;
a doped region of a second conductivity type located in the body region on at least one side of the trench, the doped region being spaced a predetermined distance from an inner wall of the trench;
a gate structure filled in the trench;
a source region of a first conductivity type located on an upper surface layer of the body region on at least one side of the gate structure, and the source region and the doped region are located in the body region on the same side of the trench;
the interlayer dielectric layer is positioned above the body region and covers the exposed surface of the gate structure;
the contact hole penetrates through the interlayer dielectric layer and the source region, the contact hole and the grid structure are spaced at preset distance, the projection of the contact hole in the horizontal direction is intersected with the projection of the doped region in the horizontal direction, and the upper conductive layer fills the contact hole and covers the upper surface of the interlayer dielectric layer.
As described above, in the semiconductor device structure and the method for manufacturing the same, after the trench is formed based on the patterned shielding layer, ion implantation is performed on the inner wall of the trench based on the shielding layer, so as to obtain the doped region with a preset distance from the inner wall of the trench, so that the formed doped region is prevented from raising the threshold voltage of the gate in the device, and the threshold voltage of the gate is ensured; the doping concentration of the doping region is higher than that of the body region, the doping region is in contact with the contact region, when the device is turned off, hole current in the device flows into the upper conductive layer preferentially through the doping region and the contact region, so that the extraction channel of holes is optimized, meanwhile, the formation of the doping region reduces the resistance value of the body region, the voltage drop of the body region is reduced, the conduction difficulty of a PN junction between the source region and the body region is increased, the starting of a parasitic transistor in the device is restrained, and the latch-up resistance of the device is improved. In addition, the doped region and the trench are formed to share one shielding layer, so that the cost is saved, the process steps are simple, and the method has high industrial utilization value.
Drawings
Fig. 1 is a schematic cross-sectional view of an insulated gate bipolar transistor.
Fig. 2 is a schematic cross-sectional view of a power MOSFET structure.
Fig. 3 is a process flow diagram illustrating a method of fabricating a semiconductor device structure in accordance with the present invention.
Fig. 4 is a schematic cross-sectional view showing a substrate used in the method for manufacturing a semiconductor device structure of the present invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device structure according to the present invention after an epitaxial layer is formed.
Fig. 6 is a schematic cross-sectional view of a semiconductor device structure according to the present invention after forming trenches.
Fig. 7 is a schematic diagram showing a method for fabricating a semiconductor device structure according to the present invention to form a doped region.
Fig. 8 is a schematic cross-sectional view of a semiconductor device structure according to the present invention after forming a gate structure.
Fig. 9 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device structure according to the present invention after forming a source region.
Fig. 10 is a schematic cross-sectional view showing a semiconductor device structure according to the present invention after an interlayer dielectric layer is formed.
Fig. 11 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device structure according to the present invention after forming a contact region.
Fig. 12 is a schematic cross-sectional view showing a method for manufacturing a semiconductor device structure according to the present invention after forming an upper conductive layer.
Fig. 13 is a schematic cross-sectional view showing a structure of a semiconductor device structure according to the present invention after forming a first conductivity type buffer region.
Fig. 14 is a schematic cross-sectional view showing a structure of a semiconductor device structure according to the present invention after forming a collector region.
Fig. 15 is a schematic cross-sectional view of a power MOSFET device formed according to the method of fabricating a semiconductor device structure of the present invention.
Fig. 16 is a schematic cross-sectional view showing the formation of an IGBT device according to the method of manufacturing a semiconductor device structure of the present invention.
Fig. 17 is a schematic cross-sectional view showing the formation of another IGBT device according to the method of manufacturing a semiconductor device structure of the invention.
Description of element reference numerals
01. Substrate and method for manufacturing the same
011. Body region
012. Groove(s)
013. Gate dielectric layer
014. Gate conductive layer
015. Source region
016. Contact region
017. Buffer zone
018. Collector region
02. Interlayer dielectric layer
021. Contact hole
03. A first metal layer
04. Second metal layer
1. Substrate and method for manufacturing the same
11. Epitaxial layer
12. Groove(s)
13. Body region
131. Contact region
14. Doped region
15. Gate structure
151. Gate dielectric layer
152. Gate conductive layer
16. Source region
17. Buffer zone
18. Collector region
2. Masking layer
21. Mask layer
22. Photoresist layer
3. Interlayer dielectric layer
31. Contact hole
4. Upper conductive layer
5. Lower conductive layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 3 to 17. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The embodiment provides a method for manufacturing a semiconductor device structure, as shown in fig. 3, which is a process flow chart of the method for manufacturing the semiconductor device structure, and includes the following steps:
s1: providing a first conductive type substrate, and forming a second conductive type epitaxial layer on the upper surface of the substrate;
s2: forming a patterned shielding layer on the upper surface of the epitaxial layer, forming grooves which are arranged at intervals and have upward openings in the epitaxial layer based on the patterned shielding layer, wherein the parts of the epitaxial layer, which are positioned on two sides of the grooves, are used as body regions;
s3: ion implantation is carried out on the inner wall of the groove based on the shielding layer so as to form a second conductive type doped region in the body region of at least one side of the groove, and the doped region is spaced from the inner wall of the groove by a preset distance;
s4: forming a gate structure in the trench, forming a source region of a first conductivity type on an upper surface layer of the body region on at least one side of the gate structure, wherein the source region and the doped region are located in the body region on the same side of the trench;
s5: forming an interlayer dielectric layer above the source region, wherein the interlayer dielectric layer covers the exposed surface of the gate structure, a contact hole penetrating through the interlayer dielectric layer and the source region is formed in the interlayer dielectric layer, the contact hole and the gate structure are spaced by a preset distance, and the projection of the contact hole in the horizontal direction overlaps with the projection of the doped region in the horizontal direction;
s6: and forming an upper conductive layer filling the contact hole in the contact hole, wherein the upper conductive layer covers the upper surface of the interlayer dielectric layer.
Referring to fig. 4 to 6, the steps S1 and S2 are performed: providing a first conductive type substrate 1, and forming a second conductive type epitaxial layer 11 on the upper surface of the substrate 1; a patterned shielding layer 2 is formed on the upper surface of the epitaxial layer 11, trenches 12 are formed in the epitaxial layer 11 at intervals and with upward openings based on the patterned shielding layer 2, and portions of the epitaxial layer located at two sides of the trenches 12 are used as body regions 13.
Specifically, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.
Specifically, as shown in fig. 4, which is a schematic cross-sectional structure of the substrate 1, the doping concentration range in the substrate 1 may be selected according to practical situations, which is not limited herein.
Specifically, the material of the substrate 1 includes silicon, silicon germanium, silicon carbide or other suitable semiconductor materials.
Specifically, the thickness of the substrate 1 may be selected according to the actual situation, while ensuring the device performance, and is not limited here.
Specifically, as shown in fig. 5, in order to schematically illustrate the cross-sectional structure of the epitaxial layer 11 after the formation of the epitaxial layer 11, the doping concentration of the epitaxial layer 11 may be selected according to practical situations, which is not limited herein.
Specifically, the thickness of the epitaxial layer 11 may be selected according to practical situations, while ensuring the device performance, and is not limited herein.
Specifically, the shielding layer 2 includes at least one of a mask layer 21 and a photoresist layer 22, and may be other suitable films with shielding effect. In this embodiment, the shielding layer 2 includes a mask layer 21 disposed on the upper surface of the epitaxial layer 11 and a photoresist layer 22 disposed on the upper surface of the mask layer 21, i.e. after forming a mask layer 21 on the upper surface of the epitaxial layer 11, a photoresist layer 22 is formed on the upper surface of the mask layer 21 to obtain the shielding layer 2.
Specifically, the mask layer 21 is made of silicon oxide, silicon nitride or other suitable materials. In this embodiment, a silicon oxide/silicon nitride/silicon oxide stack structure is used as the mask layer 21, so as to avoid the poor bonding force between the photoresist layer 22 and the substrate 1, which affects the device fabrication.
Specifically, as shown in fig. 6, to schematically illustrate the cross-sectional structure of the trench 12 after forming the trench 12, the method for forming the trench 12 includes dry etching, wet etching, or other suitable methods.
Specifically, the trench depth and the opening size of the trench 12 may be selected according to practical situations, and are not limited herein, while ensuring the device performance.
Referring to fig. 7 to 9, the steps S3 and S4 are performed: ion implanting an inner wall of the trench 12 based on the shielding layer 2 to form a second conductive type doped region 14 in the body region 13 of at least one side of the trench 12, the doped region 14 being spaced apart from the inner wall of the trench 12 by a predetermined distance; a gate structure 15 is formed in the trench 12, a source region 16 of a first conductivity type is formed on an upper surface layer of the body region 13 on at least one side of the gate structure 15, and the source region 16 and the doped region 14 are located in the body region 13 on the same side of the trench 12.
As an example, as shown in fig. 7, to form the doped region 14, the angle of ion implantation to form the doped region 14 is in the range of 30 ° to 60 °. In this embodiment, the angle of ion implantation is 45 ° during the formation of the doped region 14.
Specifically, the doped region 14 is spaced from the inner wall of the trench 12 by a predetermined distance, so that the doped region 14 is far away from the gate dielectric layer 151 region of the gate structure 15, and the doped region 14 is prevented from affecting the threshold voltage of the gate structure 15, which results in raising the threshold voltage of the gate structure 15.
Specifically, the distance between the doped region 14 and the inner wall of the trench 12 may be selected according to the actual situation under the condition that the doped region 14 does not affect the threshold voltage of the gate structure 15, that is, the energy when the doped region 14 is formed to affect the threshold voltage of the gate and is located in the body region 13, and the energy when the ion implantation is performed on the inner wall of the trench 12 may be selected according to the actual situation.
Specifically, the size of the doped region 14 may be selected according to the actual situation, while ensuring the device performance, and is not limited herein.
Specifically, the lower surface of the doped region 14 is spaced from the lower surface of the body region 13 by a predetermined distance, so as to prevent the doped region 14 from affecting the voltage-withstanding capability of the device.
Specifically, the distance between the lower surface of the doped region 14 and the lower surface of the body region 13 may be selected according to practical situations, and is not limited herein.
Specifically, in the case of ensuring that the doping concentration of the doped region 14 is higher than that of the body region 13, the doping concentration of the doped region 14 may be selected according to practical situations, and is not limited herein.
Specifically, after forming the doped region 14, before forming the gate structure 15, the step of removing the shielding layer 2 is further included.
Specifically, as shown in fig. 8, in order to schematically illustrate the cross-sectional structure after the gate structure 15 is formed, the gate structure 15 includes a gate dielectric layer 151 and a gate conductive layer 152, the gate dielectric layer 151 is located on the inner wall and the bottom surface of the trench 12, the gate conductive layer 152 fills the trench 12, the gate dielectric layer 151 wraps the side wall and the bottom surface of the gate conductive layer 152, and the gate dielectric layer 151 covers the upper surface of the body region 13.
Specifically, the thickness of the gate dielectric layer 151 may be selected according to practical situations, and is not limited herein, while ensuring the performance of the device.
Specifically, the method for forming the gate dielectric layer 151 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods.
Specifically, the gate dielectric layer 151 is made of silicon nitride, silicon oxide or other suitable dielectric materials. In this embodiment, a thin silicon oxide layer is used as the gate dielectric layer 151.
Specifically, the method of forming the gate conductive layer 152 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the gate conductive layer 152 is made of polysilicon or other suitable conductive material.
Specifically, as shown in fig. 9, to form the source region 16, a cross-sectional structure of the source region 16 is schematically illustrated, and the method of forming the source region 16 includes ion implantation or other suitable method.
Specifically, the thickness of the source region 16 may be selected according to practical situations, and is not limited herein, where the thickness refers to the distance from the upper surface of the source region 16 to the lower surface of the source region 16, while ensuring the device performance; the doping concentration of the source region 16 may be selected according to practical situations, and is not limited here.
As an example, the upper surface of the doped region 14 contacts the lower surface of the source region 16 to reduce the resistance near the contact surface of the source region 16 and the body region 13.
Referring to fig. 10 to 17, the steps S5 and S6 are performed: forming an interlayer dielectric layer 3 above the source region 16, wherein the interlayer dielectric layer 3 covers the exposed surface of the gate structure 15, and a contact hole 31 penetrating through the interlayer dielectric layer 3 and the source region 16 is formed in the interlayer dielectric layer 3, the contact hole 31 and the gate structure 15 are separated by a preset distance, and the projection of the contact hole 31 in the horizontal direction intersects with the projection of the doped region 14 in the horizontal direction; an upper conductive layer 4 is formed in the contact hole 31 to fill the contact hole 31, and the upper conductive layer 4 covers the upper surface of the interlayer dielectric layer 3.
Specifically, as shown in fig. 10, to schematically illustrate the cross-sectional structure of the interlayer dielectric layer 3 after forming the interlayer dielectric layer 3, the method for forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.
Specifically, the thickness of the interlayer dielectric layer 3 may be selected according to the actual situation while ensuring the device performance, which is not limited.
Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride or other suitable dielectric materials.
Specifically, the method of forming the contact hole 31 includes dry etching, wet etching, or other suitable methods.
Specifically, the opening size of the contact hole 31 may be selected according to the actual situation, while ensuring the device performance, and is not limited.
Specifically, the contact hole 31 exposes the body region 13, i.e., the contact hole 31 exposes the upper surface of the body region 13 under the source region 16, or the bottom surface of the contact hole 31 extends into the body region 13 under the source region 16. In this embodiment, the bottom surface of the contact hole 31 extends into the body region 13 below the source region 16.
As an example, after forming the contact hole 31, before forming the conductive layer 4, a step of forming a second conductive type contact region 131 in the body region 13 under the bottom surface of the contact hole 31 is further included.
Specifically, as shown in fig. 11, to schematically illustrate the cross-sectional structure of the contact region 131 after forming the contact region 131, a method for forming the contact region 131 includes ion implantation or other suitable methods.
As an example, the doping concentration of the doped region 14 is smaller than the doping concentration of the contact region 131, so as to form an ohmic contact region, and reduce the contact resistance of the device.
Specifically, the doping concentration of the contact region 131 is higher than that of the doped region 14, and in the case that the contact region 131 forms an ohmic contact with an upper conductive layer (see fig. 12, which follows), the doping concentration of the contact region 131 may be selected according to the actual situation, which is not limited herein; the size and thickness of the contact region 131 may be selected according to practical situations, and are not limited herein, and the thickness refers to the distance between the upper surface of the contact region 131 and the lower surface of the contact region 131.
As an example, the doped region 14 is in contact with the contact region 131, i.e., the contact region 131 is in contact with the doped region 14 in the horizontal direction.
Specifically, as shown in fig. 12, in order to form the upper conductive layer 4, the method of forming the upper conductive layer 4 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the material of the upper conductive layer 4 may include one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or may be other suitable conductive materials.
Specifically, a step of forming a gate (not shown) electrically connected to the gate conductive layer 152 is further included to control conduction of a conductive channel in the power MOSFET device or to control conduction of a conductive channel in a MOSFET structure portion in the IGBT device.
Specifically, the material of the gate electrode includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, and may be other suitable conductive materials.
As an example, after forming the upper conductive layer 4, a step of forming a first conductive type buffer region 17 on the lower surface layer of the substrate 1 is further included.
Specifically, as shown in fig. 13, the buffer region 17 is formed to have a cross-sectional structure, and the doping concentration of the buffer region 17 is greater than that of the substrate 1.
Specifically, the method of forming the buffer region 17 includes ion implantation or other suitable method.
Specifically, in the case of ensuring the device performance and the doping concentration of the buffer region 17 being greater than the doping concentration of the substrate 1, the doping concentration of the buffer region 17 may be selected according to the actual situation, which is not limited herein.
Specifically, the thickness of the buffer region 17 may be selected according to practical situations, and is not limited herein, where the thickness refers to the distance from the upper surface of the buffer region 17 to the lower surface of the buffer region 17, while ensuring device performance.
As an example, the step of forming the buffer region 17 further includes a step of forming a lower conductive layer 5 on a lower surface of the buffer region 17.
Specifically, as shown in fig. 15, after the buffer region 17 is formed, the lower conductive layer 5 is formed on the lower surface of the buffer region 17, so as to obtain the power MOSFET device.
Specifically, in the power MOSFET device, since the doping concentration of the doped region 14 is higher than that of the body region 13, the resistance of the body region 13 is reduced, so that current preferentially enters the contact region 131 and the upper conductive layer 4 through the doped region 14, the voltage drop between the upper conductive layer 4 and the gate structure 15 is reduced, the conduction of the PN junction between the source region 16 and the body region 13 in the device is suppressed, that is, the conduction of the parasitic transistor in the device is suppressed, and the latch-up resistance of the power MOSFET device is improved.
As an example, the following steps are also included: forming a second conductive type collector region 18 on a lower surface layer of the buffer region 17; a lower conductive layer 5 is formed on the lower surface of the collector region 18.
Specifically, as shown in fig. 14, after the buffer region 17 is formed, the collector region 18 is formed on the lower surface layer of the buffer region 17, and the lower conductive layer 5 is formed on the lower surface of the collector region 18, so as to obtain the IGBT structure.
Specifically, forming the collector region 18 includes the steps of: ion implantation is carried out on the lower surface of the buffer region 17 so as to obtain a doped layer of the second conductivity type positioned on the lower surface layer of the buffer region 17; the second conductivity type doped layer is annealed to obtain the collector region 18.
Specifically, annealing the doped layer of the second conductivity type may redistribute impurity particles entering the lower surface layer of the buffer region 17, and simultaneously eliminate damage to the substrate 1 during the ion implantation process, so as to ensure the performance of the device.
Specifically, in the case of ensuring the device performance, the doping concentration of the collector region 18 may be selected according to the actual situation, and the thickness of the collector region 18 may be selected according to the actual situation without limitation, where the thickness refers to the distance between the upper surface of the collector region 18 and the lower surface of the collector region 18.
Specifically, as shown in fig. 16 and 17, the cross-sectional structure of one IGBT device and the cross-sectional structure of another IGBT device are formed, where the doped region 14 contacts the contact region 131, so that in the process of turning off the device, hole current preferentially passes through the doped region 14 and the contact region 131 to reach the upper conductive layer 4, and the doping concentration of the doped region 14 is higher, so that the resistance of the body region 13 is reduced, and then the voltage drop of the body region 13 is reduced, and the conduction of the PN junction between the source region 16 and the body region 13 is suppressed, thereby suppressing the conduction of the parasitic transistor in the device, and improving the latch-up resistance of the IGBT device.
Specifically, the method of forming the lower conductive layer 5 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
Specifically, the material of the lower conductive layer 5 may include one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or may be other suitable conductive materials.
In the method for manufacturing the semiconductor device structure of the embodiment, after the trench 12 is formed, ion implantation is performed on the inner wall of the trench 12 to form the doped region 14 at a preset distance from the inner wall of the trench 12, so that the formed doped region 14 is prevented from affecting the gate threshold voltage of the device; the doping concentration of the doped region 14 is higher than that of the body region 13, the doping concentration of the contact region 131 is higher than that of the doped region 14, the doped region 14 is in contact with the contact region 131, the resistance of the body region 13 is reduced, and simultaneously when the device is turned off, hole current in the device preferentially passes through the doped region 14, the contact region 131 and flows into the upper conductive layer 4, and the voltage drop of the body region 13 is reduced under the condition of the same current due to the reduction of the resistance of the body region 13, so that the conduction of a PN junction between the source region 16 and the body region 13 is inhibited, the starting of a parasitic transistor in the device is inhibited, and the latch-up resistance of the device is improved. In addition, the formation of the doped region 14 and the formation of the trench 12 share the shielding layer 2, so that a photomask for forming the doped region 14 is not required to be manufactured, the cost is saved, and the process steps are simple.
Example two
The embodiment provides a semiconductor device structure, as shown in fig. 12, which is a schematic view of a part of the structure of the semiconductor device structure, and includes a first conductive type substrate 1, a second conductive type body region 13, a trench 12, a second conductive type doped region 14, a gate structure 15, a first conductive type source region 16, an interlayer dielectric layer 3, a contact hole 31 and an upper conductive layer 4, wherein the body region 13 is located on the upper surface of the substrate 1, a plurality of trenches 12 are arranged in the body region 13 at intervals, and the opening of the trench 12 is upward; the doped region 14 is located in the body region 13 on at least one side of the trench 12, and the doped region 14 is spaced from the inner wall of the trench 12 by a preset distance; the gate structure 15 fills in the trench 12; the source region 16 is located on an upper surface layer of the body region 13 on at least one side of the gate structure 15, and the source region 16 is located in the body region 13 on the same side of the trench 12 as the doped region 14; the interlayer dielectric layer 3 is located above the body region 13, and the interlayer dielectric layer 3 covers the exposed surface of the gate structure 15; the contact hole 31 penetrates through the interlayer dielectric layer 3 and the source region 16, the contact hole 31 and the gate structure 15 are spaced by a preset distance, the projection of the contact hole 31 in the horizontal direction intersects with the projection of the doped region 14 in the horizontal direction, and the upper conductive layer 4 fills the contact hole 31 and covers the upper surface of the interlayer dielectric layer 3.
Specifically, the distance between the doped region 14 and the lower surface of the body region 13 is preset, so as to prevent the doped region 14 from being too small from being away from the lower surface of the body region 13, which affects the width of the depletion region of the PN junction between the substrate 1 (i.e., the drift region of the device) and the body region 13, and thus affects the voltage value required for conducting the PN junction between the substrate 1 and the body region 13, i.e., prevents the doped region 14 from affecting the voltage-withstanding performance of the device.
Specifically, the gate structure 15 includes a gate dielectric layer 151 and a gate conductive layer 152, the gate dielectric layer 151 is located on the inner wall and the bottom surface of the trench 12, the gate conductive layer 152 fills the trench 12, the gate dielectric layer 151 also covers the upper surface of the body region 13, and the gate dielectric layer 151 wraps the side wall and the bottom surface of the gate conductive layer 152.
Specifically, a contact region 131 of the second conductivity type is further disposed in the body region 13 below the contact hole 31, and the contact region 131 is in contact with the upper conductive layer 4 and the doped region 14.
Specifically, a gate is further disposed in the semiconductor device structure, and the gate is electrically connected to the gate conductive layer 152 in the gate structure 15.
Specifically, as shown in fig. 15, which is a schematic cross-sectional structure of a power MOSFET device, a buffer region 17 of a first conductivity type and a lower conductive layer 5 below the buffer region 17 are further disposed on a lower surface layer of the substrate 1, so as to obtain the power MOSFET device.
Specifically, as shown in fig. 16 and 17, a schematic cross-sectional structure of one IGBT device and a schematic cross-sectional structure of another IGBT device are respectively shown, a second conductivity type collector region 18 is further provided on the lower surface layer of the buffer region 17, and the lower conductive layer 5 contacts with the lower surface of the collector region 18, so as to obtain the IGBT device.
Specifically, the doped region 14 having a doping concentration higher than that of the body region 13 is disposed in the body region 13, and the doped region 14 is far away from the gate structure 15, so as to prevent the doped region 14 from affecting the gate threshold voltage of the device.
Specifically, since the doping concentration of the doped region 14 is higher than that of the body region 13, the doped region 14 contacts with the contact region 131, so that hole current preferentially flows into the upper conductive layer 4 from the doped region 14 and the contact region 131, the hole extraction path is optimized, meanwhile, since the doping concentration of the doped region 14 is higher, the resistance of the body region 13 is reduced, the voltage drop of the body region 13 is reduced, the conduction of the PN junction between the source region 16 and the body region 13 in the device is inhibited, the conduction of a parasitic transistor in the device is inhibited, and the latch-up resistance of the device is improved.
In the semiconductor device structure of this embodiment, the doped region 14 is disposed in the body region 13, and the doped region 14 is far away from the gate structure 15, so that the gate threshold voltage of the device is ensured, and by the disposition of the doped region 14, the resistance value of the body region 13 is reduced, the voltage drop of the body region 13 is reduced, and the conduction of the PN junction between the source region 16 and the body region 13 is suppressed, so that the latch-up resistance of the device is improved.
In summary, after forming the trench, the semiconductor device structure and the method for manufacturing the same of the present invention perform ion implantation on the inner wall of the trench to form a doped region in the body region at a predetermined distance from the inner wall of the trench, so as to avoid the doped region from affecting the gate threshold voltage of the device; because the concentration of the doped region is higher than that of the body region, and the doped region is in contact with the contact region, the extraction channel of hole current is optimized, when the device is turned off, the hole current preferentially enters the upper conductive layer through the doped region and the contact region, meanwhile, the doped region is formed, the resistance of the body region is reduced, the voltage drop of the body region is reduced, the PN junction between the source region and the body region is more difficult to conduct, the starting of a parasitic transistor in the device is restrained, and the latch-up resistance of the device is improved. In addition, the doped region and the trench share one shielding layer, so that the cost is saved, and the process steps are simple. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the semiconductor device structure is characterized by comprising the following steps:
providing a first conductive type substrate, and forming a second conductive type epitaxial layer on the upper surface of the substrate;
forming a patterned shielding layer on the upper surface of the epitaxial layer, forming grooves which are arranged at intervals and have upward openings in the epitaxial layer based on the patterned shielding layer, wherein the parts of the epitaxial layer, which are positioned on two sides of the grooves, are used as body regions;
ion implantation is carried out on the inner wall of the groove based on the shielding layer so as to form a second conductive type doped region in the body region of at least one side of the groove, and the doped region is spaced from the inner wall of the groove by a preset distance;
forming a gate structure in the trench, forming a source region of a first conductivity type on an upper surface layer of the body region on at least one side of the gate structure, wherein the source region and the doped region are located in the body region on the same side of the trench;
forming an interlayer dielectric layer above the source region, wherein the interlayer dielectric layer covers the exposed surface of the gate structure, a contact hole penetrating through the interlayer dielectric layer and the source region is formed in the interlayer dielectric layer, the contact hole and the gate structure are separated by a preset distance, and the projection of the contact hole in the horizontal direction is intersected with the projection of the doped region in the horizontal direction;
and forming an upper conductive layer filling the contact hole in the contact hole, wherein the upper conductive layer covers the upper surface of the interlayer dielectric layer.
2. The method of fabricating a semiconductor device structure of claim 1, wherein: the lower surface of the doped region is spaced a preset distance from the lower surface of the body region.
3. The method of fabricating a semiconductor device structure of claim 1, wherein: the ion implantation angle for forming the doped region is in the range of 30-60 degrees.
4. The method of fabricating a semiconductor device structure of claim 1, wherein: after forming the contact hole, before forming the conductive layer, a step of forming a second conductive type contact region in the body region below a bottom surface of the contact hole is further included.
5. The method for manufacturing a semiconductor device structure according to claim 4, wherein: the doping concentration of the doped region is smaller than that of the contact region, and the doping concentration of the body region is smaller than that of the doped region.
6. The method for manufacturing a semiconductor device structure according to claim 4, wherein: the doped region is in contact with the contact region.
7. The method of fabricating a semiconductor device structure of claim 1, wherein: after the upper conductive layer is formed, a step of forming a first conductive type buffer region on the lower surface layer of the substrate is further included.
8. The method of fabricating a semiconductor device structure of claim 7, wherein: the step of forming the buffer region further comprises the step of forming a lower conductive layer on the lower surface of the buffer region.
9. The method of fabricating a semiconductor device structure of claim 7, further comprising the steps of: forming a second conductivity type collector region on the lower surface layer of the buffer region; and forming a lower conductive layer on the lower surface of the collector region.
10. A semiconductor device structure, comprising:
a first conductivity type substrate;
a second conductivity type body region on an upper surface of the substrate;
the grooves are arranged in the body region at intervals, and the openings of the grooves are upward;
a doped region of a second conductivity type located in the body region on at least one side of the trench, the doped region being spaced a predetermined distance from an inner wall of the trench;
a gate structure filled in the trench;
a source region of a first conductivity type located on an upper surface layer of the body region on at least one side of the gate structure, and the source region and the doped region are located in the body region on the same side of the trench;
the interlayer dielectric layer is positioned above the body region and covers the exposed surface of the gate structure;
the contact hole penetrates through the interlayer dielectric layer and the source region, the contact hole and the grid structure are spaced at preset distance, the projection of the contact hole in the horizontal direction is intersected with the projection of the doped region in the horizontal direction, and the upper conductive layer fills the contact hole and covers the upper surface of the interlayer dielectric layer.
CN202210854835.8A 2022-07-18 2022-07-18 Semiconductor device structure and preparation method thereof Pending CN117457709A (en)

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US6822288B2 (en) * 2001-11-20 2004-11-23 General Semiconductor, Inc. Trench MOSFET device with polycrystalline silicon source contact structure
US7678654B2 (en) * 2006-06-30 2010-03-16 Qimonda Ag Buried bitline with reduced resistance
US7633121B2 (en) * 2007-10-31 2009-12-15 Force-Mos Technology Corp. Trench MOSFET with implanted drift region
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US8264035B2 (en) * 2010-03-26 2012-09-11 Force Mos Technology Co., Ltd. Avalanche capability improvement in power semiconductor devices
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