CN117423692A - Chip and preparation method - Google Patents

Abstract

Embodiments of the present application provide a chip. The chip includes a substrate. A first through hole is opened in the substrate and penetrates the upper and lower surfaces of the substrate. At least two layers of doping materials are sequentially attached to the inner wall and bottom of the first through hole. , the at least two layers of doping materials include P-type doping materials and N-type doping materials, the first through hole is also filled with a first conductive material, the first conductive material and the first doping material in the at least two layers of doping materials The miscellaneous materials are in contact with each other; a first conductive circuit and a functional circuit are provided on the upper surface of the substrate, and the first conductive circuit is connected to the first conductive material and the functional circuit; a second conductive circuit is provided on the lower surface of the substrate, and the second conductive circuit is In contact with the second doped material in at least two layers of doped materials, the chip provided by the embodiment of the present application can increase the proportion of the area occupied by the PN junction in the electrostatic protection device within the unit area of the chip, so as to improve the electrostatic protection device. s efficiency.

Description

Chips and preparation methods

Technical field

Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a chip and a preparation method.

Background technique

With the development of semiconductor technology, the integration level of transistors on the chip is getting higher and higher, so the processing cost per unit area of the chip is also increasing. In order to reduce chip production costs while ensuring high performance of the chip, the industry proposes to combine modules with high production costs that are used to implement the core functions of the chip (such as modules that implement digital processing functions in the chip, or modules that implement storage functions) with Modules with low production costs and used to implement chip auxiliary functions or peripheral functions (such as electrostatic protection modules used to resist electrostatic discharge events that may occur at any time from the production process to use) are prepared separately, and then the two are combined using advanced packaging technology. Modules are packaged together to form a packaged system.

In the prior art, diodes are usually used as electrostatic protection devices, and the diodes are usually arranged between the signal terminals of core functional modules and public signal lines (such as public ground lines or power lines). Usually, the electrostatic protection capability of a diode is determined by the size of the PN junction area during the production process. However, in the existing technology, when an independent preparation process is used to prepare the electrostatic protection module, the area occupied by the PN junction per unit area of the chip is too small. If you want to increase the PN junction area, you need to occupy more area of the chip. , reducing chip utilization. Therefore, how to increase the proportion of the area occupied by the PN junction in the electrostatic protection device within the unit area of the chip to improve the efficiency of the electrostatic protection device has become a problem that needs to be solved.

Contents of the invention

By using the chip and the preparation method shown in this application, the proportion of the area occupied by the PN junction in the electrostatic protection device within the unit area of the chip can be increased to improve the efficiency of the electrostatic protection device.

In order to achieve the above purpose, this application adopts the following technical solutions:

In a first aspect, embodiments of the present application provide a chip. The chip includes a substrate. A first through hole is opened in the substrate and penetrates the upper and lower surfaces of the substrate. The inner wall and bottom of the first through hole are sequentially At least two layers of doping materials are attached, and the at least two layers of doping materials include P-type doping materials and N-type doping materials. The first through hole is also filled with a first conductive material, and the first through hole is filled with a first conductive material. A conductive material is in contact with the first doping material in the at least two layers of doping materials; a first conductive line and a functional circuit are provided on the upper surface of the substrate, the first conductive line and the first The conductive material is connected to the functional circuit; a second conductive line is provided on the lower surface of the substrate, and the second conductive line is in contact with the second doping material in the at least two layers of doping materials.

In the chip provided by the embodiment of the present application, a through hole is opened in the chip substrate, and at least two layers of polysilicon are attached to the bottom end and side walls of the through hole. The at least two layers of polysilicon include P-type doped polysilicon and N-type doped polysilicon. Hybrid polysilicon, P-type doped polysilicon and N-type doped polysilicon form a PN junction. Compared with the area of the PN junction of the electrostatic protection diode in the prior art which is only the cross-sectional area of the through hole, the embodiments of the present application provide The area of the PN junction of the electrostatic protection transistor in the chip is the area of the bottom end and side wall of the through hole. Therefore, compared with the existing technology, the area of the PN junction in the chip per unit area can be increased. In addition, since in the embodiment of the present application, both P-type doped polysilicon and N-type doped polysilicon are attached to the bottom end and sidewall of the through hole on the substrate, that is, the N-type will not be caused by the excessive thickness of the substrate of the chip. If the doped silicon substrate is too thick, the on-resistance of the electrostatic protection transistor can be reduced, which in turn can reduce the voltage clamping capability of the electrostatic protection transistor. In summary, the electrostatic protection transistor in the chip provided by the embodiment of the present application can improve the electrostatic protection performance.

Based on the first aspect, in a possible implementation, the substrate is further provided with a second through hole penetrating the upper and lower surfaces of the substrate, and the second through hole is filled with a second conductive material; The functional circuit is connected to the second conductive line through the second conductive material.

Based on the first aspect, in a possible implementation, the chip includes a diode, and two layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the first doping material is P-type. Doping material, the second doping material is an N-type doping material.

Based on the first aspect, in a possible implementation, the chip includes an NPN transistor, and three layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the three layers of doping material include N Type doping material, P-type doping material and N-type doping material; wherein, the first doping material is an N-type doping material, and the second doping material is an N-type doping material.

Based on the first aspect, in a possible implementation, the chip includes a PNP transistor, and three layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the three layers of doping material include P Type doping material, N-type doping material and P-type doping material; wherein, the first doping material is a P-type doping material, and the second doping material is a P-type doping material.

Based on the first aspect, in a possible implementation, the chip includes a thyristor, and four layers of doping material are sequentially attached to the inner wall and bottom of the first through hole, and the four layers of doping material include N-type doping material, P-type doping material, N-type doping material and P-type doping material; wherein, the first doping material is P-type doping material, and the second doping material is N-type Doping materials.

Based on the first aspect, in a possible implementation, the chip further includes a substrate, and the substrate is disposed on the substrate.

Based on the first aspect, in a possible implementation, the N-type doped material is formed by doping silicon material with phosphorus element; the P-type doped material is formed by doping silicon material with boron. formed from elements.

In a second aspect, embodiments of the present application provide a method for preparing a chip. The method includes: providing a substrate; forming a first through hole on the substrate, wherein the first through hole penetrates the At least two layers of doping materials are attached to the upper and lower surfaces of the substrate, the inner wall and the bottom of the first through hole in sequence, and the at least two layers of doping materials include P-type doping materials and N-type doping materials, so The first through hole is also filled with a first conductive material, and the first conductive material is in contact with the first doping material in the at least two layers of doping materials; a first conductive material is formed on the upper surface of the substrate. A conductive line, the first conductive line is connected to the first conductive material; a second conductive line is formed on the lower surface of the substrate, the second conductive line is connected to the at least two layers of doped materials. The second doped material is in contact; a functional circuit is provided on the upper surface of the substrate, and the functional circuit is connected to the first conductive line.

Based on the second aspect, in a possible implementation, forming a first through hole on the substrate includes: forming a first through hole and a second through hole on the substrate; wherein, The second through hole penetrates the upper and lower surfaces of the substrate, the second through hole is filled with a second conductive material, and the functional circuit is connected to the second conductive line through the second conductive material.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. , for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative labor.

Figure 1A is a circuit diagram of a chip with electrostatic protection in the prior art provided by an embodiment of the present application;

Figure 1B is a schematic structural diagram of the diode shown in Figure 1A;

Figure 2 is a schematic structural diagram of the chip 100 provided by the embodiment of the present application;

Figure 3 is a circuit diagram of the chip 100 shown in Figure 2 provided by an embodiment of the present application;

Figure 4 is a schematic structural diagram of the chip 200 provided by the embodiment of the present application;

Figure 5 is a schematic structural diagram of a specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;

Figure 6 is a circuit diagram of the chip 100 shown in Figure 5 provided by an embodiment of the present application;

Figure 7 is a schematic structural diagram of another specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;

Figure 8 is a circuit diagram of the chip 100 shown in Figure 7 provided by an embodiment of the present application;

Figure 9 is a schematic structural diagram of another specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;

Figure 10 is a circuit diagram of the chip 100 shown in Figure 9 provided by an embodiment of the present application;

Figure 11 is a schematic structural diagram of another specific embodiment corresponding to the chip 100 shown in Figure 2 provided by the embodiment of the present application;

Figure 12 is a circuit diagram of the chip 100 shown in Figure 11 provided by an embodiment of the present application;

Figure 13 is a flow chart of the preparation method of the chip 100 shown in Figure 6 provided by the embodiment of the present application;

FIGS. 14A to 14H are schematic structural diagrams of the chip 100 shown in FIG. 6 during the preparation process.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

"First", "second" and similar words mentioned herein do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, similar words such as "a" or "one" do not indicate a quantitative limit, but rather indicate the presence of at least one. Words such as "connection" or "coupling" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect, which are equivalent to connection in a broad sense.

In the embodiments of this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "such as" in the embodiments of the present application is not to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the words "exemplary" or "such as" is intended to present the concept in a concrete manner. In the description of the embodiments of this application, unless otherwise specified, the meaning of “plurality” refers to two or more. For example, multiple pins refers to two or more pins.

Please refer to FIG. 1A , which is a circuit diagram of a chip with electrostatic protection in the prior art provided by an embodiment of the present application. In Figure 1A, a chip with electrostatic protection includes power lines, ground wires, signal lines, diodes P1 and P2 for electrostatic protection, and protected functional circuits. Among them, the diode P1 and the diode P2 are respectively arranged between the ground line and the signal line, and the signal line and the power line. When a positive electrostatic pulse enters the chip through the signal line, the current will be discharged to the power line along the diode P2; when a negative electrostatic pulse enters the chip through the signal line, the current will flow out from the ground along the diode P1.

In the specific preparation process of a chip with electrostatic protection in the prior art, a through hole is provided in the silicon substrate of the chip, and the diode P1 and the diode P2 are embedded in the through hole (TSV), as shown in Figure 1B. In FIG. 1B , the chip includes a substrate S, a P-type doped silicon substrate embedded in the substrate S, and an N-type doped silicon substrate. A PN junction is formed between the P-type doped silicon substrate and the N-type doped silicon substrate. The metal M1 in contact with the P-type doped silicon substrate leads to the anode of the diode; the metal M2 in contact with the N-type doped silicon substrate leads to the cathode of the diode. In addition, a barrier layer is also provided between the N-type doped silicon substrate and the substrate S, and between the P-type doped silicon substrate and the N-type doped silicon substrate. As can be seen from Figure 1B, in the prior art, the P-type doped silicon substrate is placed at the bottom, the N-type doped silicon substrate is placed on the P-type doped silicon substrate, and the P-type doped silicon substrate The part in contact with the N-type doped silicon substrate (that is, the PN junction area) is the cross-sectional area of the through hole. This results in the PN junction area being too small per unit area of the chip, thereby reducing the electrostatic protection efficiency of the diode. . In addition, the P-type doped silicon substrate and the N-type doped silicon substrate are arranged up and down along the thickness direction of the substrate S. When the substrate S is too thick, the N-type doped silicon substrate is also too thick, which means This results in a large on-resistance of the diode, thereby reducing the voltage clamping capability of the diode.

Based on the above-mentioned existing technology, the problem of the PN junction area of the electrostatic protection diode per unit area of the chip is too small, and the problem that the N-type doped silicon substrate is too thick when the substrate S is too thick, this application In the chip provided by the embodiment, a through hole is opened in the chip substrate, and at least two layers of polysilicon are attached to the bottom end and side walls of the through hole. The at least two layers of polysilicon include P-type doped polysilicon and N-type doped polysilicon. , P-type doped polysilicon and N-type doped polysilicon form a PN junction. Compared with the area of the PN junction of the electrostatic protection diode in the prior art, which is only the cross-sectional area of the through hole, the chip provided by the embodiment of the present application The area of the PN junction of the electrostatic protection transistor is the area of the bottom end and side wall of the through hole, so compared with the existing technology, the area of the PN junction in the chip per unit area can be increased. In addition, since in the embodiment of the present application, both P-type doped polysilicon and N-type doped polysilicon are attached to the bottom end and sidewall of the through hole on the substrate, that is, the N-type will not be caused by the excessive thickness of the substrate of the chip. If the doped silicon substrate is too thick, the on-resistance of the electrostatic protection transistor can be reduced, which in turn can reduce the voltage clamping capability of the electrostatic protection transistor. In summary, the electrostatic protection transistor in the chip provided by the embodiment of the present application can improve the electrostatic protection performance. The chip provided by the embodiment of the present application will be described in detail below through the embodiments shown in FIGS. 2 to 11 .

Please refer to FIG. 2 , which is a schematic structural diagram of the chip 100 provided by an embodiment of the present application. As shown in FIG. 2 , the chip 100 may be a system in package chip. The chip 100 includes a substrate 10 and a functional circuit 11 disposed on the substrate 10 . The substrate 10 may also be called a silicon wafer, and the material of the substrate 10 is silicon. The substrate 10 is also provided with a through hole 12 , and the through hole 12 is used to embed an electrostatic protection transistor to protect the functional circuit 11 . In addition, a conductive trace 13 is also provided on the upper surface of the substrate 10 for connecting the functional circuit 11 and the electrostatic protection transistor in the through hole 12 . In addition, the substrate 10 is also provided with a through hole for connecting the functional circuit 11 to the common ground. The through hole can be disposed under the functional circuit 11 and covered by the functional circuit 11 . The lower surface of the substrate 10 is also provided with conductive lines for connecting the electrostatic protection transistor and the functional circuit 11 to a common ground. The planar circuit structure of the chip 100 shown in FIG. 2 is shown in FIG. 3 . Among them, the through holes on the substrate 10 for connecting the functional circuit 11 to the common ground are reference numerals 14 shown in FIG. 3 , and the conductive circuits on the lower surface of the substrate 10 are reference numerals 15 shown in FIG. 3 .

The chip 100 shown in Figure 2 is a bare chip formed directly on the substrate 10. The chip provided in the embodiment of the present application can also be a chip packaging structure formed after being packaged with a substrate, as shown in Figure 4. Figure 4 is a schematic diagram of this application. The application embodiment provides a schematic structural diagram of the chip 200. Compared with the chip 100 shown in FIG. 2 , the chip 200 shown in FIG. 4 also includes a substrate 20 , and the chip 100 shown in FIG. 2 is disposed on the substrate 20 . A plurality of pins 21 are provided on the substrate 20. Each lead-out terminal of the functional circuit 11, each lead-out terminal of the electrostatic protection transistor embedded in the through hole 12, the upper surface conductive circuit 13 and the lower surface conductive circuit 15 on the substrate 10 are respectively Lead to each pin 21 of the substrate 20 to realize board-level connection between the chip 200 and other chips or components.

In the embodiment of the present application, the functional circuit 11 can be a memory (Memory), a discrete device, an Application Processor (AP), a Micro-Electro-Mechanical System (MEMS), a microwave radio frequency chip, or an application-specific integrated circuit. (ApplicationSpecific Integrated Circuit, ASIC for short), etc. The functional circuit 11 can be pre-integrated on one or more bare chips and then installed on the chip 100 . In specific applications, the above-mentioned application processing chips or application-specific integrated circuits can be central processing units (CPU), graphics processing units (GPU), artificial intelligence processors (such as neural network processors), integrated computing Amplifiers, filters, etc. The memory may be a cache, a random access memory (Random Access Memory, RAM), a read only memory (Read Only Memory, ROM), or other memory.

The electrostatic protection transistor provided by the embodiment of the present application may be a diode, a triode or a thyristor. The structure of the electrostatic protection transistor provided by the embodiment of the present application and its connection relationship with the functional circuit 11 in the chip 100 will be described in more detail below through the examples shown in FIGS. 5 to 11 .

Referring to FIG. 5 , FIG. 5 is a schematic diagram of a planar circuit structure in which the electrostatic protection transistor is a diode in the chip 100 provided by the embodiment of the present application. In this case, the chip 100 includes a diode P1 and a diode P2. The diode P1 is disposed between the conductive line 13 and the conductive line 15 (ie, the common ground Gnd), and the diode P2 is disposed between the conductive line 13 and the power line Pdd. In addition, the functional circuit 11 is connected to the conductive line 15 and the power supply line Pdd, respectively. The structure of the chip 100 shown in FIG. 5 is shown in FIG. 6 . It should be noted that FIG. 6 only schematically shows the structure of the diode P1 and the situation in which the functional circuit 11 is connected to the conductive line 15 through a through hole. The structure of the diode P2 and the structure in which the functional circuit 11 is connected to the power line Vdd through the through hole are respectively the same as the structure of the diode P1 and the structure in which the functional circuit 11 is connected to the conductive line 15 through the through hole.

Please continue to refer to FIG. 6 . In FIG. 6 , the chip 100 includes a substrate 10 . The substrate 10 is provided with a through hole 12 penetrating the upper and lower surfaces of the substrate 10 . The through hole 12 is formed by etching the substrate 10 . The via 12 is isolated from the substrate 10 by a barrier layer 21 . The material of the barrier layer 21 may include, but is not limited to: silicon nitride (SiNx), titanium nitride (TiN) or titanium tungsten alloy (TiW). N-type semiconductor material 22 and P-type semiconductor material 23 are sequentially deposited on the inner wall and bottom of the through-hole 12 . The N-type semiconductor material 22 is close to the inner wall of the through-hole 12 , that is, close to the barrier layer 21 , and the P-type semiconductor material 23 is close to the inner wall of the through-hole 12 . attached to the N-type semiconductor material 22. The N-type semiconductor material 22 is made by doping polysilicon with phosphorus element, and the P-type semiconductor material 23 is made by doping polysilicon with boron element. Thus, a PN junction is formed between the N-type semiconductor material 22 and the P-type semiconductor material 23 . The through hole 12 is also filled with conductive material 24 , and the conductive material 24 is in contact with the P-type semiconductor material 23 . The conductive material 24 may include, for example, but is not limited to: metal materials, heavily doped polysilicon materials, and the like. The upper surface of the substrate 10 is also provided with conductive lines 13 , which cover the through holes 12 and are connected to the conductive material 24 . The conductive lines 13 are isolated from the N-type semiconductor material 22 and the P-type semiconductor material 23 by insulating materials. The insulating material is silicon oxide, for example. The conductive line 13 is used not only to lead out the anode of the diode P1 but also to connect with the functional circuit 11 . In addition, a conductive trace 15 is provided on the lower surface of the substrate 10 , and the conductive trace 15 covers the through hole 12 and is in contact with the N-type semiconductor material 22 . The conductive trace 15 is used not only to draw out the cathode of the diode P1 but also as the common ground Gnd of the chip 100 . In FIG. 6 , the upper surface of the substrate 10 is also provided with a functional circuit 11 , and the substrate 10 is also provided with a through hole 14 penetrating the upper and lower surfaces of the substrate 10 . Via 14 is isolated from substrate 10 by barrier layer 26 . The through hole 14 is filled with conductive material 25. The conductive material 25 in the through hole 14 is connected to the functional circuit 11 and the conductive line 15. The functional circuit 11 is connected to the conductive line 15 through the conductive material 25 in the through hole 14, that is, connected to common ground Gnd.

As can be seen from Figure 6, the chip 100 provided by the embodiment of the present application opens a through hole 12 in the substrate of the chip 100, and attaches N-type semiconductor material 22 and P-type semiconductor material 22 to the bottom end and side walls of the through hole 12. A PN junction is formed between the semiconductor material 23, the N-type semiconductor material 22 and the P-type semiconductor material 23. Compared with the area of the PN junction of the electrostatic protection diode in the prior art which is only the cross-sectional area of the through hole, this application implements The area of the PN junction of the diode P1 in the chip 100 provided in the example is the area of the bottom end and the side wall of the through hole. Therefore, compared with the existing technology, the area of the PN junction in the chip per unit area can be increased. In addition, since in the embodiment of the present application, the N-type semiconductor material 22 and the P-type semiconductor material 23 are both attached to the bottom end and side walls of the through hole 12, that is, there will be no problem due to the substrate 10 of the chip 100 being too thick. In the technology, the N-type silicon substrate is deposited too thickly, which can reduce the on-resistance of the electrostatic protection transistor, thereby reducing the voltage clamping capability of the electrostatic protection transistor. In summary, the diode P1 in the chip 100 provided by the embodiment of the present application can improve the electrostatic protection performance of the chip 100 .

When the electrostatic protection transistor is a triode, please continue to refer to FIG. 7 , which is a schematic diagram of the planar circuit structure of the chip 100 provided by the embodiment of the present application. In the chip 100, as shown in FIG. 7, the chip 100 includes a transistor G1 and a functional circuit 11. Transistor G1 is an NPN transistor. The transistor is arranged between the conductive line 13 and the conductive line 15 . The functional circuit 11 is connected to the common ground Gnd via a conductive line 15 . The structure of the chip 100 shown in FIG. 7 is as shown in FIG. 8 . The chip 100 shown in FIG. 8 includes a substrate 10, a through hole 12 penetrating the upper and lower surfaces of the substrate 10, a through hole 14 penetrating the upper and lower surfaces of the substrate 10, a conductive line 13 provided on the upper surface of the substrate 10, and a conductive line 13 provided on the upper surface of the substrate 10. The conductive circuit 15 on the lower surface of the substrate 10 and the functional circuit 11 provided on the substrate 10 . Different from the chip 100 shown in FIG. 6 , N-type semiconductor material 32 , P-type semiconductor material 33 and N-type semiconductor material 34 are sequentially deposited on the inner wall and bottom of the through hole 12 . The N-type semiconductor material 32 is close to the inner wall of the through hole 12 (that is, close to the barrier layer 31 ), the P-type semiconductor material 33 is attached to the N-type semiconductor material 32 , and the N-type semiconductor material 34 is attached to the P-type semiconductor material 33 superior. Therefore, a PN junction is formed between the N-type semiconductor material 32 and the P-type semiconductor material 33 , and a PN junction is formed between the P-type semiconductor material 33 and the N-type semiconductor material 34 . N-type semiconductor material 32 and N-type semiconductor material 34 are realized by doping polysilicon with phosphorus element, and P-type semiconductor material 33 is realized by doping polysilicon with boron element. In addition, the conductive line 13 in Figure 8 is connected with the conductive material 35 filled in the through hole 12 to lead out the collector of the transistor G1; the conductive line 15 in Figure 8 is in contact with the N-type semiconductor material 32 to lead out The emitter of transistor G1. In addition, other structures in the chip 100 shown in FIG. 8 and the connection relationships between the structures are the same as the structure of the chip 200 shown in FIG. 6 and the connection relationships between the structures. Please refer to FIG. 6 for details. The relevant description of the chip 200 shown will not be described again.

In the chip 100 shown in FIGS. 7 and 8 , the electrostatic protection transistor is an NPN transistor. In a possible implementation manner, the electrostatic protection transistor may also be a PNP transistor. When the electrostatic protection transistor is a PNP transistor, the planar circuit structure schematic diagram of the chip 100 is shown in FIG. 9 , and FIG. 10 is a schematic structural diagram of the chip 100 shown in FIG. 9 . Different from the chip 100 shown in FIGS. 7 and 8 , the chip 100 shown in FIGS. 9 and 10 is a PNP transistor. Therefore, in FIG. 10 , P-type semiconductor material 42 , N-type semiconductor material 43 and P-type semiconductor material 44 are sequentially deposited on the inner wall and bottom of the through hole 12 . The P-type semiconductor material 42 is close to the inner wall of the through hole 12 (that is, close to the barrier layer 41 ), the N-type semiconductor material 43 is attached to the P-type semiconductor material 42 , and the P-type semiconductor material 44 is attached to the N-type semiconductor material 43 superior. Therefore, a PN junction is formed between the P-type semiconductor material 42 and the N-type semiconductor material 43 , and a PN junction is formed between the N-type semiconductor material 43 and the P-type semiconductor material 44 . In addition, the conductive line 13 in Figure 8 is connected with the conductive material 45 filled in the through hole 12 to lead out the emitter of the transistor G1; the conductive line 15 in Figure 8 is in contact with the P-type semiconductor material 42 to lead out The collector of transistor G1. In addition, other structures in the chip 100 shown in FIG. 10 and the connection relationships between the structures are the same as the structure of the chip 100 shown in FIG. 7 and the connection relationships between the structures. Please refer to FIG. 7 for details. The relevant descriptions of the chip 100 shown will not be described again.

Please continue to refer to FIG. 11 , which is a schematic diagram of the planar circuit structure of the chip 100 provided by the embodiment of the present application. In the chip 100, the electrostatic protection transistor is a thyristor G3. As shown in FIG. 11 , the chip 100 includes a thyristor G3 and a functional circuit 11 . SCR G3 includes NPN transistor and PNP transistor. The emitter of the NPN transistor is connected to the common ground Gnd through the conductive line 15, the collector of the NPN transistor is connected to the base of the PNP transistor, and the base of the NPN transistor is connected to the collector of the PNP transistor. The emitter is connected to the functional circuit 11 via a conductive line 13 . Thus, three PN junctions are included in the thyristor G3. The functional circuit 11 is connected to the common ground Gnd via a conductive line 15 . A cross-sectional view of chip 100 is shown in FIG. 12 . The chip 100 shown in Figure 12 includes a substrate 10, a through hole 12 penetrating the upper and lower surfaces of the substrate 10, a through hole 14 penetrating the upper and lower surfaces of the substrate 10, a conductive line 13 provided on the upper surface of the substrate 10, and a conductive line 13 provided on the upper surface of the substrate 10. The conductive circuit 15 on the lower surface of the base 10 and the functional circuit 11 provided on the substrate 10 . Different from the chips shown in the above embodiments, N-type semiconductor material 52 , P-type semiconductor material 53 , N-type semiconductor material 54 and P-type semiconductor material 55 are deposited in sequence on the inner wall and bottom of the through hole 12 . The N-type semiconductor material 52 is close to the inner wall of the through hole 12 (that is, close to the barrier layer 51 ), the P-type semiconductor material 53 is attached to the N-type semiconductor material 52 , and the N-type semiconductor material 54 is attached to the P-type semiconductor material 53 On the top, the P-type semiconductor material 55 is attached to the N-type semiconductor material 54 . Therefore, a PN junction is formed between the N-type semiconductor material 52 and the P-type semiconductor material 53, a PN junction is formed between the P-type semiconductor material 53 and the N-type semiconductor material 54, and a PN junction is formed between the N-type semiconductor material 54 and the P-type semiconductor material 55. PN junction. N-type semiconductor material 52 and N-type semiconductor material 54 are realized by doping polysilicon with phosphorus element, and P-type semiconductor material 53 and P-type semiconductor material 55 are realized by doping polysilicon with boron element. In one possible implementation, the N-type semiconductor material 52 is made by heavily doping polysilicon with phosphorus elements, and the P-type semiconductor material 55 is made by heavily doping polysilicon with boron elements. The above-mentioned heavily doped concentration is greater than Equal to 1E18cm^-3. In addition, the conductive circuit 13 in Figure 12 is connected with the P-type semiconductor material 55 through the conductive material 56 filled in the through hole 12 to lead out the electrode in the thyristor G3 connected to the functional circuit 11; the conductive circuit in Figure 12 The line 15 is in contact with the N-type semiconductor material 52 to lead out the electrode in the thyristor G3 that is connected to the common ground Gnd. In addition, other structures in the chip 100 shown in FIG. 12 and the connection relationships between the structures are the same as the structure of the chip 100 shown in FIG. 6 and the connection relationships between the structures. Please refer to FIG. 6 for details. The relevant description of the chip 200 shown will not be described again.

Based on the structure of the chip as described above, embodiments of the present application also provide a method of manufacturing a chip. Taking the preparation of the chip 100 as shown in Figure 6 as an example, the process of preparing the chip will be described in conjunction with the process 1300 shown in Figure 13. The process is described in detail. The process flow 1300 includes the following steps:

Step 1301: Provide a substrate 10, and etch the substrate 10 to form deep trenches 1311 and 1312. The material of the substrate 10 may be silicon, which may also be called a wafer. In this step, a patterned photoresist 1313 can be deposited on the surface of the substrate 10, and the substrate 10 can be etched using reactive ions or particle beams. Among them, the portion of the substrate 10 that is not coated with the photoresist 1313 is etched to form deep grooves 1311 and 1312 . The photoresist is then removed using an organic solvent. As shown in Figure 14A.

Step 1302: Form barrier layers 21 on the side walls of the deep trench 1311 and the deep trench 1312 respectively. The material of the barrier layer 21 may include, but is not limited to: silicon nitride (SiNx), titanium nitride (TiN) or titanium tungsten (TiW) alloy. Taking the barrier layer 21 as TiN as an example, in this step, chemical vapor deposition (CVD, Chemical Vapor Deposition) or physical vapor deposition (PVD, Physical Vapor Deposition) or other processes can be used to deposit TiN on the exposed surface of the substrate 10 ; Then, use a reactive ion or particle beam process to etch away the TiN on the upper surface of the substrate 10, the TiN on the bottom of the deep trench 1311, and the TiN on the bottom of the deep trench 1312, leaving the TiN on the side walls of the deep trench 1311 and the deep trench 1312. , to form the barrier layer 21 . As shown in Figure 14B.

Step 1303, deposit filling medium 1333 in deep trench 1311 and deep trench 1312. The material of the filling medium 1333 may include but is not limited to SiOx or SiNx. In this step, a CVD process is first used to deposit a filling medium 1333 on the deep grooves 1311 and 1312 and the upper surface of the substrate 10; then, a chemical mechanical polishing (CMP, Chemical Mechanical Polishing) process is used to remove excess material on the upper surface of the substrate 10. of filling medium 1333, leaving only the filling medium 1333 in the deep grooves 1311 and 1312. As shown in Figure 14C.

Step 1304: Etch the filling medium 1333 in the deep trench 1311. In this step, photoresist 1341 is first coated on the upper surface of substrate 10 . The photoresist 1341 covers the opening of the deep groove 1312, and the opening of the deep groove 1311 is not covered with the photoresist; then, chemical etching is used to etch away the filling medium 1333 in the deep groove 1311. Since the deep groove 1312 The filling medium 1333 is protected by the photoresist 1341 and is not etched away; finally, the photoresist 1341 on the substrate 10 is removed. As shown in Figure 14D.

Step 1305: N-type semiconductor material 22 and P-type semiconductor material 23 are formed on the sidewalls and bottom of the deep trench 1311. In this step, a low-pressure chemical vapor deposition (LPCVD, low-pressure chemical vapordeposition) or plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition) process can first be used to deposit the film on the exposed surface of the substrate 10 and the deep groove 1311 Polycrystalline silicon or amorphous silicon is deposited on the surface. During the deposition process of polycrystalline silicon or amorphous silicon, by controlling the impurity source gas content in the reaction chamber, in-situ doping of polycrystalline silicon or amorphous silicon can be achieved. In specific implementation, during the polysilicon deposition process, phosphorus-containing gas can be first introduced to form N-type polysilicon, that is, N-type semiconductor material 22, on the side walls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the gas containing phosphorus can be introduced. Boron gas is used to form P-type polysilicon, that is, P-type semiconductor material 23, on N-type polysilicon. Then, a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 . Therefore, N-type semiconductor material 22 and P-type semiconductor material 23 are formed on the sidewalls and bottom of the deep trench 1311, that is, a PN junction is formed. As shown in Figure 14E.

Step 1306: Etch the filling medium 1333 in the deep trench 1312. In this step, chemical etching may be used to etch away the filling medium 1333 in the deep trench 1312 . As shown in Figure 14F.

Step 1307: Fill the deep grooves 1311 and 1312 with metal 24 and metal 25 respectively. In this step, a sputtering process can first be used to electroplat a layer of titanium seed layer on the upper surface of the deep trench 1311, the deep trench 1312 and the substrate 10, and then electroplating is used to deposit metallic copper; then, the CMP process is used to remove the upper surface of the substrate 10 metal; then the exposed silicon surface and copper surface are oxidized. Specifically, the P-type semiconductor material and N-type semiconductor material exposed in the deep trench 1311 are oxidized into silicon oxide, and the exposed silicon oxide surface in the deep trench 1311 and the deep trench 1312 are exposed. The copper material produced is oxidized into copper oxide; finally, ferric chloride solution is used to remove the copper chloride and retain silicon oxide 1371. The structure after this step is shown in Figure 14G.

Step 1308: Form conductive lines 13 and 15 on the upper surface of the substrate 10 and the lower surface of the substrate 10 respectively. The conductive lines 13 are connected to the metal 24, and the conductive lines 15 are connected to the N-type semiconductor material 22 and the metal 25. . In this step, a conductive line 13 is first formed on the upper surface of the substrate 10 . The conductive line 13 may be formed by etching copper. The conductive line 13 covers the notch of the deep groove 1311 and is in contact with the metal 24 . The surface of the metal 25 Conductive lines are also provided on it, which are used to connect the metal 25 and the functional circuit 11; then, the lower surface of the substrate 10 is thinned to expose the bottom N-type semiconductor material 22; then, on the substrate 10 Metal copper is deposited on the lower surface to form a conductive line 15; finally, high temperature annealing is performed to form an ohmic contact between the metal 24 and the P-type semiconductor material 23 to lead out the anode of the diode P1, between the conductive line 15 and the N-type semiconductor material 22 An ohmic contact is formed to lead out the cathode of the diode P1 and activate the doping impurities in the N-type semiconductor material 22 and the P-type semiconductor material 23 . As shown in Figure 14H.

Through steps 1301 to 1308, the through hole 12 and the through hole 14 can be formed on the substrate 10, and the diode P1 is prepared in the through hole 13.

Step 1309 , the functional circuit 11 is disposed on the upper surface of the substrate 10 . The functional circuit 11 covers the through hole 14 and is connected to the metal 25 in the through hole 14 . In addition, the functional circuit 11 is also connected to the conductive line 13 . Thereby, the functional circuit 11 is in communication with the anode of the diode P1, and the functional circuit 11 is in communication with the conductive line 15 through the metal 25 in the through hole 14 to be connected to the common ground.

After steps 1301 to 1309, the chip 100 shown in Figure 6 can be prepared.

After preparing the chip 100 as shown in Figure 6, when it is necessary to prepare the chip 100 as shown in Figure 8, in the above step 1305, N-type semiconductor materials can be sequentially formed on the side walls and bottom of the deep trench 1311. 32. P-type semiconductor material 33 and N-type semiconductor material 34. Specifically, a LPCVD or PECVD process may be first used to deposit polysilicon on the exposed surface of the substrate 10 and the surface of the deep trench 1311 . During the polysilicon deposition process, phosphorus-containing gas can be first introduced to form N-type polysilicon, that is, N-type semiconductor material 32, on the sidewalls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the boron-containing gas can be introduced to form P-type polysilicon, also known as P-type semiconductor material 33, is formed on N-type polysilicon. Finally, phosphorus-containing gas is introduced to form N-type polysilicon, also known as N-type semiconductor material 34, on P-type polysilicon. Then, a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 . Thus, N-type semiconductor material 32 , P-type semiconductor material 33 and N-type semiconductor material 34 are formed on the sidewalls and bottom of the deep trench 1311 . Other process steps are the same as those shown in Figure 6 and will not be described again.

After preparing the chip 100 as shown in Figure 6, when it is necessary to prepare the chip 100 as shown in Figure 10, in the above step 1305, P-type semiconductor materials can be sequentially formed on the side walls and bottom of the deep trench 1311. 42. N-type semiconductor material 43 and P-type semiconductor material 44. Specifically, a LPCVD or PECVD process may be first used to deposit polysilicon on the exposed surface of the substrate 10 and the surface of the deep trench 1311 . During the polysilicon deposition process, boron-containing gas can be first introduced to form P-type polysilicon, that is, P-type semiconductor material 42, on the sidewalls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the phosphorus-containing gas can be introduced to form N-type polysilicon, also known as N-type semiconductor material 43, is formed on P-type polysilicon. Finally, boron-containing gas is introduced to form P-type polysilicon, also known as P-type semiconductor material 44, on N-type polysilicon. Then, a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 . Thus, P-type semiconductor material 42 , N-type semiconductor material 43 and P-type semiconductor material 44 are formed on the sidewalls and bottom of the deep trench 1311 . Other process steps are the same as those shown in Figure 6 and will not be described again.

After preparing the chip 100 as shown in Figure 6, when it is necessary to prepare the chip 100 as shown in Figure 12, in the above step 1305, N-type semiconductor materials can be sequentially formed on the side walls and bottom of the deep trench 1311. 52. P-type semiconductor material 53, N-type semiconductor material 54 and P-type semiconductor material 55. Specifically, a LPCVD or PECVD process may be first used to deposit polysilicon on the exposed surface of the substrate 10 and the surface of the deep trench 1311 . During the polysilicon deposition process, phosphorus-containing gas can be first introduced to form N-type polysilicon, that is, N-type semiconductor material 52, on the sidewalls and bottom of the deep trench 1311 and the upper surface of the substrate 10, and then the boron-containing gas can be introduced to form P-type polysilicon, also known as P-type semiconductor material 53, is formed on N-type polysilicon, and then phosphorus-containing gas is introduced to form N-type polysilicon, that is, N-type semiconductor material 54, on P-type polysilicon. Finally, phosphorus-containing gas is introduced. Boron-containing gas is used to form P-type polysilicon, that is, P-type semiconductor material 55, on N-type polysilicon. Then, a CMP process is used to remove excess polysilicon on the upper surface of the substrate 10 , leaving only the polysilicon in the sidewalls and bottom of the deep trench 1311 . Thus, N-type semiconductor material 52 , P-type semiconductor material 53 , N-type semiconductor material 54 and P-type semiconductor material 55 are formed on the sidewalls and bottom of the deep trench 1311 . Other process steps are the same as those shown in Figure 6 and will not be described again.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present application. scope.

Claims (10)

1. A chip, comprising:

the substrate is provided with a first through hole penetrating through the upper surface and the lower surface of the substrate, at least two layers of doping materials are sequentially attached to the inner wall and the bottom of the first through hole, the at least two layers of doping materials comprise P-type doping materials and N-type doping materials, the first through hole is filled with a first conductive material, and the first conductive material is in contact with the first doping materials in the at least two layers of doping materials;

the first conductive circuit is arranged on the upper surface of the substrate and is connected with the first conductive material and the functional circuit;

and the second conductive circuit is arranged on the lower surface of the substrate and is contacted with the second doping material in the at least two layers of doping materials.

2. The chip of claim 1, wherein a second through hole penetrating the upper and lower surfaces of the substrate is further provided in the substrate, and the second through hole is filled with a second conductive material;

the functional circuit is connected with the second conductive line through the second conductive material.

3. The chip according to claim 1 or 2, wherein the chip comprises a diode, two layers of doping materials are sequentially attached to the inner wall and the bottom of the first through hole, the first doping material is a P-type doping material, and the second doping material is an N-type doping material.

4. The chip according to claim 1 or 2, wherein the chip comprises an NPN transistor, wherein three layers of doping materials are sequentially attached to the inner wall and the bottom of the first through hole, and the three layers of doping materials comprise an N-type doping material, a P-type doping material and an N-type doping material; wherein,

the first doping material is an N-type doping material, and the second doping material is an N-type doping material.

5. The chip according to claim 1 or 2, wherein the chip comprises a PNP triode, wherein three layers of doping materials are sequentially attached to the inner wall and the bottom of the first through hole, and the three layers of doping materials comprise a P-type doping material, an N-type doping material and a P-type doping material; wherein,

the first doping material is a P-type doping material, and the second doping material is a P-type doping material.

6. The chip according to claim 1 or 2, wherein the chip comprises a silicon controlled rectifier, wherein four layers of doping materials are sequentially attached to the inner wall and the bottom of the first through hole, and the four layers of doping materials comprise an N-type doping material, a P-type doping material, an N-type doping material and a P-type doping material; wherein,

the first doping material is a P-type doping material, and the second doping material is an N-type doping material.

7. The chip of any one of claims 1-6, further comprising a substrate, the substrate being disposed over the substrate.

8. The chip according to any one of claim 1 to 7, wherein,

the N-type doped material is formed by doping phosphorus element in a silicon material;

the P-type doped material is formed by doping boron element in a silicon material.

9. A method for preparing a chip, comprising:

providing a substrate;

forming a first through hole on the substrate, wherein the first through hole penetrates through the upper surface and the lower surface of the substrate, at least two layers of doping materials are sequentially attached to the inner wall and the bottom of the first through hole, the at least two layers of doping materials comprise P-type doping materials and N-type doping materials, a first conductive material is filled in the first through hole, and the first conductive material is in contact with the first doping materials in the at least two layers of doping materials;

forming a first conductive line on the upper surface of the substrate, wherein the first conductive line is connected with the first conductive material;

forming a second conductive line on the lower surface of the substrate, wherein the second conductive line is in contact with a second doping material in the at least two layers of doping materials;

and a functional circuit is arranged on the upper surface of the substrate and is connected with the first conductive circuit.

10. The method of claim 9, wherein forming a first via on the substrate comprises:

forming a first through hole and a second through hole on the substrate;

the second through hole penetrates through the upper surface and the lower surface of the substrate, a second conductive material is filled in the second through hole, and the functional circuit is connected with the second conductive circuit through the second conductive material.