CN117410278A - Semiconductor die package and method of forming the same - Google Patents

Abstract

A semiconductor die package includes a high-k dielectric layer over a component region of a first semiconductor die. The first semiconductor dies are bonded together in a wafer on wafer (WOW) type configuration. The silicon through hole structure runs through the component area. The high-k dielectric layer has an intrinsic negative charge polarity to provide a coupling voltage for adjusting the potential within the component region. In particular, electron carriers in the high-k dielectric layer attract hole carriers in the device region, which inhibits trap-assisted channels caused by surface defects formed when etching the recesses housing the silicon via structures. Accordingly, the high-k dielectric layers described herein reduce the likelihood (and/or magnitude) of current leakage within the semiconductor device in the device region of the first semiconductor die.

Description

Semiconductor die packaging and formation method thereof

Technical field

Embodiments of the present disclosure relate to a semiconductor chip package and a forming method thereof.

Background technique

Various semiconductor device packaging technologies are used to integrate one or more semiconductor dies into a semiconductor device package. In some cases, multiple semiconductor dies may be stacked in a semiconductor device package to provide the semiconductor device package with a smaller horizontal or lateral footprint and/or to increase the density of the semiconductor device. Semiconductor device packaging technologies that can be used to integrate multiple semiconductor dies into semiconductor device packages may include integrated fanout (InFO) packaging, package on package (POP), chip stacked die ( chip on wafer (CoW) packaging, wafer on wafer (WoW) packaging, and/or chip on waferon substrate (CoWoS) packaging, as well as other examples.

Contents of the invention

An aspect of the present disclosure provides a semiconductor die package. A semiconductor die package includes: a first semiconductor die; a second semiconductor die bonded to the first semiconductor die on a first side and including: a component region including one or more semiconductor components; and interconnects A region is located between the component region and the first semiconductor die. In addition, the semiconductor die package further includes: a dielectric layer located on a second side of the second semiconductor die relative to the first side, wherein the dielectric layer has an intrinsic negative charge polarity; and a conductor A via structure extends through the dielectric layer and the component area, and extends into a portion of the interconnection area.

Another aspect of the present disclosure provides a method of forming a semiconductor die package. The method includes: forming a high-k dielectric layer on a semiconductor die, wherein the high-k dielectric layer has a negative charge polarity; forming a layer through the high-k dielectric layer and the a recess in a component region of a semiconductor die and extending into a portion of an interconnect region of the semiconductor die to expose a portion of a metallization layer in the interconnect region; and forming a via hole in the recess structure.

Yet another aspect of the present disclosure provides a semiconductor die package. The semiconductor die package includes: a first semiconductor die; a second semiconductor die bonded to the first semiconductor die with a first side and including: a component region including one or more semiconductor components; and A connection area is located between the component area and the first semiconductor die. In addition, the semiconductor die package further includes: a high-k dielectric layer on a second side of the second semiconductor die relative to the first side, wherein the high-k dielectric layer has intrinsically negative charge polarity; and a silicon via structure extending through the high-k dielectric layer and the device region and into a portion of the interconnect region, wherein the silicon through silicon structure extends through a p-type well in the device region adjacent to the n-type well, and wherein the intrinsic negative charge polarity of the high-k dielectric layer is configured to inhibit transition from the p-type well to the n-type Well leakage.

Description of the drawings

Various aspects of the disclosure will be understood by reading the following detailed description in conjunction with the accompanying drawings. It is understood that the devices and/or structures shown in the figures are not necessarily drawn to scale. Therefore, the dimensions of the various features may be arbitrarily increased and/or reduced for clarity of discussion.

FIG. 1 is a schematic diagram illustrating an example environment in which systems and/or methods described herein may be implemented.

Figure 2 is a schematic diagram of an example semiconductor die package described herein.

3A and 3B are schematic diagrams illustrating an example embodiment of a region of a semiconductor die package described herein.

4 is a schematic diagram illustrating example embodiments of charge polarity for various high-k dielectric materials described herein.

Figure 5 is a schematic diagram illustrating an example embodiment of the edge of a depletion region described herein.

6A-6E are schematic diagrams illustrating example embodiments of forming semiconductor dies described herein.

7A-7D are schematic diagrams illustrating example embodiments forming part of a semiconductor die package described herein.

8A-8D are schematic diagrams illustrating example embodiments forming part of a semiconductor die package described herein.

Figure 9 is a schematic diagram illustrating example components of the components described herein.

10 is a flow diagram illustrating an example process associated with forming a semiconductor die package.

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which the first feature is formed in direct contact with the second feature. Embodiments in which additional features may be formed between one feature and a second feature such that the first feature and the second feature may not be in direct contact. Additionally, this disclosure may reuse reference numbers and/or letters in various instances. Such repeated use is for the sake of simplicity and clarity and does not itself imply a relationship between the various embodiments and/or configurations discussed.

In addition, for ease of explanation, "beneath", "below", "lower", "above", "upper" may be used herein. (upper)" and other spatially relative terms are used to explain the relationship between one component or feature shown in the figure and another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Unless explicitly described, components with the same reference number are assumed to have the same material composition and have thicknesses within the same thickness range.

In a wafer on wafer (WoW) semiconductor die package, multiple semiconductor die are directly bonded so that the semiconductor die are vertically arranged in the WoW semiconductor die package. The use of direct bonding and vertical stacking can shorten the interconnect length between semiconductor dies (which reduces power loss and signal conduction times) and can increase the density of semiconductor die packaging in semiconductor device packages including WoW semiconductor die packaging. .

WoW semiconductor die packaging may include through silicon via (TSV) structures. TSV structures are elongated conductor structures that extend through the silicon substrate (eg, device area) of one or more semiconductor dies of a WoW semiconductor die package. The TSV structure can electrically connect the back end of line (BEOL) region of one or more semiconductor dies to the redistribution structure (and external electrical connections) of the WoW semiconductor die package.

In some cases, the TSV structure may be adjacent to semiconductor components, such as transistors or other types of semiconductor components, included in the silicon substrate of the semiconductor die of the WoW semiconductor die package. In particular, the TSV structure may extend through one or more doping wells (eg, p-type doping wells, n-type doping wells) included in the silicon substrate where the semiconductor device is located.

Forming the TSV structure through the doped well may include etching the silicon substrate to form a recess through the doped well and depositing one or more conductive materials in the recess to form the TSV structure. In some cases, the etching operations used to form the recesses can result in the formation of dangling bonds at the surface of the silicon substrate in the doped wells. These dangling bonds can serve as trapping states of charges, which can lead to the formation of trap-assist tunnels (TATs) in the silicon substrate. In particular, if one doping well is located next to another doping well with an opposite doping type, the formation of TAT can cause current leakage between the two doping wells. The current leakage may cause the semiconductor device formed in the two doping wells to leak current, have poor performance and/or fail. The above-mentioned current leakage becomes more common when the pitch or spacing between the TSV structure and the semiconductor components in the WoW semiconductor die package is shortened to achieve higher semiconductor component density of the WoW semiconductor die package.

In the embodiments described herein, a semiconductor die package (eg, a WoW semiconductor die package) includes a high-k dielectric on a component region of a first semiconductor die (eg, a silicon substrate). An electrical layer wherein the first semiconductor die is bonded to the second semiconductor die in a WoW configuration. TSV structures, such as backside TSV (BTSV) structures, may be formed across the device area. The high-k dielectric layer has intrinsic negative charge polarity, which provides a coupling voltage used to adjust the potential in the device region. Specifically, negative charges (such as electron carriers) in the high-k dielectric layer attract hole charge carriers in the device region. This suppression is caused by the recessing period of etching the TSV structure. Trap-assist tunnel (TAT) caused by surface defects. Accordingly, the high-k dielectric layers described herein reduce the likelihood (and/or magnitude) of current leakage from semiconductor devices included in the device regions of the first semiconductor die. Among other advantages, this can improve the performance of the semiconductor devices and/or allow the semiconductor devices to be arranged more closely and closer to the TSV structure, which can shorten the pitch of the semiconductor devices in the first semiconductor die and improve the Semiconductor component density.

FIG. 1 is a schematic diagram illustrating an example environment 100 in which systems and/or methods described herein are implemented. As shown in FIG. 1 , an example environment 100 may include a plurality of semiconductor processing equipment 102 - 114 and a wafer/die transfer equipment 116 . The plurality of semiconductor processing equipment 102 - 114 may include deposition equipment 102 , exposure equipment 104 , development equipment 106 , etching equipment 108 , planarization equipment 110 , plating equipment 112 , bonding equipment 114 , and/or other types of semiconductor processing. equipment. Example environment 100 may include equipment, for example, in a clean room, a semiconductor foundry, a semiconductor processing facility, and/or a semiconductor manufacturing facility.

Deposition apparatus 102 is a semiconductor processing apparatus that includes a semiconductor processing chamber and one or more components capable of depositing various materials on a substrate. In some embodiments, deposition apparatus 102 includes a spin coating apparatus capable of depositing a photoresist layer on a substrate, such as a wafer. In some embodiments, the deposition equipment 102 includes chemical vapor deposition (CVD) equipment (eg, plasma-enhanced CVD (PECVD) equipment, high-density plasma-assisted chemical vapor deposition (PECVD) equipment, etc. plasma CVD, HDP-CVD) equipment, sub-atmospheric chemical vapor deposition (sub-atmospheric CVD, SACVD) equipment, low-pressure chemical vapor deposition (low-pressure CVD, LPCVD) equipment, atomic layer deposition (ALD) equipment, Plasma-enhanced atomic layer deposition (PEALD) equipment or other types of CVD equipment. In some embodiments, the deposition equipment 102 includes physical vapordeposition (PVD) equipment, such as sputtering equipment or Other types of PVD equipment. In some embodiments, deposition equipment 102 includes epitaxial equipment configured to form layers and/or regions of components by epitaxial growth. In some embodiments, example environment 100 includes multiple types of deposition Device 102.

Exposure equipment 104 is a semiconductor processing equipment capable of exposing a photoresist layer to a radiation source. For example, the radiation source may be an ultraviolet light (UV) source (such as a deep UV (deep UV) source, an extreme ultraviolet (EUV) source and/or the like), an X-ray source , electron beam (e-beam) source and/or the like). Exposure equipment 104 can expose the photoresist layer to a radiation source to transfer the pattern of the photomask to the photoresist layer. The pattern may include one or more semiconductor component layer patterns for forming one or more semiconductor components, may include patterns for forming one or more structures of the semiconductor component, may include multiple patterns for etching the semiconductor component. parts and/or the like. In some embodiments, exposure equipment 104 includes a scanning exposure machine, a stepper exposure machine, or similar types of exposure equipment.

The developing device 106 is a semiconductor processing device capable of developing a photoresist layer that has been exposed to a radiation source to reveal a pattern transferred to the photoresist layer from the exposure device 104 on the photoresist layer. In some embodiments, exposure device 106 achieves development of the pattern by removing unexposed portions of the photoresist layer. In some embodiments, exposure device 106 achieves development of the pattern by removing exposed portions of the photoresist layer. In some embodiments, exposure device 106 achieves development of the pattern by using a chemical exposure agent to dissolve exposed or unexposed portions of the photoresist layer.

The etching apparatus 108 is a semiconductor processing apparatus capable of etching various materials of substrates, wafers, or semiconductor components. For example, the etching apparatus 108 may include a wet etching apparatus, a dry etching apparatus, or the like. In some embodiments, the etching apparatus 108 includes a chamber filled with etchant, and the substrate is placed in the chamber for a specified period of time to remove one or more portions of the substrate in a specified amount. In some embodiments, etching apparatus 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate. The plasma etching or plasma-assisted etching may include using a dissociated gas to isotropically or directionally etch one or more portions of the substrate.

The planarization equipment 110 is a semiconductor processing equipment capable of polishing or planarizing multiple layers of a wafer or semiconductor component. For example, planarization equipment 110 may include a chemical mechanical planarization (CMP) equipment and/or another planarization equipment that grinds or planarizes the plating material. The planarization device 110 can grind or planarize the surface of the semiconductor component through chemical and mechanical energy (eg, chemical etching and abrasive-free grinding). The planarization device 110 may use abrasive particles, corrosive chemical slurry, polishing pads and clamping rings (for example, with a diameter larger than the diameter of the semiconductor device). The polishing pad and the semiconductor component are pressed together by a dynamic polishing heat and held by a clamping ring. The dynamic grinding head can rotate non-axially to remove material and planarize the irregular topography of the semiconductor component so that the semiconductor component becomes flat/planar.

Plating equipment 112 is a semiconductor processing equipment capable of plating one or more metals on a substrate (eg, a wafer, a semiconductor component, and/or the like) or a portion of a substrate. For example, the plating equipment 112 may include copper plating components, aluminum plating components, nickel plating components, tin plating components, compound/alloy (eg, tin-silver, tin-lead, and/or the like) plating components, and/or or one or more other electroplated components of conductive materials, metals and/or similar materials.

The bonding equipment 114 is a semiconductor processing equipment capable of bonding two or more workpieces (eg, two or more semiconductor substrates, two or more semiconductor components, and two or more semiconductor dies). For example, bonding equipment 114 may include a hybrid bonding tool. Hybrid bonding equipment is a bonding equipment configured to join semiconductor dies directly via copper-to-copper connections (or other metal direct connections). As another example, bonding apparatus 114 may include a eutectic bonding apparatus capable of bonding two or more wafers by forming a eutectic bond. In this example, bonding apparatus 114 may heat two or more wafers to form a eutectic system between the materials of the wafers.

Wafer/die transfer equipment 116 includes movable robots, robotic arms, tram/railcars, overhead hoist transport (OHT) systems, automated materially handling systems (AMHS), or configured to transfer substrates and/or semiconductor components between semiconductor processing equipment 102-114, configured to transfer substrates and/or semiconductor components between different processing chambers of the same semiconductor processing equipment, and/or configured Another component for re-transmitting substrates and/or semiconductor components to or removing substrates and/or semiconductor components from other locations such as wafer racks, storage chambers, and/or the like) . In some embodiments, the wafer/die transfer device 116 may be a programmed component that is configured to move along a specific path and/or may operate autonomously or semi-autonomously. In some embodiments, the example environment 100 includes multiple wafer/die transfer devices 116 .

For example, the wafer/die transfer apparatus 116 may be included in a cluster tool or another type of apparatus that includes a plurality of processing chambers, and may be configured, for example, to transfer between the plurality of processing chambers. Transferring substrates and/or semiconductor components between processing chambers and buffer areas, transferring substrates and/or semiconductor components between processing chambers and, for example, equipment front end modules (EFEM) ), and/or transfer substrates and/or semiconductor components between processing chambers and transfer carriers (such as front opening unified pods (FOUP)). substrate and/or semiconductor components. In some embodiments, wafer/die transfer equipment 116 may be included in multi-chamber deposition equipment 102, which may include a pre-clean processing chamber (eg, for cleaning or removing oxide from substrates and/or semiconductor components). materials, oxidation and/or other types of contaminants or by-products) and a variety of deposition processing chambers (eg, processing chambers for depositing different types of materials, processing chambers for performing various deposition operations). In such embodiments, the wafer/die transfer apparatus 116 is configured to transfer substrates/semiconductor components between the processing chambers of the deposition apparatus 102 without breaking the vacuum (or at least maintaining a partial vacuum).

In some embodiments, one or more semiconductor processing equipment 102 - 114 and/or wafer/die transfer equipment 116 may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing equipment 102 - 114 and/or the wafer/die transfer equipment 116 may be used to: join the first semiconductor die and the second semiconductor die at a bonding interface, where the bonding interface is located on a first side of the second semiconductor die; and a high-k dielectric layer is formed on a second side of the second semiconductor die relative to the first side, wherein the high-k dielectric layer has a negative charge polarity ( negativecharge polarity); forming an interconnect region from the second side of the second semiconductor die through the high-k dielectric layer and the device region of the second semiconductor die and extending into the second semiconductor die to expose the internal A recess in a portion of the metallization layer in the connection area; and/or a BTSV structure is formed in the recess.

The component labels and configuration methods shown in Figure 1 are provided as one or more instances. In practice, there may be additional components, fewer components, different components, or components configured in a different configuration than shown in FIG. 1 . Furthermore, two or more components shown in FIG. 1 may be implemented as a single component. Alternatively, the single component shown in Figure 1 may be implemented as multiple separate components. Additionally or alternatively, a set of components (eg, one or more components) of the example environment 100 may perform operations described as being performed by another set of components of the example environment 100 .

FIG. 2 is a schematic diagram of an example semiconductor die package 200 described herein. The semiconductor die package 200 includes an example wafer on wafer (WoW) semiconductor die package or another semiconductor die package in which the semiconductor dies are directly bonded and vertically configured or stacked.

As shown in FIG. 2 , the semiconductor die package 200 includes a first semiconductor die 202 and a second semiconductor die 204 . In some embodiments, semiconductor die package 200 includes additional semiconductor dies. The first semiconductor die 202 may include a system on chip (SoC) die, such as a logic die, a central processing unit (CPU) die, or a graphics processing unit (GPU) die. die and/or other types of SoC die. Additionally or alternatively, the first semiconductor die 202 may include a memory die, an input/output (I/O) die, a pixel sensor die, and/or other types of semiconductor die. . Memory chips may include static random access memory (SRAM) chips, dynamic random access memory (DRAM) chips, NAND flash memory chips, high bandwidth memory (high bandwidth) memory, HBM) die and/or other types of memory die. The second semiconductor die 204 may be the same or different in type than the first semiconductor die 202 .

The first semiconductor die 202 and the second semiconductor die 204 may be bonded to each other (eg, directly bonded) at the bonding interface 206 . In some embodiments, the bonding interface 206 between the first semiconductor die 202 and the second semiconductor die 204 may include one or more material layers, such as one or more passivation layers, a Or multiple layers of bonding films and/or one or more layers and other types of material layers. In some embodiments, the thickness of the second semiconductor die 204 is in the range of about 0.5 microns (μm) to about 5 μm. However, second semiconductor die 204 having thicknesses in other ranges also fall within the scope of this disclosure.

The first semiconductor die 202 may include a device region 208 and an interconnect region 210 adjacent and/or above the device region 208 . In some embodiments, first semiconductor die 202 may include additional regions. Similarly, the second semiconductor die 204 may include a device region 212 and an interconnect region 214 adjacent and/or above the device region 212 . In some embodiments, the second semiconductor die 204 may include additional regions. The first semiconductor die 202 and the second semiconductor die 204 may be bonded to each other at interconnect regions 210, 214. The bonding interface 206 may be located on a first side of the interconnect region 214 facing the interconnect region 210 and corresponding to the first side of the second semiconductor die 204 .

Component regions 208, 212 may each include a silicon substrate, a substrate formed of a material including silicon, or a III-V compound semiconductor material substrate (eg, a gallium arsenide substrate, a silicon-on-insulator, such as a silicon-on-insulator substrate). on an insulator (SOI) substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, or other types of semiconductor substrates. Component region 212 may include one or more semiconductor components 216 in the substrate of component region 212 . Device region 208 may include one or more semiconductor devices 218 in the substrate of device region 208. Semiconductor devices 216, 218 may each include one or more transistors (eg, planar transistors, fin field effect transistors (fin field effect transistors)). field effect transistor (FinFET), nanosheet transistors (such as gate all around (GAA) transistors), memory cells, capacitors, inductors, resistors, pixel sensors and/or other types of semiconductor components.

The interconnect areas 210 and 214 may be called back end of line (BEOL) areas. Interconnect region 212 may include one or more dielectric layers 220 , which may include silicon nitride, oxide (such as silicon oxide and/or other oxide materials), low-k dielectric materials and/or other types of dielectric materials. In some embodiments, one or more etch stop layers (ESL) may be included between one or more dielectric layers 220 . For example, ESL may include aluminum oxide, aluminum nitride, silicon nitride, silicon oxynitride, aluminum oxynitride, and/or silicon oxide, etc.

The interconnect region 210 may further include a metallization layer 222 in one or more dielectric layers 220 . Semiconductor devices 218 in device region 208 may be electrically and/or physically connected to one or more metallization layers 222 . Metallization layer 222 may include wires, trenches, vias, pillars, interconnect structures, and/or other types of metallization layers. Contact structure 224 may be included in one or more dielectric layers 220 of interconnect region 210 . Contact structures 224 may be electrically and/or physically connected to one or more metallization layers 222 . Contact structures 224 may include conductive terminals, conductor pads, conductive posts, and/or other types of contact structures. The metallization layer 222 and the contact structure 224 may each include one or more conductive materials, such as copper, gold, silver, nickel, tin, ruthenium, cobalt, tungsten, titanium, one or more metals, one or more Conductive ceramics and/or other types of conductive materials.

Interconnect region 214 may include one or more dielectric layers 226 , which may include silicon nitride, oxide (such as silicon oxide and/or other oxide materials), low-k dielectric materials and/or other types of dielectric materials. In some embodiments, one or more etch stop layers (ESL) may be included between one or more dielectric layers 226 . For example, ESL may include aluminum oxide, aluminum nitride, silicon nitride, silicon oxynitride, aluminum oxynitride, and/or silicon oxide, etc.

Interconnect region 214 may further include a metallization layer 228 within one or more dielectric layers 226 . Semiconductor devices 216 in device region 212 may be electrically and/or physically connected to one or more metallization layers 228 . Metallization layer 228 may include wires, trenches, vias, pillars, interconnect structures, and/or other types of metallization layers. Contact structure 230 may be included in one or more dielectric layers 226 of interconnect region 214 . Contact structure 230 may be electrically and/or physically connected to one or more metallization layers 228 . Furthermore, the contact structure 230 may be electrically connected and/or physically connected to the contact structure 224 of the first semiconductor die 202 . Contact structure 230 may include conductive terminals, conductor pads, conductive posts, and/or other types of contact structures. Metallization layer 228 and contact structure 230 may each include one or more conductive materials, such as copper, gold, silver, nickel, tin, ruthenium, cobalt, tungsten, titanium, one or more metals, one or more Conductive ceramics and/or other types of conductive materials.

As further shown in FIG. 2 , the semiconductor die package 200 may include a redistribution structure 232 . The redistribution structure 232 may include a redistribution layer (RDL) and/or other types of redistribution structures. The redistribution structure 232 may be configured to route signals and I/O (in a fan-out fashion) for the semiconductor dies 202, 204.

The redistribution structure 232 may include one or more dielectric layers 234 and multiple metallization layers 236 disposed within the one or more dielectric layers 234 . Dielectric layer 234 may include silicon nitride, oxide (such as silicon oxide and/or other types of oxide materials), low-k dielectric materials, and/or other suitable dielectric materials.

The metallization layer 236 of the redistribution structure 232 may include one or more materials, such as gold, copper, silver, nickel, tin, and/or palladium. The metallization layer 236 of the redistribution structure 232 may include metal lines, vias, interconnect structures, and/or other types of metallization layers.

As further shown in FIG. 2 , the semiconductor die package 200 may include one or more BTSV structures 238 passing through the device area 212 and extending into a portion of the interconnect area 214 . One or more BTSV structures 238 may include vertically elongated conductor structures (e.g., conductor posts, vias) that electrically connect one or more metallization layers 228 in the interconnect region 214 of the second semiconductor die 204 . to one or more metallization layers 236 in the redistribution structure 232. The BTSV structure 238 may be referred to as a through silicon via (TSV) structure because the BTSV structure 238 completely extends through the silicon substrate (eg, the silicon substrate of the device region 212 ) rather than completely extending through the dielectric layer. or insulation. One or more BTSV structures 238 may include one or more conductive materials, such as copper, gold, silver, nickel, tin, ruthenium, cobalt, tungsten, titanium, one or more metals, one or more conductive ceramics, and/or or other types of conductive materials.

A buffer oxide layer 240 may be included between the second semiconductor die 204 and the redistribution structure 232 . In particular, buffer oxide layer 240 may contact or be located over the second side of second semiconductor die 204 . One or more BTSV structures 238 may extend through the buffer oxide layer 240 . Buffer oxide layer 240 may include one or more oxide layers that serve as buffers between device regions 212 of second semiconductor die 204 and redistribution structures 232 . The buffer oxide layer 240 may include one or more oxide materials, such as silicon oxide, silicon oxycarbide, silicon oxynitride, and/or other types of oxide materials.

A high-k dielectric layer 242 may be included between the second semiconductor die 204 and the redistribution structure 232 . In particular, the high-k dielectric layer 242 may be located over the second side of the second semiconductor die 204 and contact the buffer oxide layer 240 . One or more BTSV structures 238 may extend through the high-k dielectric layer 242 .

The high-k dielectric layer 242 is a material layer with negative charge polarity. In other words, the high-k dielectric layer 242 includes one or more materials having excess electron charge carriers. The high-k dielectric layer 242 may have an intrinsic negative charge polarity because the material selected for the high-k dielectric layer 242 may have excess electron carriers. The negative charge polarity of the high-k dielectric layer 242 causes the hole carriers in the silicon substrate of the device region 212 to be attracted in a direction toward the electron carriers in the high-k dielectric layer 242 .

As discussed above, dangling bonds formed during etching of the recesses housing BTSV structures 238 may serve as charge trap states, which may result in the formation of trap-assist tunnels in the silicon substrate of device region 212 . The trap auxiliary channel may cause leakage current from the p-well 302 to the n-well 304 via the BTSV structure 238 . Leakage current may pass through adjacent doping wells associated with semiconductor component 216 . The negative charge polarity of high-k dielectric layer 242 provides a coupling voltage to adjust the potential in the silicon substrate of device region 212 . In particular, electron carriers in high-k dielectric layer 242 attract hole carriers in the silicon substrate of device region 212 , which suppresses surface defects formed during etching of recesses housing BTSV structures 238 Resulting trap auxiliary channel. Therefore, the high-k dielectric layer 242 may reduce the likelihood (and/or the magnitude of the leakage current) of leakage current in the semiconductor device 216 .

In some embodiments, the high-k dielectric layer 242 has a thickness of about 20 Angstroms. Until about/> Within the range, a sufficient amount of electron carriers can be provided to attract hole carriers in the silicon substrate in the component region 212 and suppress trap auxiliary channels. However, high-k dielectric layers 242 having other thickness ranges are also included within the scope of this disclosure.

The high-k dielectric layer 242 may include one or more high-k dielectric materials, such as hafnium oxide, aluminum oxide, tantalum oxide, gallium oxide, titanium oxide, niobium oxide, and/or other suitable high-k dielectric materials. Constant dielectric materials, etc. Additionally or alternatively, high-k dielectric layer 242 may include one or more low-k dielectric materials. The material and/or thickness of the high-k dielectric layer 242 may be selected such that a sufficient number of electron carriers are included in the high-k dielectric layer 242 .

In some embodiments, the electron carriers in the high-k dielectric layer have an equivalent surface charge density of about -8·10 ^-9 coulombs per square centimeter (i.e., -8·10 ^-9 C/cm ² ) to about -1.6·10 ^-7 C/cm ² to provide a sufficient amount of electron carriers to attract hole carriers in the silicon substrate in the component region 212 and to suppress trap assistance aisle. However, high-k dielectric layers with equivalent surface charge densities in other ranges are also included within the scope of this disclosure.

UBM layer 244 may include a top surface of one or more dielectric layers 234 . UBM layer 244 may be electrically connected and/or physically connected to one or more metallization layers 236 of redistribution structure 232 . UBM layer 244 may be included in recesses on the top surface of one or more dielectric layers 234 . UBM layer 244 may include one or more conductive materials, such as copper, gold, silver, nickel, tin, ruthenium, cobalt, tungsten, titanium, one or more metals, one or more conductive ceramics, and/or Other types of conductor materials.

As further shown in FIG. 2 , semiconductor die package 200 may include conductive terminals 246 . The conductive terminals 246 may be electrically connected and/or physically connected to the UBM layer 244 . Under-bump metallization layer 244 may be configured to facilitate attachment of conductive terminals 246 to one or more metallization layers 236 in redistribution structure 232 and/or provide greater structural stiffness to conductive terminals 246 (by increasing conductive surface area to which terminal 246 is connected). The conductive terminals 246 may include ball grid array (ball grid array) bumps, land grid array (LGA) pads, pin grid array (PGA) pins, and/or other types of conductive terminals. The conductive terminals 246 enable the semiconductor die package 200 to be mounted to a circuit board, a socket (eg, an LGA socket), an interposer, or a semiconductor component package (eg, a chip onwafer on substrate (CoWoS) package, Integrated fanout (InFO) package) rewiring structure and/or other types of mounting structures.

As further shown in FIG. 2 , the semiconductor die package 200 may include one or more regions 248 in which the BTSV structures 238 are adjacent (eg, adjacent to, immediately adjacent to, and/or through) the device region 212 of the second semiconductor die 204 semiconductor component 216 in . Subsequent drawings (eg, FIGS. 3A and 3B ) may refer to region 248 of semiconductor die package 200 .

As mentioned above, Figure 2 is provided as an example only. Other examples may differ from that described with reference to FIG. 2 .

3A and 3B are schematic diagrams illustrating example embodiments of region 248 of semiconductor die package 200 described herein. Region 248 includes BTSV structure 238 extending adjacent one or more semiconductor devices 216 in the silicon substrate of device region 212 and through buffer oxide layer 240 and high-k dielectric layer 242 .

As shown in FIG. 3A , a plurality of doped regions are included in the silicon substrate of device region 212 . For example, p-type well 302 may be included in the silicon substrate of device region 212 . The p-type well 302 may include a portion of the silicon substrate that is doped with one or more p-type dopants, such as boron or germanium. As another example, n-type well 304 may be located in the silicon substrate of component region 212 . The n-type well 304 may be adjacent to the p-type well 302 (eg, adjacent to the p-type well 302 or alongside the p-type well 302) such that the boundaries of the p-type well 302 and the n-type well 304 meet at the interface. The n-type well 304 may include one or more n-type dopants, such as phosphorus or arsenic. In some embodiments, additional doped regions are included, such as a deep n-type well 306 below the n-type well 304 .

As further shown in FIG. 3A , one or more semiconductor components 216 may include source/drain regions 308 and source/drain regions 310 . In some embodiments, source/drain regions 308 and source/drain regions 310 are included on opposite sides of BTSV structure 238 . In various instances, the source/drain regions are referred to as source regions, drain regions, or a combination of source and drain regions. Source/drain regions 308 , 310 may be source/drain regions of one or more transistors of one or more semiconductor devices 216 .

Source/drain regions 308, 310 include silicon doped with one or more dopants. The dopant is, for example, a p-type material (such as boron, germanium, etc.), an n-type material (such as phosphorus or arsenic, etc.) and/or other types of dopants. For example, source/drain region 308 may be included in n-type well 304 and may be referred to as an n-type source/drain region because source/drain region 308 is doped with one or more n-type dopants. doped. As another example, source/drain region 310 may be included in p-type well 302 and may be referred to as a p-type source/drain region because source/drain region 310 is doped with one or more p-type dopants. Mixed with quality.

A shallow trench isolation (STI) region 312 may be included between the source/drain regions 308 and 310 to provide electrical isolation between the source/drain regions 308 and 310. The STI region 312 may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric materials, and/or other suitable of insulating materials. The STI region 312 may include a multi-layer structure, such as one or more liner layers.

As further shown in FIG. 3A , sidewall spacers 314 may be included around the BTSV structure 238 and between the BTSV structure 238 and the p-well 302 . Furthermore, sidewall spacers 314 may be included between the BTSV structure 238 and the silicon substrate of the device region 212 . Additionally, sidewall spacers 314 may be included between the BTSV structure 238 and the buffer oxide layer 240 . Additionally, sidewall spacers 314 may be included between the BTSV structure 238 and the high-k dielectric layer 242 . The sidewall spacers 314 may include one or more dielectric materials, such as silicon oxide (eg, silicon dioxide), silicon nitride, and/or silicon oxynitride.

BTSV structure 238 may extend through p-well 302 but not through n-well 304 . Furthermore, BTSV structure 238 does not extend through any other n-type wells, which would result in direct current leakage between BTSV structure 238 and other n-type wells. The sidewalls of the BTSV structure 238 are spaced apart from the edge of the p-type well 302 adjacent the n-type well 304 by a distance D1, and the area between the sidewalls of the BTSV structure 238 and the edge of the p-type well 302 may be referred to as a keep -out-zone, KOZ). The KOZ can be considered a design guideline that prohibits placing the BTSV structure 238 near the edge of the p-type well 302 immediately adjacent to the n-type well. As discussed above, the dangling bonds formed during etching of the recesses housing the BTSV structures 238 may act as charge trap states, which may result in the formation of trap-assisted channels in the silicon substrate of the component region 212 . The trap auxiliary channel may cause current leakage from p-well 302 to n-well 304 via BTSV structure 238 . Accordingly, distance D1 may be selected to reduce or prevent leakage current due to BTSV structure 238 .

The negative charge polarity of high-k dielectric layer 242 provides a coupling voltage to adjust the potential in the silicon substrate of device region 212 . In particular, electron carriers in high-k dielectric layer 242 attract hole carriers in the silicon substrate of device region 212 , which suppresses surface defects formed during etching of recesses housing BTSV structures 238 Resulting trap auxiliary channel. This allows the distance D1 to be shortened and the BTSV structure 238 to be placed closer to the p-type well without increasing the likelihood of leakage current in one or more semiconductor devices and/or increasing the magnitude of the leakage current. 302 (for example, the edge of the p-type well 302 immediately adjacent to or bordering the n-type well 304). In some embodiments, distance D1 is in the range of about 0.2 μm to about 2 μm based on the negative charge polarity of high-k dielectric layer 242 . If the high-k dielectric layer 242 is not provided, the distance D1 is in the range of about 0.5 μm to about 50 μm. However, situations where the distance D1 is in other ranges also fall within the scope of this disclosure.

FIG. 3B shows a schematic cross-sectional view along line A-A in FIG. 3A (a schematic top view viewed from top to bottom along this cross-section). As shown in FIG. 3B , sidewall spacers 314 may surround BTSV structure 238 such that BTSV structure 238 does not directly contact p-well 302 (and, therefore, does not directly contact the silicon substrate of device region 212 ). If the BTSV structure 238 directly contacts the p-type well 302, problems such as current leakage and/or copper migration into the silicon substrate, and/or delamination of the BTSV structure 238 from the silicon substrate may occur.

As mentioned above, FIG. 3A and FIG. 3B are provided as an example. Other examples may differ from those described with reference to Figures 3A and 3B.

4 is a schematic diagram illustrating an example embodiment 400 of charge polarity for various high-k dielectric materials described herein. The high-k dielectric layer 242 described herein may include one or more high-k dielectric materials.

As shown in example embodiment 400, the charge polarity is a function of the interface state density (D _it ) 402 (in eV ⁻¹ /cm ² ) and the fixed charge density (Q _f /q) 404 (in cm ⁻² ). function. As shown in Figure 4, high-k dielectric materials such as hafnium oxide, aluminum oxide, tantalum oxide, aluminum nitride, and gallium oxide have a negative fixed charge density 404 (in the form of hafnium oxide) corresponding to all interface state densities. For example, mainly negative fixed charge density 404). Other high-k dielectric materials such as titanium oxide and niobium oxide also have negative fixed charge densities 404 corresponding to the respective interface state densities of these high-k dielectric materials.

As mentioned above, Figure 4 is provided as an example. Other examples may differ from that described with reference to FIG. 4 .

FIG. 5 is a schematic diagram illustrating an example embodiment 500 of a depletion region edge 502 described herein. Depletion region edge 502 may occur within p-type well 302 in the silicon substrate of component region 212 of second semiconductor die 204 as described herein.

Depletion region edge 502 represents the edge of the depletion region in p-well 302 . In this depletion region (eg, the region in p-well 302 between the edge of n-well 304 and depletion region edge 502), a built-in electric field exists in the majority of carriers that will be displaced. If the edge of the depletion region contacts the BTSV structure 238, the built-in electric field can easily create a current leakage path through the dangling bonds at the sidewalls of the BTSV structure 238.

Since the high-k dielectric layer 242 has negative charge polarity, the negative charge carriers/electron carriers in the high-k dielectric layer 242 can attract the hole carriers in the p-type well 302, which can Suppress the depletion region and reduce the width D2 of the depletion region. This causes the depletion region 502 to recede from the BTSV structure 238 instead of expanding toward the BTSV structure 238 (which would result in current leakage). In some embodiments, the intrinsic negative charge polarity of the high-k dielectric layer 242 results in the width D2 of the depletion region being less than or approximately equal to 1.22 μm. However, depletion regions with width D2 in other ranges also fall within the scope of the present disclosure.

As mentioned above, Figure 5 is provided as an example. Other examples may differ from that described with reference to FIG. 5 .

6A-6E are schematic diagrams illustrating an example embodiment 600 of forming a semiconductor die described herein. In some embodiments, example embodiment 600 includes an example process (or a portion of an example process) for forming second semiconductor die 204 . The operations that will be described with reference to FIGS. 6A-6E correspond to the second semiconductor die 204 . Similar operations may be performed to form first semiconductor die 202 .

In some embodiments, the operations described with reference to FIGS. 6A-6E may be performed by semiconductor processing equipment 102 - 114 and/or wafer/die transfer equipment 116 . In some embodiments, the operations described with reference to FIGS. 6A-6E may be performed by other semiconductor processing equipment. Referring to FIG. 6A , one or more operations of the example embodiment 600 may be performed corresponding to the silicon substrate in the device region 212 of the second semiconductor die 204 .

As shown in FIG. 6B , one or more semiconductor devices 216 may be formed in device region 212 . For example, one or more of semiconductor processing equipment 102-114 may be used to perform photolithography patterning operations, etching operations, deposition operations, CMP operations, and/or other operations to form one or more transistors, a or multiple capacitors, one or more memory cells, and/or one or more other types of semiconductor components. In some embodiments, one or more regions of the silicon substrate in the device region may be doped during an ion implantation operation to form one or more p-type wells 302 and one or more n-type wells 304 and/or one or more deep n-wells 306. In some embodiments, deposition apparatus 102 may be used to deposit one or more source/drain regions 308, one or more source/drain regions 310, and/or one or more STI regions 312, etc.

As shown in FIGS. 6C to 6E , the interconnect area 214 of the second semiconductor die 204 may be formed on the surface of the silicon substrate in the device area 212 and/or on the silicon substrate. One or more of the semiconductor processing devices 102 - 114 may form interconnect region 214 by forming one or more dielectric layers 226 and forming multiple metallization layers 228 in dielectric layer 226 . For example, deposition apparatus 102 may deposit a first layer of one or more dielectric layers 226 (eg, by using CVD techniques, ALD techniques, PVD techniques, and/or other types of deposition techniques); etching apparatus 108 may move removing portions of the first layer to form recesses in the first layer; and deposition apparatus 102 and/or plating apparatus 112 may form the first metallization layer of multi-layer metallization layer 228 in the recesses (e.g., by using CVD technology, ALD technology, PVD technology, electroplating technology and/or other types of deposition technology). At least a portion of the first metallization layer may be electrically connected and/or physically connected to the semiconductor device 216 . Deposition equipment 102 , etching equipment 108 , plating equipment 112 and/or other semiconductor processing equipment may continue to perform similar processing operations to form interconnect regions 214 until a sufficient or desired configuration of metallization layer 228 is achieved.

As shown in FIG. 6E , one or more of the semiconductor processing equipment 102 - 114 may be used to form another layer of one or more dielectric layers 226 and may be used to form a plurality of contact structures in such dielectric layer 226 230 , such that the contact structure 230 is electrically and/or physically connected to one or more of the metallization layers 228 . For example, deposition apparatus 102 may be used to deposit one or more layers of dielectric layer 226 (eg, by using CVD techniques, ALD techniques, PVD techniques, and/or other types of deposition techniques); etching apparatus 108 Portions of the dielectric layer 226 may be removed to form recesses in the dielectric layer 226; and deposition equipment 102 and/or plating equipment 112 may be used to form contact structures 230 in the recesses (eg, by using CVD techniques , ALD technology, PVD technology, electroplating technology and/or other types of deposition technology).

As mentioned above, FIGS. 6A to 6E are provided as an example. Other examples may differ from those described with reference to Figures 6A-6E.

7A-7D are schematic diagrams illustrating an example embodiment 700 forming part of a semiconductor die package 200 described herein. In some embodiments, one or more of the operations described with reference to FIGS. 7A-7D may be performed by semiconductor processing equipment 102 - 114 and/or wafer/die transfer equipment 116 . In some embodiments, one or more of the operations described with reference to FIGS. 7A-7D may be performed by other semiconductor processing equipment.

As shown in FIG. 7A , the first semiconductor die 202 and the second semiconductor die 204 are bonded to each other at the bonding interface 206 such that the first semiconductor die 202 and the second semiconductor die 204 are vertically aligned or vertically stacked in a WoW configuration. . The bonding apparatus 114 may be used to perform a bonding operation to bond the first semiconductor die 202 and the second semiconductor die 204 to each other at the bonding interface 206 . The bonding operation may include a direct bonding operation (or a hybrid bonding operation) in which bonding of the first semiconductor die 202 and the second semiconductor die 204 is accomplished through physical connection of the contact structure 224 and the contact structure 230 .

As shown in FIG. 7B , a buffer oxide layer 240 may be formed on the second semiconductor die 204 . The second semiconductor die 204 may be bonded to the first semiconductor die 202 on a first side, and the first side of the second semiconductor die 204 may correspond to the first side of the interconnect region 214 . The buffer oxide layer 204 may be formed on a second side of the second semiconductor die 204 relative to the first side, and the second side of the second semiconductor die 204 may correspond to the device region 212 of the second semiconductor die 204 . First side. Deposition apparatus 102 may deposit buffer oxide layer 240 using an epitaxial technique, a CVD technique, a PVD technique, an ALD technique, another deposition technique described with reference to FIG. 1 , and/or a deposition technique different from that described with reference to FIG. 1 .

As further shown in FIG. 7B , a high-k dielectric layer 242 may be formed on the second semiconductor die 204 . The high-k dielectric layer 242 may be formed on a second side of the second semiconductor die 204 relative to the first side, and the second side of the second semiconductor die 204 corresponds to a component of the second semiconductor die 204 The first side of area 212. A high-k dielectric layer 242 may be formed on the buffer oxide layer 240 . Deposition apparatus 102 may deposit a high-k dielectric by using an epitaxial technique, a CVD technique, a PVD technique, an ALD technique, another deposition technique described with reference to FIG. 1 , and/or a deposition technique other than that described with reference to FIG. 1 Layer 242. The high-k dielectric layer 242 may be deposited in a temperature range of about 150 degrees Celsius to about 300 degrees Celsius. However, forming the high-k dielectric layer 242 in other temperature ranges also falls within the scope of the present disclosure.

As discussed above, the high-k dielectric layer 242 may have an intrinsically negative charge polarity. Accordingly, forming the high-k dielectric layer 242 may include depositing one or more materials having intrinsically negative charge polarity to form the high-k dielectric layer 242 . When one or more of the above materials are deposited, lattice defects are formed in them, resulting in intrinsically negative charge polarity.

As shown in FIG. 7C , one or more dielectric layers 226 may be formed through the high-k dielectric layer 242 , the buffer oxide layer 240 , the silicon substrate of the device region 212 and extending into the interconnect region 214 Depression 702. One or more recesses 702 may expose one or more portions of metallization layer 228 in interconnect region 214 . Accordingly, one or more recesses 702 may be formed on one or more portions of metallization layer 228 .

In some embodiments, a pattern in the photoresist layer is used to form one or more recesses 702 . In such embodiments, deposition apparatus 102 is used to form a photoresist layer on high-k dielectric layer 242 . The exposure device 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developing device 106 is used to develop and remove some portions of the photoresist layer to reveal the pattern. The etching apparatus 108 is used to etch through the high-k dielectric layer 242 , the buffer oxide layer 240 , and the device region 212 and into the interconnect region 214 to form one or more recesses 702 . In some embodiments, the etching operation includes plasma etching technology, wet chemical etching technology, and/or other types of etching technology. In some embodiments, a photoresist removal device is used to remove remaining portions of the photoresist layer (eg, through chemical strippers, plasma ashing, and/or other techniques). In some embodiments, as an alternative technique, a hard mask layer is used to form one or more recesses 702 based on a pattern.

As shown in Figure 7D, one or more BTSV structures 238 may be formed in one or more recesses 702. As a result, one or more BTSV structures 238 extend through the high-k dielectric layer 242 , the buffer oxide layer 240 and the device region 212 , and into the interconnect region 214 . Furthermore, one or more BTSV structures 238 may be formed adjacent to one or more semiconductor devices 216 in device region 212 and may pass through one or more p-type wells 302 in the silicon substrate of device region 212 (For example, p-well 302 associated with one or more semiconductor devices 216). One or more BTSV structures 238 may be electrically connected and/or physically connected to one or more portions of metallization layer 228 exposed by one or more recesses 702 .

Deposition equipment 102 and/or plating equipment 112 may deposit one or more by CVD technology, PVD technology, ALD technology, electroplating technology, other deposition technologies described with reference to FIG. 1 and/or deposition technologies different from those described with reference to FIG. 1 . Multiple BTSV structures 238. In some embodiments, planarization apparatus 110 may be used to perform a CMP operation to planarize one or more BTSV structures 238 after depositing one or more BTSV structures 238 .

As described above, FIGS. 7A to 7D are provided as an example. Other examples may differ from those described with reference to Figures 7A-7D.

8A-8D are schematic diagrams illustrating an example embodiment 800 forming part of a semiconductor die package 200 described herein. In some embodiments, one or more operations described with reference to FIGS. 8A-8D may be performed after one or more operations described with reference to FIGS. 7A-7D. In some embodiments, one or more of the operations described with reference to FIGS. 8A-8D may be performed by one or more of the semiconductor processing equipment 102 - 114 and/or the wafer/die transfer equipment 116 . In some embodiments, one or more of the operations described with reference to FIGS. 8A-8D may be performed by other semiconductor processing equipment.

As shown in FIG. 8A , a redistribution structure 232 of the semiconductor die package 200 may be formed on the second semiconductor die 204 . One or more of semiconductor processing equipment 102 - 114 may be used to form one or more dielectric layers 234 and multiple metallization layers 236 in dielectric layer 234 to form redistribution structure 232 . For example, the deposition apparatus 102 may be used to deposit a first layer of one or more dielectric layers 234 (eg, by using CVD techniques, ALD techniques, PVD techniques, and/or other types of deposition techniques); the etching apparatus 108 may be Portions of the first layer are removed to form recesses in the first layer; and deposition device 102 and/or plating device 112 may form the first metallization layer of multi-layer metallization layer 236 in the recesses (by using CVD techniques , ALD technology, PVD technology, electroplating technology and/or other types of deposition technology). At least a portion of the first metallization layer may be electrically connected and/or physically connected to one or more BTSV structures 238 . Deposition equipment 102 , etching equipment 108 , plating equipment 112 and/or other semiconductor processing equipment may continue to perform similar operations to form redistribution structure 232 until a sufficient or desired configuration of metallization layer 236 is achieved.

As shown in FIG. 8B , recesses 802 may be formed in one or more dielectric layers 234 . Recesses 802 may be formed to expose a portion of metallization layer 236 in redistribution structure 232 . Accordingly, recesses 802 may be formed in one or more portions of metallization layer 236 .

In some embodiments, recesses 802 are formed using patterns in a photoresist layer. In such embodiments, deposition apparatus 102 is used to form a photoresist layer on one or more dielectric layers 234 . The exposure device 104 is used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developing device 106 is used to develop and remove some portions of the photoresist layer to reveal the pattern. Etching apparatus 108 is used to etch through one or more dielectric layers 234 to form one or more recesses 802 . In some embodiments, the etching operation includes plasma etching technology, wet chemical etching technology, and/or other types of etching technology. In some embodiments, a photoresist removal device is used to remove remaining portions of the photoresist layer (eg, through chemical strippers, plasma ashing, and/or other techniques). In some embodiments, as an alternative technique, a hard mask layer is used to form the recesses 802 based on the pattern.

As shown in FIG. 8C , an under-bump metal layer 244 may be formed in the recess 802 . The deposition equipment 102 and/or the plating equipment 112 may deposit under the bumps through CVD technology, PVD technology, ALD technology, electroplating technology, other technologies described with reference to FIG. 1 and/or deposition technologies different from those described with reference to FIG. 1 Metal layer 244. In some embodiments, a continuous layer of conductive material is deposited on the top surface of redistribution structure 232 including recesses 802 . Subsequently, a patterning operation is performed to form a pattern on the successive layers of conductive material, for example by a deposition device 102, an exposure device 104 and a development device 106, and the layer of conductive material is removed based on the pattern by an etching device 108. Some parts of consecutive layers. The remaining portion of the continuous layer of conductive material may correspond to under-bump metal layer 244 .

As shown in FIG. 8D , conductive terminals 246 on under-bump metal layer 244 may be formed in recesses 802 . In some embodiments, plating equipment 112 is used to form conductive terminals 246 through electroplating techniques. In some embodiments, solder is disposed in recess 802 to form conductive terminal 246 .

As described above, FIGS. 8A to 8D are provided as an example. Other examples may differ from those described with reference to Figures 8A-8D.

Figure 9 is a schematic diagram illustrating example components of assembly 900 described herein. In some embodiments, one or more of the semiconductor processing equipment 102 - 114 and/or the wafer/die transfer equipment 116 may include one or more components 900 and/or one or more components of the component 900 . As shown in FIG. 9 , component 900 may include bus 910 , processor 920 , memory 930 , input component 940 , output component 950 , and communication component 960 .

Bus 910 may include one or more components that enable multiple components of assembly 900 to communicate in a wired and/or wireless manner. The bus 910 may couple two or more components shown in FIG. 9 together (for example, through operative coupling, communicative coupling, electronic coupling, and/or electric coupling). coupling)). The processor 920 may include a central processing unit, an image processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit -specific integrated circuit) and/or other types of processor components. Processor 920 is implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 920 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

Memory 930 may include volatile and/or non-volatile memory. For example, the memory 930 may include random access memory (RAM), read only memory (ROM), hard disk drive, and/or other types of memory (such as flash memory, magnetic memory). and/or optical memory). Memory 930 may include internal memory (eg, RAM, ROM, or hard disk) and/or removable memory (eg, removable via a universal serial bus connection). Memory 930 may be a non-transitory computer-readable medium. Memory 930 stores information, instructions and/or software (eg, one or more software applications) related to the operation of component 900 . In some embodiments, memory 930 may include one or more memories coupled to one or more processors (eg, processor 920 ) via bus 910 .

The input component 940 enables the component 900 to receive input signals, such as user input signals and/or sensing input signals. For example, the input component 940 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an acceleration sensor, a gyroscope, and/or a sensor. actuator. The output member 950 enables the component 900 to provide an output signal, such as via a display, a speaker, and/or a light emitting diode. The communication component 960 enables the component 900 to communicate with other components through wired and/or wireless communication. For example, communication component 960 may include a receiver, transmitter, transceiver, modem, network interface card, and/or antenna.

Component 900 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (eg, memory 930 ) may store a set of instructions (eg, one or more instructions or code) executed by processor 920 . Processor 920 may execute this set of instructions to perform one or more operations or processes described herein. In some embodiments, execution of the set of instructions by one or more processors 920 causes one or more processors 920 and/or component 900 to perform one or more operations or processes described herein. In some embodiments, one or more operations or processes described herein are performed using hardwired circuitry or a combination of hardwired circuitry and instructions. Additionally or alternatively, processor 920 may be configured to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any specific combination of hardwired circuitry and software.

The component labels and configuration methods shown in Figure 9 are provided as an example. Assembly 900 may include additional components, fewer components, different components, or components configured in a different manner than that shown in FIG. 9 . Additionally or alternatively, a set of components (eg, one or more components) of assembly 900 may perform one or more functions described as being performed by other sets of components of assembly 900 .

FIG. 10 is a flow diagram illustrating an example process 1000 associated with forming a semiconductor die package. In some embodiments, one or more process blocks of FIG. 10 are performed by one or more semiconductor process equipment (eg, one or more of semiconductor process equipment 102 - 114 ). Additionally or alternatively, one or more of the components shown in FIG. 10 may be performed by one or more components of component 900 (eg, processor 920, memory 930, input component 940, output component 950, and/or communication component 960). Crafting blocks.

As further shown in FIG. 10 , process 1000 may include forming a high-k dielectric layer on a semiconductor die (operation 1010 ). For example, as described herein, one or more of semiconductor process equipment 102 - 114 may be used to form high-k dielectric layer 242 on second semiconductor die 204 . In some embodiments, high-k dielectric layer 242 has negative charge polarity. In some embodiments, the second semiconductor die 204 and the first semiconductor die 202 are bonded to each other at a bonding interface 206 .

As further shown in FIG. 10 , process 1000 may include forming a portion of the interconnect region through the high-k dielectric layer and the component region of the semiconductor die and extending into the semiconductor die to expose the interconnect region. Recessing of a portion of the metallization layer (operation 1020). For example, as described herein, one or more of semiconductor process equipment 102 - 114 may be used to form device region 212 through high-k dielectric layer 242 and second semiconductor die 204 and extending into the second semiconductor die 204 . The interconnect region 214 of the semiconductor die 204 is recessed 702 to expose a portion of the metallization layer 228 in the interconnect region 214 .

As further shown in FIG. 10 , process 1000 may include forming via structures in recesses (operation 1030 ). For example, as described herein, one or more of semiconductor process equipment 102 - 114 may be used to form BTSV structure 238 in recess 702 .

Process 1000 may include additional embodiments, such as a single embodiment as described below or any combination of embodiments and/or in conjunction with one or more other processes described elsewhere herein.

In the first embodiment, forming the BTSV structure 238 includes forming the BTSV structure 238 adjacent one or more semiconductor devices 216 in the device region 212 of the second semiconductor die 204 .

In a second embodiment, separately or in combination with the first embodiment, forming BTSV structure 238 includes forming BTSV structure 238 through p-type well 302 associated with one or more semiconductor components 216 , wherein p-type well 302 Adjacent to n-type well 304 associated with one or more semiconductor components 216 .

In the third embodiment, alone or in combination with the first and second embodiments, forming the high-k dielectric layer 242 includes forming a layer having a thickness of about Until about/> high-k dielectric layer 242 in the range.

In the fourth embodiment, alone or in combination with the first through third embodiments, forming the high-k dielectric layer 242 includes depositing one or more materials with intrinsically negative charge polarity to form the high-k dielectric layer 242 . Electrical layer 242.

In a fifth embodiment, alone or in combination with the first to fourth embodiments, the one or more materials include at least one of hafnium oxide, aluminum oxide, tantalum oxide, gallium oxide, titanium oxide, or niobium oxide .

In a sixth embodiment, alone or in combination with the first to fifth embodiments, lattice defects created during deposition of the one or more materials result in intrinsically negative charge polarity.

In a seventh embodiment, alone or combined with the first to sixth embodiments, fabrication 1000 includes forming a buffer oxide layer 240 on the device region 212, wherein forming the high-k dielectric layer 242 includes forming the buffer oxide layer 240 on the device region 212. A high-k dielectric layer 242 is formed on 240 .

In an eighth embodiment, alone or in combination with the first to seventh embodiments, the process 1000 includes bonding the first semiconductor die 202 and the second semiconductor die 204 in a WoW configuration by performing a hybrid bonding operation. together.

Although FIG. 10 illustrates example operations of process 1000, in some embodiments process 1000 includes additional operations, fewer operations, different operations, or operations in a different order than that shown in FIG. 10. Additionally or alternatively, two or more operations of process 1000 may be performed in parallel.

In summary, a semiconductor die package (for example, a WoW semiconductor die package) includes a high-k dielectric layer on a component region of a first semiconductor die (for example, a silicon substrate), and the first semiconductor die The die is bonded to the second semiconductor die in a WoW configuration. TSV structures, such as BTSV structures, may be formed across the device area. The high-k dielectric layer has an intrinsically negative charge polarity and provides a coupling voltage to adjust the potential within the device region. In particular, negative charges (e.g., electron carriers) in the high-k dielectric layer attract hole carriers in the device region, which suppresses the effects of surface defects formed when etching the recesses housing the TSV structures. Leading trap auxiliary channel. Accordingly, the high-k dielectric layers described herein reduce the occurrence and/or magnitude of leakage currents within semiconductor devices included in the device regions of the first semiconductor die. This can improve the performance of the semiconductor devices and/or enable the semiconductor devices to be arranged closer together and placed closer to the TSV structure, shorten the pitch of the semiconductor devices in the first semiconductor die and increase the density of the semiconductor devices, etc.

As described in greater detail above, some embodiments herein provide a semiconductor die package. A semiconductor die package includes: a first semiconductor die; a second semiconductor die bonded to the first semiconductor die on a first side and including: a component region including one or more semiconductor components; and interconnects A region is located between the component region and the first semiconductor die. In addition, the semiconductor die package further includes: a dielectric layer located on a second side of the second semiconductor die relative to the first side, wherein the dielectric layer has an intrinsic negative charge polarity; and a conductor A via structure extends through the dielectric layer and the component area, and extends into a portion of the interconnection area.

In some embodiments, the via structure is a silicon via structure extending through a p-type well in the component region but not through an n-type well in the component region. In some embodiments, the distance between the sidewalls of the silicon via structure and the edge of the p-type well is in the range of about 0.2 μm to about 2 μm. In some embodiments, the dielectric layer is configured such that hole carriers in the component region are attracted to electron carriers in the dielectric layer. In some embodiments, the dielectric layer has a thickness of about Until about/> within the range. In some embodiments, the dielectric layer includes at least one of hafnium oxide, aluminum oxide, tantalum oxide, gallium oxide, titanium oxide, or niobium oxide. In some embodiments, the semiconductor die package further includes: a buffer oxide layer located between the second semiconductor die and the dielectric layer, wherein the via hole structure extends through the buffer oxide layer.

As described in greater detail above, some embodiments herein provide a method of forming a semiconductor die package. The method includes: forming a high-k dielectric layer on a semiconductor die, wherein the high-k dielectric layer has a negative charge polarity; forming a layer through the high-k dielectric layer and the a recess in a component region of a semiconductor die and extending into a portion of an interconnect region of the semiconductor die to expose a portion of a metallization layer in the interconnect region; and forming a via hole in the recess structure.

In some embodiments, forming the via structure includes forming a backside silicon via structure adjacent one or more semiconductor components in the component region of the semiconductor die. In some embodiments, forming the backside TSV structure includes forming the backside TSV structure through a p-type well associated with the one or more semiconductor components, wherein the p-type well is adjacent n-type well associated with the one or more semiconductor components. In some embodiments, forming the high-k dielectric layer includes forming a layer having a thickness of about Until about/> The thickness of the high-k dielectric layer is in the range. In some embodiments, forming the high-k dielectric layer includes depositing one or more materials with intrinsically negative charge polarity to form the high-k dielectric layer. In some embodiments, the one or more materials include at least one of hafnium oxide, aluminum oxide, tantalum oxide, gallium oxide, titanium oxide, or niobium oxide. In some embodiments, lattice defects formed during deposition of the one or more materials result in the intrinsic negative charge polarity. In some embodiments, the method for forming a semiconductor die package further includes: forming a buffer oxide layer on the component region, wherein forming the high-k dielectric layer includes: forming the buffer oxide layer on the buffer oxide layer. High dielectric constant dielectric layer. In some embodiments, the method of forming a semiconductor die package further includes performing a hybrid bonding operation to bond the semiconductor die with another semiconductor die in a die-on-wafer configuration.

As described in greater detail above, some embodiments herein provide a semiconductor die package. The semiconductor die package includes: a first semiconductor die; a second semiconductor die bonded to the first semiconductor die with a first side and including: a component region including one or more semiconductor components; and A connection area is located between the component area and the first semiconductor die. In addition, the semiconductor die package further includes: a high-k dielectric layer on a second side of the second semiconductor die relative to the first side, wherein the high-k dielectric layer has intrinsically negative charge polarity; and a silicon via structure extending through the high-k dielectric layer and the device region and into a portion of the interconnect region, wherein the silicon through silicon structure extends through a p-type well in the device region adjacent to the n-type well, and wherein the intrinsic negative charge polarity of the high-k dielectric layer is configured to inhibit transition from the p-type well to the n-type Well leakage.

In some embodiments, the second semiconductor die has a thickness in the range of about 0.5 μm to about 5 μm. In some embodiments, the high-k dielectric layer has an equivalent surface charge density in the range of about -8·10 ^-9 C/cm ² to about -1.6·10 ^-7 C/cm ² . In some embodiments, the high-k dielectric layer includes at least one of hafnium oxide, aluminum oxide, tantalum oxide, gallium oxide, titanium oxide, or niobium oxide.

The foregoing summary summarizes the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same purposes as the embodiments described herein. Same advantages. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and they can make various changes, substitutions and alterations thereto without departing from the spirit and scope of the disclosure. .

Claims (12)

1. A semiconductor chip package, including: the first semiconductor die; A second semiconductor die bonded to the first semiconductor die on a first side and comprising: a component area, including one or more semiconductor components; and An interconnection area located between the component area and the first semiconductor die; a dielectric layer on a second side of the second semiconductor die relative to the first side, wherein the dielectric layer has an intrinsically negative charge polarity; and A via structure extends through the dielectric layer and the component area, and extends into a portion of the interconnect area. 2. The semiconductor die package of claim 1, wherein the via structure is silicon extending through a p-type well in the component region but not through an n-type well in the component region Perforated structure. 3. The semiconductor die package of claim 2, wherein a distance between a sidewall of the silicon via structure and an edge of the p-type well is in the range of 0.2 microns to 2 microns. 4. The semiconductor die package of claim 1, wherein the dielectric layer is configured such that hole carriers in the device region are attracted to electron carriers in the dielectric layer. 5. The semiconductor die package of claim 1, wherein the dielectric layer has a thickness in the range of 20 Angstroms to 500 Angstroms. 6. The semiconductor die package of claim 1, wherein the dielectric layer includes at least one of hafnium oxide, aluminum oxide, tantalum oxide, gallium oxide, titanium oxide, or niobium oxide. 7. The semiconductor die package according to claim 1, further comprising: A buffer oxide layer is located between the second semiconductor die and the dielectric layer, wherein the via hole structure extends through the buffer oxide layer. 8. A method for forming semiconductor chip packaging, including: forming a high-k dielectric layer on the semiconductor die, wherein the high-k dielectric layer has a negative charge polarity; Forming a metallization layer through the high-k dielectric layer and a component region of the semiconductor die and extending into a portion of the interconnect region of the semiconductor die to expose the interconnect region a depression in a part of A via hole structure is formed in the recess. 9. The method of forming a semiconductor die package according to claim 8, wherein forming the via hole structure includes: A backside silicon via structure is formed adjacent one or more semiconductor devices in the device region of the semiconductor die. 10. The method of forming a semiconductor die package according to claim 9, wherein forming the backside silicon via structure includes: The backside TSV structure is formed through a p-type well associated with the one or more semiconductor components, wherein the p-type well is adjacent an n-type well associated with the one or more semiconductor components . 11. The method of forming a semiconductor die package according to claim 8, further comprising: A hybrid bonding operation is performed to bond the semiconductor die together with another semiconductor die in a wafer-on-wafer type configuration. 12. A semiconductor chip package, including: The first semiconductor die; The second semiconductor die is bonded to the first semiconductor die with a first side and includes: a component area, including one or more semiconductor components; and An interconnection area located between the component area and the first semiconductor die; a high-k dielectric layer on a second side of the second semiconductor die relative to the first side, wherein the high-k dielectric layer has an intrinsically negative charge polarity; and A through-silicon via structure extending through the high-k dielectric layer and the device region and extending into a portion of the interconnect region, wherein the through-silicon via structure extends through an adjacent region in the device region A p-type well in an n-type well, and wherein the intrinsic negative charge polarity of the high-k dielectric layer is configured to inhibit leakage from the p-type well to the n-type well.