CN117413628A - Storage array, preparation method, read and write control method, memory and electronic device - Google Patents
Storage array, preparation method, read and write control method, memory and electronic device Download PDFInfo
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Abstract
一种存储阵列、制备方法、读写控制方法、存储器及电子设备，用以提高存储阵列的存储密度。其中，存储阵列包括：交替堆叠的至少一层绝缘层和至少一层第二金属层、设置在每层绝缘层中的M×N个第一孔和设置在每层第二金属层中的对应的M×N个第二孔、贯穿每个对应的第一孔和第二孔的第一金属层和设置在每个第二孔内且环绕第一金属层的存储层。该存储阵列中每层第二金属层所环绕的孔可单独刻蚀形成，如此可降低每层第二金属层所环绕的孔的孔径对刻蚀能力的依赖而做到足够小，进而使得孔内生成的存储层的直径也可以足够小，通过减小存储层的直径，能在同样尺寸的存储阵列中集成更多的存储单元，有效提高存储阵列的存储密度。
A storage array, preparation method, reading and writing control method, memory and electronic equipment are used to improve the storage density of the storage array. Wherein, the memory array includes: at least one insulating layer and at least one second metal layer alternately stacked, M×N first holes provided in each insulating layer and corresponding holes provided in each second metal layer. M×N second holes, a first metal layer penetrating each corresponding first hole and second hole, and a storage layer disposed in each second hole and surrounding the first metal layer. The holes surrounded by each second metal layer in the memory array can be formed by etching separately. This can reduce the dependence of the hole diameter of each second metal layer on the etching ability and make it small enough, thereby making the holes small enough. The diameter of the internally generated storage layer can also be small enough. By reducing the diameter of the storage layer, more storage units can be integrated into a storage array of the same size, effectively increasing the storage density of the storage array.
Description
The present disclosure relates to the field of memory technologies, and in particular, to a memory array, a preparation method, a read-write control method, a memory, and an electronic device.
In recent years, with the development and popularization of semiconductor technology, a variety of new memories have been developed, such as a resistive random access memory (resistive random access memory, reRAM), a ferroelectric random access memory (ferroelectric random access memory, feRAM), a phase change random access memory (phase change random access memory, PCRAM), and a magnetic random access memory (magnetic random access memory, MRAM). These new memories have smaller memory cell sizes and can achieve faster access speeds with lower power consumption, and are now becoming more widely used.
However, in the prior art, memory arrays often have a strict manufacturing flow and a narrow process window. For example, in one existing method for manufacturing a memory array, deep holes must be etched first, and it should be understood that deep holes refer to holes having a large ratio of hole depth to hole diameter, and then a memory layer and a metal layer are grown in the deep holes. However, the aperture of the deep hole is limited by etching capability, so that the diameter of the storage layer grown in the deep hole is larger, and the larger the diameter of the storage layer is, the smaller the number of storage units which can be accommodated in the storage array with the same size is, which is further unfavorable for improving the density of the storage array.
In view of the foregoing, there is a need for a memory array for increasing the memory density of the memory array.
Disclosure of Invention
The application provides a memory array, a preparation method, a read-write control method, a memory and electronic equipment, which are used for improving the memory density of the memory array.
In a first aspect, the present application provides a memory array comprising: at least one insulating layer and at least one second metal layer alternately stacked; an m×n first holes provided in each insulating layer and a corresponding m×n second holes provided in each second metal layer, each first hole being coaxial with the corresponding second hole, and the aperture of each first hole being smaller than the aperture of the corresponding second hole; a first metal layer extending through each of the coaxial first and second holes; and a memory layer disposed in each of the second holes and surrounding the first metal layer. Wherein M is an integer greater than or equal to 2, N is a positive integer, or M is a positive integer, N is an integer greater than or equal to 2.
In the design, the insulating layers and the second metal layers are alternately stacked, and the aperture of the second hole formed in the second metal layer is larger than the aperture of the first hole formed in the insulating layer, which means that when the insulating layers are stacked on the second metal layer, the second hole must be etched in the second metal layer, because the aperture of the second hole of the second metal layer positioned on the lower layer cannot be larger than the aperture of the first hole of the insulating layer positioned on the upper layer in the stacked structure by one etching, the holes surrounded by each layer of the second metal layer in the storage array can be independently etched to form, so that the dependence of the aperture of the holes surrounded by each layer of the second metal layer on etching capability can be reduced to be small enough, the diameter of the storage layer generated in the holes can be small enough, more storage cells can be integrated in the storage array with the same size by reducing the diameter of the storage layer, and the storage density of the storage array can be effectively improved.
In one possible design, multiple second metal layers may be included in the stacked structure. Specifically, each second metal layer, one memory layer surrounded by the second metal layer, and the first metal layer surrounded by the memory layer may constitute one memory cell of the memory array. In this way, by providing a plurality of second metal layers, the memory array can form a three-dimensional memory array, and the memory density of the memory array can be further improved under the condition that the size of the memory array on a plane perpendicular to the stacking direction is unchanged.
In one possible design, the first metal layer includes a first end and a second end, where at least one of the first end and the second end is provided with a field effect transistor, for example, a memory array may further include a first field effect transistor disposed only at the first end of the first metal layer, or include a second field effect transistor disposed only at the second end of the first metal layer, or include a first field effect transistor disposed at the first end of the first metal layer in a stacking direction and a second field effect transistor disposed at the second end of the first metal layer in the stacking direction. Therefore, the on-off operation of the memory cells in the memory array can be realized through the field effect transistor, so that the read-write operation of the memory array can be completed.
In one possible design, the memory array may further include m×n first field effect transistors and m×n second field effect transistors corresponding to the m×n first metal layers, where a first electrode of each first field effect transistor is connected to a first end of the corresponding first metal layer, and second electrodes of N first field effect transistors in each row of the m×n first field effect transistors are connected to form a row word line of the memory array, where the row word line is used to conduct all first field effect transistors located on the corresponding row, and a column selection line of the memory array is formed after third electrodes of M first field effect transistors in each column of the m×n first field effect transistors are connected to each other, where the column selection line is used to select all first field effect transistors located on the corresponding column; correspondingly, the first electrode of each second field effect transistor is connected with the second end of the corresponding first metal layer in the stacking direction, the second electrodes of the M second field effect transistors in each column of the M x N second field effect transistors are connected to form a column word line of the memory array, the column word line is used for conducting all the second field effect transistors on the corresponding column, the third electrodes of the N second field effect transistors in each row of the M x N second field effect transistors are connected to form a row selection line of the memory array, and the row selection line is used for selecting all the second field effect transistors on the corresponding row. Wherein the second electrode is a grid electrode; the first electrode is a source and the third electrode is a drain, or the first electrode is a drain and the third electrode is a source.
In the above design, by disposing two sets of FETs at two ends of the first metal layer, the two sets of FETs can form two sets of word lines and select lines in quadrature, so that the transposed read-write operation of the memory array can be implemented through the two sets of word lines and select lines in quadrature, and the transposed read-write operation belongs to the memory array which is used frequently, so that the memory array is particularly suitable for the memory array where the internal operation needs to be implemented, such as the memory array which can include but is not limited to convolutional neural network (convolutional neural network, CNN), recurrent neural network (rerrent neural network, RNN), deep neural network (deep neural networks, DNN) or memory-enhanced neural network (memory-augmented neural network, man) and the modified memory array thereof.
In one possible design, the field effect transistor may be a surrounding channel field effect transistor (channel all around field effect transistor, CAAFET) or a metal oxide semiconductor field effect transistor (metallic oxide semiconductor field effect transistor, MOSFET). For example, considering that the MOSFET needs to be integrated on the substrate, the CAAFET may not need to be integrated on the substrate, so when the fet is disposed at the lower end of the first metal layer in the stacking direction, the fet may select the CAAFET or the MOSFET, and when the fet is disposed at the upper end of the first metal layer in the stacking direction, the fet may select the CAAFET, thereby further reducing the area requirement of the memory array on the plane perpendicular to the stacking direction, and further improving the integration level of the memory array.
In one possible design, one address line of the memory array is led out from each second metal layer, and the address line is used for selecting the memory cell on the corresponding second metal layer. In this way, all memory cells located on one second metal layer can be activated directly through the address line.
In one possible design, a target second metal layer exists in the memory array, at least two rows or at least two columns of adjacent second holes of the target second metal layer are separated by a non-conductive material, and any one second metal layer separated by the non-conductive material is led out of an address line of the memory array, where the address line is used for selecting a memory cell on a corresponding target second metal layer. Therefore, the second metal layer is divided into the plurality of second metal strips in the row direction or the column direction, so that part of memory cells on each layer of second metal layer can be read and written through each second metal strip, the capacitance load in the read-write operation process can be reduced, the read-write operation speed can be effectively improved, and the read-write operation feasibility can be improved. Furthermore, the memory array structure can also realize the memory addition calculation of the memory array, namely the controller can directly obtain the sum value of binary data stored by at least two memory units output by the memory array without the need of carrying out subsequent addition calculation by the controller, so that the working pressure of the controller can be reduced.
In one possible design, if the memory array is a resistive memory array, the memory layer may be composed of a metal oxide; alternatively, if the memory array is a ferroelectric memory array, the memory layer is composed of ferroelectric material; alternatively, if the memory array is a magnetic memory array, the memory layer is composed of a magnetic material; alternatively, if the memory array is a phase change memory array, the memory layer is composed of a phase change material. Therefore, the memory array structure provided by the application can be suitable for various memory arrays and has good universality.
In a second aspect, the present application provides a method for preparing a memory array, where the memory array is prepared by P times, and a subsequent preparation is stacked on a structure prepared in the previous preparation, and each preparation includes the following steps: depositing an insulating layer, etching the insulating layer to form M multiplied by N first holes, depositing a first metal layer in each first hole of the M multiplied by N first holes, depositing a second metal layer above the insulating layer and the first metal layer, etching the second metal layer to form M multiplied by N second holes, and forming a storage layer and a first metal layer surrounding the storage layer in each second hole of the M multiplied by N second holes, wherein P, M, N is a positive integer. By etching holes in each insulating layer or second metal layer deposited in the stacking direction, compared with the mode of stacking multiple insulating layers and etching holes in the second metal layer, the hole depth of each etched hole depends on the height of one layer deposited instead of the height of multiple layers, and the aperture of the hole can be reduced under the restriction of etching capability, so that more memory cells can be integrated in the memory array with the same size on the plane vertical to the stacking direction by reducing the aperture of the hole, and the memory density of the memory array is effectively improved.
In one possible design, after P preparations, it may further comprise: one end of each first metal layer is connected with the first FET, and the other end of each first metal layer is connected with the second FET. Thus, by arranging two sets of FETs at two ends of the first metal layer, the two sets of FETs can form two orthogonal sets of word lines and selection lines, and further transposed read-write operation of the memory array can be realized.
In one possible design, after the second metal layer is etched to form the mxn second holes, the method further includes: and forming a separation region between at least two rows or at least two columns of adjacent second holes on the second metal layer through a metal cutting process, and filling non-conductive materials in the separation region. Accordingly, after P preparations, further comprising: one end of each first metal layer is connected to the FET. Therefore, the second metal layer is divided into the plurality of second metal strips, and part of memory cells on each layer of second metal layer can be read and written through each second metal strip, so that the capacitor load in the read-write operation process is reduced, and the read-write operation speed is effectively improved.
In a third aspect, the present application provides a read-write control method, applicable to a controller, where the controller is connected to the storage array according to any one of the first aspect, and the method includes: transmitting a read control signal to the memory array, and receiving a read response signal returned by the memory array, wherein the read response signal comprises data to be read; or, sending a write control signal to the memory array; and receiving a write response signal sent by the storage array, wherein the write response signal is used for indicating write success or write failure.
In one possible design, where the memory array includes column select lines, row word lines, column word lines, and row select lines, the controller may further connect the column select lines, the row word lines, the column word lines, and the row select lines, respectively, the method further comprising: when the data to be read is the data in the memory array, sending a read control signal to the column selection line and the row word line; alternatively, when the data to be read is transposed data of the data in the memory array, a read control signal is sent to the column word lines and the row select lines.
In one possible design, where the memory array includes column select lines and row word lines, the column select lines may also be connected to sense amplifiers, and the controller may be connected to the column select lines, the row word lines, and the sense amplifiers, the method further comprising: and transmitting a read control signal to at least two memory cells through a row word line and a column selection line, acquiring the current magnitude on the column selection line induced by the sense amplifier, and determining the sum of data stored in the at least two memory cells according to the current magnitude.
In a fourth aspect, the present application provides a memory, including a controller and a memory array according to any one of the first aspect, where the controller is configured to perform the read-write control method according to any one of the third aspect.
In a fifth aspect, the present application provides an electronic device comprising a printed circuit board (printed circuit board, PCB) and a memory according to any one of the designs of the fourth aspect, wherein the memory is arranged on a surface of the PCB.
Specifically, the electronic device includes, but is not limited to: smart phones, smart watches, tablet computers, virtual Reality (VR) devices, augmented reality (augmented reality, AR) devices, in-vehicle devices, desktop computers, personal computers, handheld computers, or personal digital assistants.
The various aspects described above, or other aspects of the present application, are described in detail in the following examples.
FIG. 1 is a schematic diagram illustrating an internal structure of a memory to which embodiments of the present application are applicable;
FIG. 2 illustrates a schematic diagram of a memory array provided by the industry;
FIG. 3 is a schematic diagram illustrating a manufacturing process corresponding to a memory array provided by the industry;
FIG. 4A schematically illustrates a perspective view of a memory array according to an embodiment of the present disclosure;
FIG. 4B illustrates a cross-sectional front view of a memory array provided by an embodiment of the present application;
FIG. 4C illustrates a cross-sectional top view of a memory array provided by embodiments of the present application;
Fig. 5 schematically illustrates a possible stacked structure of an insulating layer and a second metal layer according to an embodiment of the present application;
FIG. 6A illustrates a cross-sectional front view of another memory array provided by embodiments of the present application;
FIG. 6B illustrates an equivalent circuit block diagram of a memory array provided by an embodiment of the present application;
fig. 7A is a schematic diagram schematically illustrating an operation principle of a memory cell according to an embodiment of the present application;
FIG. 7B is a graph illustrating operating voltage versus operating current for a memory cell according to an embodiment of the present application;
FIG. 8A is a schematic diagram illustrating a perspective structure of yet another memory array according to an embodiment of the present disclosure;
FIG. 8B illustrates a cross-sectional front view of yet another memory array provided by embodiments of the present application;
FIG. 8C illustrates a cross-sectional top view of yet another memory array provided by embodiments of the present application;
FIG. 9A is a schematic diagram schematically illustrating a perspective structure of still another memory array according to an embodiment of the present disclosure;
FIG. 9B illustrates a cross-sectional front view of yet another memory array provided by embodiments of the present application;
FIG. 9C illustrates a cross-sectional top view of yet another memory array provided by embodiments of the present application;
FIG. 10 illustrates an equivalent circuit block diagram of another memory array provided by an embodiment of the present application;
FIG. 11 schematically illustrates a process for preparing a memory array according to an embodiment of the present application;
fig. 12 is a schematic diagram schematically illustrating a specific structure of a memory according to an embodiment of the present application.
The memory arrays disclosed herein may be suitable for devices having memory capabilities, for example, for memory devices having only memory capabilities, such as memory, but also for electronic devices having memory capabilities and also having other capabilities (e.g., read and write functions). The electronic device may be a portable electronic device that includes functionality such as a personal digital assistant and/or a music player, such as a cell phone, tablet computer, wearable device (e.g., smart watch) with wireless communication functionality, or an in-vehicle device. Exemplary embodiments of portable electronic devices include, but are not limited to, piggy-back Or other operating system. The portable electronic device may also be a portable electronic device such as a Laptop computer (Laptop) having a touch sensitive surface, e.g. a touch panel. It should also be appreciated that in other embodiments of the present application, the electronic device described above may also be a desktop computer having a touch-sensitive surface (e.g., a touch panel).
The memory may be, for example, volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), flash memory (FE), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), direct RAM (DRAM), and direct RAM (DR RAM), as well as new types of memory such as resistive RAM (resistive random access memory, reRAM), ferroelectric RAM (ferroelectric random access memory, feRAM), phase change RAM (phase change random access memory, PCRAM), or magnetic RAM (magnetic random access memory, MRAM). The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable Programmable ROM (EPROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. It should be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
Fig. 1 schematically illustrates an internal structure of a memory to which the embodiments of the present application are applicable.
It should be understood that the illustrated memory 100 is only one example, and that the memory 100 may have more or fewer components than shown in the figures, may combine two or more components, or may have different configurations of components. The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.
The various components of memory 100 are described in detail below in conjunction with FIG. 1:
as shown in fig. 1, memory 100 may include a memory array 110 and a controller 120. The memory array 110 is used to store data, and is a matrix array formed by arranging a plurality of memory cells in rows and columns, and each memory cell can be used to store 1-bit or multi-bit binary data, such as "0" and/or "1". The plurality of storage units may be located on different tracks of the same disk, or may be located on different disks, which is not limited in particular. The controller 120 is used to perform a read operation or a write operation on data in the memory array 110, and is a device with control capability. The controller 120 may be coupled to the memory array 110, for example, by a bus connection. The controller 120 may include a number of functional components therein, such as including, but not limited to, drive circuitry, decoding circuitry, and amplifier circuitry. These functional components may be provided as separate devices, may be implemented in one device, or may be provided in at least two devices in any combination, and are not particularly limited.
With continued reference to fig. 1, the controller 120 may also be connected to an external device 200, and the external device 200 may be, for example, a read-write device or a processor. In reading/writing data, the external device 200 may send a read/write request to the controller 120, where the read/write request carries row address information and column address information of a target memory cell to be read/written. The controller 120 decodes the row address information in the read/write request to determine the row where the target storage unit is located, and starts all storage units corresponding to the row where the target storage unit is located by decoding the selection signal, then decodes the column address information in the read/write request to obtain the column where the target storage unit is located, and further reads the data stored in the target storage unit at the column and sends the data to the external device 200, or writes the data to be written sent by the external device 200 into the target storage unit at the column.
Although not shown in fig. 1, the memory 100 may further include other components, such as a main memory data register (memory data register, MDR) and a main memory address register (memory address register, MAR), which are not described herein.
FIG. 2 illustrates an exemplary architecture of a memory array provided in the industry A schematic view, wherein (a) in fig. 2 shows along the illustration L 12 A front view of the memory array is cut in plan view, and fig. 2 (B) shows a view along the drawing L 11 A cross-sectional plan view of the memory array obtained by planar dicing. Fig. 3 is a schematic diagram schematically illustrating a preparation flow corresponding to the storage array, and referring to fig. 2 and 3, the preparation flow of the storage array mainly includes the following steps:
step 1, depositing and forming insulating layers and second metal layers which are alternately stacked to obtain a stacked structure shown in (A) of fig. 3;
step 2, etching the stacked structure shown in (A) of fig. 3 to form holes, thereby obtaining a structure shown in (B) of fig. 3;
step 3, depositing a memory layer in the hole shown in (B) in fig. 3 to obtain a structure shown in (C) in fig. 3, wherein the memory layer is a layer which is formed by a memory material and is used for storing data in a memory array, and the memory material can be a capacitive material, for example, a ferroelectric material in a ferroelectric memory array, a metal oxide in a resistive memory array, a magnetic material in a magnetic memory array, or a phase change material in a phase change memory array;
step 4, depositing a first metal layer on the inner side of the storage layer shown in (C) of fig. 3, to obtain a structure shown in (D) of fig. 3.
In the above memory array, as shown in fig. 2 (a), one memory cell in the memory array is formed by any one of the second metal layer, the memory layer surrounded by the second metal layer, and the first metal layer surrounded by the memory layer. In this way, the memory array can constitute a three-dimensional memory array in the case where at least two second metal layers and at least one insulating layer are stacked. In this three-dimensional memory array, the aperture (i.e., d shown in fig. 2 (B)) of the hole determines the number of memory cells that can be included in the memory array in a plane perpendicular to the stacking direction (i.e., a plane shown in fig. 2 (B)), and when the aperture d of the hole is larger, the number of memory cells included in the memory array of the same size in the plane perpendicular to the stacking direction is smaller, the memory density of the memory array is lower, and when the aperture d of the hole is smaller, the number of memory cells included in the memory array of the same size in the plane perpendicular to the stacking direction is larger, and the memory density of the memory array is higher. However, in the above-described production process, the hole is directly obtained by etching the second metal layer and the insulating layer alternately stacked in plural layers, in which case the hole diameter d of the hole is strictly dependent on etching ability, which in turn is affected by hole depth, and the deeper the hole is, the worse the etching ability is, which in turn makes the hole diameter d of the hole larger, so that in the case of stacking more second metal layers and insulating layers, the hole diameter d of the hole cannot be made sufficiently small due to the restriction of etching ability, which in turn makes the number of holes that can be contained in a memory array of the same size on a plane perpendicular to the stacking direction smaller, in other words, the number of memory cells that can be contained in a memory array of the same size on a plane perpendicular to the stacking direction smaller, which is obviously disadvantageous for improving the memory density of the memory array.
Based on this, the embodiment of the application provides a memory array, which is used for independently etching holes in each second metal layer, so as to reduce the limitation of the aperture of the holes on etching capability, so that the aperture of the holes can be made smaller, further the memory array with the same size on the plane perpendicular to the stacking direction can contain more memory cells, and the memory density of the memory array is effectively improved.
Possible structures of the memory array in the embodiments of the present application are described below through specific embodiments.
It is noted that in the following description of the present application, "plurality" may be understood as "at least two". "and/or", describe the association relationship of the associated objects, and the representation may have three relationships, for example, a and/or B may represent: a alone, a and B together, and B alone, wherein a, B may be singular or plural. "the following item(s)" or "items(s)" or the like, refer to any combination of these items, including any combination of single item(s) or plural item(s). For example, one (or more) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
And, unless specifically stated otherwise, the embodiments herein refer to "first," "second," etc. ordinal numbers for the purpose of distinguishing between the descriptions and not to indicate or imply relative importance, nor to indicate or imply a sequence. For example, the "first metal layer" and "second metal layer" indicated below are merely metal layers for indicating different positions, and are not different in order, priority, or importance.
Fig. 4A schematically illustrates a perspective view of a memory array (for understanding, the insulating layer is drawn as a transparent structure in fig. 4A), fig. 4B illustrates a front cross-sectional view of the memory array, fig. 4C illustrates a top cross-sectional view of the memory array, where the front cross-sectional view shown in fig. 4B is along L shown in fig. 4C 22 The memory cell is cut in a plane, and the top view of the cross section shown in FIG. 4C is along L shown in FIG. 4B 21 And (3) cutting the memory cell in a plane. Referring to fig. 4A, 4B and 4C, it is shown that:
in this example, the memory array includes at least one insulating layer and at least one second metal layer stacked alternately, m×n first holes provided in each insulating layer and corresponding m×n second holes provided in each second metal layer (first holes and second Kong Canzhao are shown in fig. 4B), first metal layers penetrating the corresponding first holes and second holes, and memory layers provided in the second holes and surrounding the first metal layers (the description of the relevant contents of the memory layers may be referred to above, and the details of which will not be repeated here). Wherein each corresponding first hole and second hole are coaxial, and the aperture of each corresponding first hole is smaller than the aperture of the second hole. Since the first and second coaxial holes share mxn parts, the first metal layer penetrates the first and second coaxial holes, and thus the number of the first metal layers is also mxn. Wherein M is an integer greater than or equal to 2, N is a positive integer, or M is a positive integer, N is an integer greater than or equal to 2.
Further exemplary, suppose the V illustrated in FIG. 4C 2 The direction is the row direction, V illustrated in FIG. 4C 3 The direction is the column direction, the memory array is oriented perpendicular to the stacking direction (i.e., V as illustrated in FIG. 4B 1 Direction) may form an array structure of M×N, M being V as illustrated in FIG. 4C 2 The number of holes in the direction, N is V as illustrated in FIG. 4C 3 Number of holes in the direction. For example, when M is 1 and N is an integer greater than or equal to 2, the memory array is perpendicular to the stacking direction V 1 A single row array structure is formed on the plane of the memory array, and N memory cells are contained in the single row; when M is an integer greater than or equal to 2 and N is 1, the memory array is perpendicular to the stacking direction V 1 A single-column array structure is formed on the plane of the memory array, and M memory cells are contained in the single column; when M and N are integers greater than or equal to 2, the memory array is perpendicular to the stacking direction V 1 A multi-row multi-column memory array such as the 4-row 4-column array structure illustrated in fig. 4A.
In the embodiment of the present application, as shown in fig. 4B, each of the second metal layer, one of the memory layers surrounded by the second metal layer, and the first metal layer surrounded by the memory layer may form one memory cell in the memory array. Since the insulating layers and the second metal layers are alternately stacked, the number of insulating layers and the number of second metal layers are the same or differ by 1. For example, fig. 5 schematically illustrates a possible stacked structure of an insulating layer and a second metal layer according to an embodiment of the present application, as shown in fig. 5:
When the number of insulating layers and the number of second metal layers are both 1, the stacked structure includes only one insulating layer and one second metal layer, and the insulating layer may be located on the lower side of the second metal layer as illustrated in fig. 5 (a) or may be located on the upper side of the second metal layer as illustrated in fig. 5 (B). In this case, the memory array is in the stacking direction V 1 Only one layer of memory cells is included, so that the memory array forms a two-dimensional memory array;
when the number of insulating layers is 1 and the number of second metal layers is 2, the stacked structure includes one insulating layer and two second metal layers as illustrated in fig. 5 (C), with the insulating layer sandwiched between the two second metal layers.In this case, the memory array is in the stacking direction V 1 The upper layer comprises two layers of memory units, so that the memory array forms a three-dimensional memory array;
when the number of insulating layers is 2 and the number of second metal layers is 1, the stacked structure includes two insulating layers and one second metal layer as illustrated in fig. 5 (D), with the second metal layer sandwiched between the two insulating layers. In this case, the memory array is in the stacking direction V 1 Only one layer of memory cells is included, so that the memory array forms a two-dimensional memory array;
When the number of the insulating layers and the number of the second metal layers are both greater than or equal to 2, the stacked structure includes at least two insulating layers and at least two second metal layers, and the at least two insulating layers and the at least two second metal layers may be alternately stacked in the manner of the insulating layers, the second metal layers, and … …, or may be alternately stacked in the manner of the second metal layers, the insulating layers, and … …, and may be specifically implemented by one or more combinations of (a) to (D) in fig. 5. In this case, the memory array is in the stacking direction V 1 At least two layers of memory cells may be included, and thus the memory array constitutes a three-dimensional memory array. For example, in the memory array illustrated in FIG. 4B, the stacking direction V 1 4 second metal layers and 5 insulating layers are alternately stacked thereon, such that the memory array constitutes a 4 x 4 three-dimensional memory array.
In the embodiment of the application, each layer in the storage array may be implemented by one or more of the following:
the insulating layer is made of SiO 2 Realizing;
the storage layer is realized by a capacitance material;
the first metal layer is realized by tungsten (W) or molybdenum (Mo);
or,
the second metal layer is realized by tungsten (W) or molybdenum (Mo).
For example, when the memory array is a ferroelectric memory array, the memory layer may be composed of a ferroelectric material, such as a ferroelectric thin film. When the memory array is a magnetic memory array, the memory layer may be specifically composed of a magnetic material such as an oxide magnetic powder film, a metal alloy magnetic powder film, or a metal film. When the memory array is a phase change memory array, the memory layer may be specifically composed of a phase change material, such as a germanium antimony tellurium (Ge-Sb-Te, GST) film or an oxygen doped GST film. When the memory array is a resistive memory array, the memory film may be specifically composed of a resistive material such as a perovskite oxide film, a zinc manganese oxide film, or the like. It should be understood that the storage array and the corresponding storage layer may also be of other types, which are not listed here.
In the above embodiment, the insulating layers and the second metal layers are stacked alternately, and the aperture of the second hole provided in the second metal layer is larger than the aperture of the first hole provided in the insulating layer, which means that when the insulating layers are stacked on the second metal layer, the second hole must be etched in the second metal layer, because the aperture of the second hole of the second metal layer located at the lower layer cannot be made larger than the aperture of the first hole of the insulating layer located at the upper layer in the stacked structure by one etching, it can be seen that the hole surrounded by each second metal layer in the memory array can be formed by etching alone, so that the dependence of the aperture of the hole surrounded by each second metal layer on etching capability can be reduced to be made small enough, and further, the diameter of the memory layer generated in the hole can also be made small enough, by reducing the diameter of the memory layer, more memory cells can be integrated in the memory array of the same size on the plane in the vertical stacking direction, and the memory density of the memory array can be effectively improved.
In this embodiment, the memory array may further include, in addition to the insulating layer, the second metal layer, the memory layer, and the first metal layer described above, a layer disposed on the first metal layer in the stacking direction V 1 Is provided, a field effect transistor (field effect transistor, FET) at least one end of the transistor. Wherein the FET can be a metal oxide semiconductor field effect transistor (metallic oxide semiconductor field effect transistor, MOSFET), such as N-MOSFET or P-MOSFET, a surrounding channel field effect transistor (channel all around field effect transistor, CAAFET), or other devices capable of achieving switchingAnd turning off the functional device. Wherein the MOSFET is a device which is integrated on the substrate for use, and the CAAFET is a device which is not integrated on the substrate for use, so that if the first metal layer is in the stacking direction V 1 If a MOSFET is provided at the upper end of the illustration of (a) a lead is additionally provided to be led to the MOSFET of the substrate, if a first metal layer is provided in the stacking direction V 1 The CAAFET is arranged at the upper end of the diagram of the first metal layer, and then the CAAFET can be directly suspended at the upper end of the diagram of the first metal layer and connected through leads, so that compared with a MOSFET, the arrangement of the CAAFET can further reduce the width requirement of the storage array on a plane perpendicular to the stacking direction, and further improve the integration level of the storage array. It should be noted that the structure of the CAAFET may directly refer to the prior art, and embodiments of the present application are not limited in this regard.
Based on the above embodiments, several specific implementations of the memory array are further described below.
Detailed description of the invention
FIG. 6A is a front cross-sectional view illustrating another memory array according to an embodiment of the present application, including, in addition to the insulating layer, the second metal layer, the memory layer, and the first metal layer described above, a first metal layer disposed in each of the first metal layers in the stacking direction V, as shown in FIG. 6A 1 A first FET at the upper end of the diagram and a second FET at the lower end of the diagram. Since the memory array has M×N first holes in each insulating layer and M×N second holes corresponding to the first holes in each second metal layer, and the first metal layers penetrate the corresponding first holes and second holes, the memory array is arranged in the stacking direction V 1 Will include M N first FETs in the stacking direction V 1 Correspondingly, the lower end of the diagram of (c) includes M x N second FETs. Wherein the first FET or the second FET may be of the MOSFET or CAAFET type. For example, in one example, the first FET on the upper end of the diagram may be CAAFET, the second FET on the lower end of the diagram may be CAAFET or MOSFET, and the CAAFET may be directly suspended on the upper end of the diagram of the first metal layer and connected by wire, Without the need of arranging on the substrate like MOSFET and additionally arranging lead wires for connection, thereby reducing the number of memory array pairs perpendicular to the stacking direction V 1 The integration level of the memory array is improved.
FIG. 6B is an equivalent circuit diagram of the memory array, as shown in FIG. 6B, assuming diagram V 2 The direction is the row direction, diagram V 3 The direction is the column direction, M×N first metal layers are stacked in the stacking direction V 1 The M N first FETs disposed at the upper end of (a) include FETs 111, 112, … …, 11N, FET, 121, … …, 12N, … …, 1M1, 1M2, … …, 1MN, and M N first metal layers in the stacking direction V 1 The mxn second FETs disposed at the lower end of the diagram of (a) include FETs 211, 212, … …, 21N, FET, 221, 222, … …, 22N, … …, 2M1, 2M2, … …, 2MN, then, referring to fig. 6B, each of the first FETs and each of the second FETs includes a first electrode (i.e., electrode "1" as illustrated in fig. 6B), a second electrode (i.e., electrode "2" as illustrated in fig. 6B), and a third electrode (i.e., electrode "3" as illustrated in fig. 6B), the second electrode being the gate of the FET, the first electrode being the source of the FET, the third electrode being the drain of the FET, or the second electrode being the gate of the FET, the first electrode being the drain of the FET, the third electrode being the source of the FET, wherein:
The first electrode of each first FET is connected to the upper end of the corresponding first metal layer, the second electrodes of the N first FETs in each row are connected to form a Row Word Line (RWL) of the memory array, the third electrodes of the M first FETs in each column are connected to form a column select line (column select line, CSL) of the memory array, the row word line RWL is used for turning on all the first FETs in the corresponding row, and the column select line CSL is used for selecting all the first FETs in the corresponding column. For example, the second electrodes of the FETs 111, 112, … … FET11N in the first row are connected from the left side of the figure to form a row word line RWL 1 Through row word line RWL 1 The FETs 111 to 11N in the first row are turned on, and the second electrodes of the FETs 121, 122 and … … FET12N in the second row are connected to formRow word line RWL 2 Through row word line RWL 2 The second electrodes of the FETs 121-12N, … … on the second row and the FETs 1M1, 1M2, … … FET1MN on the M-th row are connected to form a row word line RWL M Through row word line RWL M The FETs 1M1 to 1MN on the M-th row are turned on, and the third electrodes of the FETs 111, 121, … … FET1M1 on the first column from the front side are connected to form a column selection line CSL 1 Through column select line CSL 1 The FETs 111-1M 1 on the first column can be selected, and the third electrodes of the FETs 112, 122 and … … FET1M2 on the second column are connected to form a column selection line CSL 2 Through column select line CSL 2 The FETs 112-1M 2, … … on the second column are selected, and the third electrodes of the FETs 11N, FET N, … … FET1MN on the N column are connected to form a column select line CSL N ；
Correspondingly, the first electrode of each second FET is connected to the lower end of the corresponding first metal layer, the third electrodes of the N second FETs on each row are connected to form a Row Select Line (RSL) of the memory array, the second electrodes of the M second FETs on each column are connected to form a Column Word Line (CWL) of the memory array, the row select line RSL is used to select all the second FETs on the corresponding row, and the column word line CWL is used to turn on all the second FETs on the corresponding column. For example, the third electrodes of the FETs 211, 212, … … and 21N in the first row are connected from the left side to form a row select line RSL 1 Through row selection line RSL 1 The FETs 211 to 21N in the first row are selected, and the third electrodes of the FETs 221, 222 and … … FET22N in the second row are connected to form a row selection line RSL 2 Through row selection line RSL 2 The FETs 221-22N, … … on the second row are selected, and the third electrodes of FET2M1, FET2M2, … … FET2MN on the M-th row are connected to form a row select line RSL M Through row selection line RSL M FETs 2M1 through FET2MN located on the M-th row can be selected, and accordingly, FETs 211, 221, respectively, on the first column from the front side of the figure,The second electrode of … … FET2M1 is connected to form a column word line CWL 1 Through column word line CWL 1 The FETs 211 to 2M1 on the first column are turned on, and the second electrodes of the FETs 212, 222 and … … FET2M2 on the second column are connected to form a column word line CWL 2 Through column word line CWL 2 The second electrodes of FETs 212-2M 2, … … on the second column and FETs 21N, FET N, … … FET2MN on the N column are connected to form a column word line CWL N Through column word line CWL N The FETs 21N to 2MN located on the nth column may be turned on.
In the circuit configuration illustrated in fig. 6B, the row word lines RWL and the column select lines CSL formed by the m×n first FETs are orthogonal to the row select lines RSL and the column word lines CWL formed by the m×n second FETs, so that, when the memory array is read or written, normal read or write operations in the row and column directions are illustrated by the row word lines RWL and the column select lines CSL formed by the m×n first FETs, or transposed read or write operations in the row and column directions are performed by the row select lines RSL and the column word lines CWL formed by the m×n second FETs (refer to the following for specific implementation, and are not described in detail here), that is, the memory array of this configuration can realize transposed operations.
Further exemplary, with continued reference to fig. 6B, assuming that the memory array includes P second metal layers, where P is a positive integer, each of the P second metal layers may lead out one Address Line (AL) of the memory array, where the address line AL is used to select all memory cells on the corresponding second metal layer. For example, the address line AL is led out from the second metal layer on the first layer from the upper side of the figure 1 Through column word line address line AL 1 All memory cells (i.e., memory layers) on the second metal layer of the first layer can be selected, and the address line AL is led out from the second metal layer on the second layer 2 Through column word line address line AL 2 All memory cells on the second metal layer of the second layer can be selected … …, and the second metal layer on the P layer leads out the address line AL P Through column word line address line AL P Optionally atAll memory cells on the second metal layer of the P-th layer. Also, in the memory array, each row word line RWL, each column select line CSL, each row select line RSL, each column word line CWL, and each address line AL are connected to a peripheral control circuit, which is illustratively located in the controller 120 illustrated in fig. 1. Any one of the first metal layers in the memory array, any one of the memory layers surrounding the first metal layer and the second metal layer surrounding the memory layer form a memory unit of the memory array, and the read-write operation of the memory unit is realized by controlling each connected control line through a peripheral control circuit so as to change the voltage difference at two ends of the memory layer contained in the memory unit. For ease of understanding, the following description exemplarily describes the read and write operations of any memory cell in the memory array in detail:
Write operation
Fig. 7A is a schematic diagram illustrating a structure of a memory cell according to an embodiment of the present application, and fig. 7B is a schematic diagram illustrating a relationship between an operating voltage and an operating current of the memory cell, where, as shown in fig. 7A and 7B, when no operating voltage is applied to a second metal layer of the memory cell, the memory layer is insulated, and both ends of the memory layer are in a high-resistance state, i.e., one end of the memory layer near the second metal layer and one end near the first metal layer are both in a low level. When a positive working voltage is applied to the second metal layer of the memory cell and exceeds the forming voltage of the memory layer, conductive fibers are formed in the memory layer, so that two ends of the memory layer are in a low-resistance state, at the moment, one end, close to the second metal layer, of the memory layer is displayed in a high level, and one end, close to the first metal layer, of the memory layer is displayed in a low level, and in this case, binary data such as 1 is written in the memory layer. On the contrary, when the reverse operation voltage is applied to the second metal layer of the memory cell, both ends of the memory layer are changed to the high resistance state again, and at this time, one end of the memory layer close to the second metal layer is displayed as a low level, and one end close to the first metal layer is displayed as a high level, in which case, another binary data such as "0" is written in the memory layer.
Further exemplary, assuming that one end of the memory layer near the second metal layer is presented as a high level, one end near the first metal layer is presented as a low level, binary data "1" is written in the memory layer, one end of the memory layer near the second metal layer is presented as a low level, one end near the first metal layer is presented as a high level, binary data "0" is written in the memory layer, if binary data "1" needs to be written to a memory cell located in the X-th row Y-th column Z-th layer of the memory array:
in an alternative embodiment, with continued reference to fig. 6B, a write operation may be performed through row word lines RWL and column select lines CSL formed of m×n first FETs: first, since the memory cell is located in the Z-th layer, it is necessary to activate the second metal layer of the Z-th layer but not activate other second metal layers than the second metal layer of the Z-th layer, in which case the address line AL led out to the second metal layer of the Z-th layer through the peripheral control circuit Z Applying a first write voltage V corresponding to the written binary data "1 write1 And divide the address line AL Z Other than address lines AL 1 ～AL Z-1 And AL Z+1 ～AL P Suspending (i.e. neither high nor low); second, at address line AL Z Applying a write voltage V write1 In the case where the right side of the diagram of all the memory layers on the Z-th layer corresponds to a high level, and the left side of the diagram of the memory layers on the X-th row and Y-th column corresponds to a low level, and the left side of the diagram of the memory layers other than the memory layers on the X-th row and Y-th column corresponds to a high level, in order to turn on the memory layers on the X-th row and Y-th column, it is necessary to make the left side of the diagram of the memory layers on the X-th row and Y-th column correspond to a low level, in which case the column selection line CSL can be connected to the peripheral control circuit Y Grounded, and a column select line CSL Y Column select lines CSL other than 1 ～CSL Y-1 CSL Y+1 ～CSL N Upper apply and address line AL Z The same first write voltage V write1 Or hang in the air; furthermore, to make the column select line CSL Y The low level of ground can be synchronized to the left side of the diagram of the memory layer on the X-th row and Y-th column, alsoTo turn on FETXY and turn off other FETXY other than FETXY, the column word line RWL may be turned on by a peripheral control circuit X Applying a turn-on voltage to turn on FETXY to the divided word line RWL X Other row word lines RWL than 1 ～RWL X-1 RWL (RWL) X+1 ～RWL M Applying a cut-off voltage or suspending; thus, address line AL Z First write voltage V on write1 Writing binary data "1" to the memory cells of the X-th row, Y-th column, and Z-th layer may be completed. When the first FET is NMOS, the on voltage is a voltage corresponding to a high level 1, the off voltage is a voltage corresponding to a low level 0, and when the first FET is PMOS, the on voltage is a voltage corresponding to a low level 0, and the off voltage is a voltage corresponding to a high level 1.
In another alternative embodiment, with continued reference to fig. 6B, the write operation may be performed through row select lines RSL and column word lines CWL formed by m×n second FETs: first, since the memory cell is located in the Z-th layer, the address line AL can be led out to the second metal layer of the Z-th layer through the peripheral control circuit Z Applying a first write voltage V corresponding to the written binary data "1 write1 And divide the address line AL Z Other than address lines AL 1 ～AL Z-1 And AL Z+1 ～AL P Suspending; second, at address line AL Z Applying a first write voltage V write1 In the case where the right side of the diagram of all the memory layers on the Z-th layer corresponds to a high level, and the left side of the diagram of the memory layers on the X-th row and Y-th column corresponds to a low level, and the left side of the diagram of the memory layers other than the memory layers on the X-th row and Y-th column corresponds to a high level, in order to turn on the memory layers on the X-th row and Y-th column, it is necessary to make the left side of the diagram of the memory layers on the X-th row and Y-th column correspond to a low level, in which case the row selection line RSL can be connected by the peripheral control circuit X Grounded, divided by row select line RSL X Other row select lines RSL than 1 ～RSL X-1 RSL (RSL) X+1 ～RSL M Upper apply and address line AL Z Identical first writeVoltage V write1 Or hang in the air; thereafter, the row select line RSL is to be made X The low level of ground can be synchronized to the left side of the diagram of the memory layer on the X-th row and Y-th column, and it is also necessary to turn on FETXY and turn off other FETXY than FETXY, in which case the column word line CWL can be turned on by peripheral control circuitry Y Applying a turn-on voltage to turn on FETXY to the divided column word line CWL Y Other than column word lines CWL 1 ～CWL Y-1 CWL Y+1 ～CWL N Applying a cut-off voltage or suspending, at this time, the address line AL Z First write voltage V on write1 Writing binary data "1" into the memory cells of the X-th row, Y-th column and Z-th layer can be completed.
In still another alternative embodiment, as shown in fig. 6B, in the same control manner as the row word line RWL and the column selection line CSL formed by the m×n first FETs write binary data "1" to the memory cells in the Z-th layer of the X-th row and the Y-th column of the memory array, the memory array may be transposed written by the row selection line RSL and the column word line CWL formed by the m×n second FETs, that is, the same control operation actually writes binary data "1" to the memory cells in the X-th layer of the Y-th row and the X-th column of the memory array, specifically: first, an address line AL led out to a second metal layer of a Z-th layer through a peripheral control circuit Z Applying a first write voltage V corresponding to the written binary data "1 write1 And divide the address line AL Z Other than address lines AL 1 ～AL Z-1 And AL Z+1 ～AL P After suspending, the right side of the diagram of all the storage layers of the Z layer is made to be high level; next, the row select line RSL is connected to the peripheral control circuit Y Grounded, divided by row select line RSL Y Other row select lines RSL than 1 ～RSL Y-1 RSL (RSL) Y+1 ～RSL N Upper apply and address line AL Z The same first write voltage V write1 Or after suspending, the third electrode of FET on Y line is made to be low-electricLeveling; thereafter, the word line CWL is aligned by a peripheral control circuit X Applying a turn-on voltage to the column-divided word line CWL X Other than column word lines CWL 1 ～CWL X-1 CWL X+1 ～CWL M After applying the cut-off voltage or suspending, the FET on the X column of the Y row is turned on, at this time, the low level at the third electrode of the FET on the X column of the Y row is synchronized to one end of the left side of the diagram of the memory layer of the X column of the Y row, and then passes through the address line AL Z First write voltage V on write1 Binary data "1" may be written to memory cells of the Z-th layer of the Y-th row and the X-th column.
Conversely, if it is desired to write a binary data "0" to a memory cell located in the Z-th layer of the X-th row, Y-th column of the memory array:
in an alternative embodiment, with continued reference to fig. 6B, a write operation may be performed through row word lines RWL and column select lines CSL formed of m×n first FETs: first, since the memory cell is located in the Z-th layer, it is necessary to activate the first metal layer of the Z-th layer but not activate other first metal layers except the first metal layer of the Z-th layer, in which case the address line AL led out from the second metal layer of the Z-th layer can be controlled by the peripheral control circuit Z Grounded except for address line AL Z Other than address lines AL 1 ～AL Z-1 And AL Z+1 ～AL P Suspending; second, at address line AL Z In the case of grounding, the left side of the diagram of all the memory layers on the Z-th layer is low, and in order to turn on the memory layers on the Z-th layer of the X-th row and Y-th column, it is necessary to make the left side of the diagram of the memory layers on the X-th row and Y-th column high, and the left sides of the diagrams of the other memory layers except the memory layers on the X-th row and Y-th column low, in which case the column selection line CSL may be set to be low by the peripheral control circuit Y Applying a second write voltage V corresponding to the written binary data "0 write2 And divide the column selection line CSL Y Column select lines CSL other than 1 ～CSL Y-1 CSL Y+1 ～CSL N Grounding or suspending; furthermore, to make the column select line CSL Y The high level applied thereto can be synchronized to the left side of the diagram of the memory layer on the X-th row and Y-th column, and it is also necessary to turn on FETXY and turn off other FETXY than FETXY, in which case the row word line RWL can be turned on by the peripheral control circuit X Applying a turn-on voltage to turn on FETXY to the divided word line RWL X Other row word lines RWL than 1 ～RWL X-1 RWL (RWL) X+1 ～RWL M Applying a cut-off voltage or suspending; thus, column select line CSL Y Second write voltage V on write2 Writing binary data "0" to the memory cells of the X-th row, Y-th column, and Z-th layer may be completed.
In the above embodiments, it should be noted that the description is merely given of how to write binary data "0" to the memory cells of the Z-th layer of the X-th row and Y-th columns through the row word lines RWL and the column selection lines CSL formed by the m×n first FETs, and in other alternative embodiments, binary data "0" may be written to the memory cells of the Z-th layer of the X-th row and Y-th column through the row selection lines RSL and the column word lines CWL formed by the m×n second FETs, or binary data "0" may be written to the memory cells of the Z-th layer of the X-th row and Y-th columns of the memory array through the row word lines RSL and the column word lines CWL formed by the m×n first FETs, or the binary data "1" may be written to the memory cells of the X-th row and Y-th column of the memory array by the row selection lines RSL and the column selection lines CSL formed by the m×n first FETs, which the binary data "0" 1 "is written to the memory cells of the X-th row and Y-th column of the memory array, which is not repeated.
Read operation
Each memory cell in the memory array is typically also coupled to a Sense Amplifier (SA), which may be located in the controller 120 illustrated in fig. 1, for example, and binary data stored in any memory cell may be read by sensing a voltage change or a current change across the memory cell by the SA. For example, if it is desired to read binary data stored in a memory cell located in the Z-th layer of the X-th row, Y-th column of the memory array:
In an alternative embodiment, with continued reference to fig. 6B, a read operation may be performed through row word lines RWL and column select lines CSL formed of m×n first FETs: first, since data in the memory cells of the Xth row, the Y th column and the Z th layer are to be read, FETXY of the Xth row, the Y th column is required to be turned on, and FETs other than FETXY of the Xth row, the Y th column are turned off, and at this time, the data can be transferred to the row word line RWL through the peripheral control circuit X Applying a turn-on voltage to the column-divided word line RWL X Other row word lines RWL than 1 ～RWL x-1 RWL (RWL) x+1 ～RWL M Applying a cutoff voltage; next, the data in the memory cells of the X-th row, Y-th column and Z-th layer are read, that is, the voltage difference exists on both sides of the memory cells of the X-th row, Y-th column and Z-th layer, and the voltage difference does not exist on both sides of the memory cells of other memory cells, so that the column selection line CSL can be controlled by the peripheral control circuit Y Grounded, control column select line CSL Y All other column select lines except for the one that is floating, and address line AL located at the Z-th layer Z Applying a read voltage V read At this time, the read voltage V read If the binary data 1 is stored in the memory cell, the memory cell is in a low-resistance state, so that the current at two ends of the memory cell exceeds a current threshold in the reading process, and the binary data 1 is stored in the memory cell after the large current at two ends of the memory cell is read through SA; otherwise, if the binary data "0" is stored in the memory cell, the memory layer in the memory cell is in a high-resistance state, so that the current at two ends of the memory layer in the reading process does not exceed the current threshold, and the binary data "0" is stored in the memory cell after the small current at two ends of the memory layer is read through SA.
It should be noted that the above description is only illustrative of one possible reading mode, and the present application is trueOther reading schemes may also be employed in embodiments. For example, in another example, with continued reference to FIG. 6B, the row word line RWL may also be accessed through peripheral control circuitry X Applying a turn-on voltage to the other row word lines RWL 1 ～RWL x-1 RWL (RWL) x+1 ～RWL M Applying an off voltage, at which time all FETs located on row X are turned on; second, to make the voltage difference between the two sides of the memory cell of the X-th row, Y-th column and Z-th layer and the voltage difference between the two sides of the memory cell of other memory cells are not present, the column selection line CSL can be selected by the peripheral control circuit Y Applying a read voltage V read Control other column select lines to ground or float, and control address line AL of the Z-th layer Z The grounding is carried out, so that only the two sides of the storage layer of the storage unit of the X row, the Y column and the Z layer have voltage differences, and the two sides of the storage layer of other storage units do not have voltage differences; therefore, if a large current exists across the memory layer through the SA reading, it can be known that binary data "1" is stored in the memory cell, whereas if a small current exists across the memory layer through the SA reading, it can be known that binary data "0" is stored in the memory cell. Alternatively, in yet another example, the column word line RWL may be first accessed by a peripheral control circuit X Applying a turn-on voltage to the other row word lines RWL 1 ～RWL x-1 RWL (RWL) x+1 ～RWL M Applying a cut-off voltage to turn on all FETs located on the X-th row and then to column select line CSL via peripheral control circuit Y Precharging to a predetermined charging voltage V readprech And address lines AL to other column select lines and Z-th layer Z Applying a read voltage V read Thus, only the two sides of the storage layer of the storage unit of the X row, the Y column and the Z layer have voltage differences, and the two sides of the storage layer of other storage units do not have voltage differences; therefore, if a large current exists at both ends of the memory layer through SA reading, it can be known that binary data "1" is stored in the memory cell, whereas if a small current exists at both ends of the memory layer through SA reading, it can be known that binary data is stored in the memory cellData "0" is made. It should be understood that there are many possible reading ways, and this embodiment of the present application will not be repeated here.
Illustratively, the following description will proceed with the reading mode in the first example described above, and other possible reading modes will be described.
In another alternative embodiment, with continued reference to fig. 6B, a read operation may be performed through row select lines RSL and column word lines CWL formed by m×n second FETs: can be arranged to a word line CWL by a peripheral control circuit Y Applying a turn-on voltage and controlling a row select line RSL X Grounding to turn on the FETXY of the X row and Y column; thereafter, the peripheral control circuit can supply the address line AL at the Z-th layer Z Applying a read voltage V read At this time, if binary data "1" is stored in the memory cell, the address line AL Z A first write voltage V applied originally write1 The current at two ends of the storage layer exceeds a certain current threshold value, and then after the large current at two ends of the storage layer is read through SA, the binary data 1 is stored in the storage unit; conversely, if the binary data "0" is stored in the memory cell, AL Z The current at two ends of the storage layer does not exceed the current threshold value in the reading process, and thus, after the small current at two ends of the storage layer is read through SA, the binary data "0" stored in the storage unit can be obtained.
In still another alternative embodiment, as shown in fig. 6B, in the same control manner as the row word line RWL and the column selection line CSL formed by the mxn first FETs are controlled to read the binary data stored in the memory cells of the Z-th layer of the X-th row and the Y-th column of the memory array, the memory array may also be transposed read through the row selection line RSL and the column word line CWL formed by the mxn second FETs, that is, the same control operation actually reads the binary data stored in the memory cells of the Z-th layer of the Y-th row and the X-th column of the memory array, specifically implemented as follows: first, the column word line CWL is formed by peripheral control circuit X Applying a turn-on voltage and controlling a row select line RSL Y After being groundedSo that FETs located in the Y-th row and X-th column XY Is turned on; then, the peripheral control circuit is used for leading the address line AL positioned at the Z-th layer Z Applying a read voltage V read Then, if the current read by SA at two ends of the storage layer exceeds a certain current threshold value, the storage unit positioned at the X-th layer of the Y-th row and the X-th column can be informed of storing binary data '1'; otherwise, if the current read by the SA at the two ends of the storage layer does not exceed a certain current threshold value, it is known that binary data "0" is stored in the storage unit positioned in the Z layer of the X column of the Y row.
In one embodiment, two sets of FETs are disposed at two ends of the first metal layer, so that the two sets of FETs form two sets of word lines and select lines in quadrature, and further, the transposed read-write operation of the memory array can be implemented through the two sets of word lines and select lines in quadrature, and the transposed read-write operation belongs to the memory array which is used frequently, so that the memory array is particularly suitable for memory occasions requiring the implementation of the internal operation, such as memory arrays in convolutional neural networks (convolutional neural network, CNN), recurrent neural networks (rerrent neural network, RNN), deep neural networks (deep neural networks, DNN) or memory-enhanced neural networks (memory-augmented neural network, man) and modified variants thereof.
Concretely realize two
In an alternative implementation, fig. 8A schematically illustrates a schematic perspective view of still another storage array provided in the embodiment of the present application, fig. 8B schematically illustrates two possible cross-sectional front views of the storage array, and fig. 8C schematically illustrates a cross-sectional top view of the storage array, where the cross-sectional front view illustrated in fig. 8B is along the plane L illustrated in fig. 8C 32 The cross-sectional top view of FIG. 8C is taken along plane L shown in FIG. 8B 31 And cutting the memory array. Referring to fig. 8A to 8C, it is shown that:
referring to FIG. 8B, the memory array includes, in addition to the insulating layer, the second metal layer, the memory layer, and the first metal layer described aboveThe metal layers are arranged in the stacking direction V 1 As shown in the first diagram of FIG. 8B, is disposed at each of the first metal layers in the stacking direction V 1 Or disposed at each first metal layer in the stacking direction V as in the second diagram of fig. 8B 1 Is shown for the lower FET. And, since each second metal layer and each insulating layer of the memory array contains corresponding MxN holes, the first metal layer is disposed in the corresponding holes, and the memory array is stacked in the stacking direction V 1 And will include M x N FETs, respectively. The FET may be of the MOSFET or CAAFET type. For example, in one example, the FET may be CAAFET when the FET is disposed at the upper end of the diagram as illustrated in the first diagram of fig. 8B, and CAAFET or MOSFET when the FET is disposed at the lower end of the diagram as illustrated in the second diagram of fig. 8B;
further, referring to fig. 8A and 8C, a second metal layer including a P (P is a positive integer) layer is assumed in the stacked structure, and V is illustrated 2 The direction is the row direction, diagram V 3 The direction is the column direction, there is at least one target second metal layer in the P-layer second metal layers, and at least two adjacent rows of second holes of each of the at least one target second metal layer may be separated by a non-conductive material, and may be, for example, separated by a non-conductive material between each two adjacent rows of second holes as illustrated in fig. 8A and 8C, so that each target second metal layer is divided into M second metal strips. The non-conductive material may be, for example, plastic, rubber, glass, ceramic, or the like. The memory array illustrated in fig. 8A to 8C may be implemented by cutting a cutting region between every two adjacent rows of the second holes of each target second metal layer through a metal cutting process on the basis of the memory array illustrated in fig. 4A, and filling the non-conductive material in the cutting region.
In another alternative implementation, fig. 9A schematically illustrates a schematic perspective view of still another storage array provided in an embodiment of the present application, and fig. 9B schematically illustrates the storage arrayFIG. 9C schematically illustrates a cross-sectional top view of the memory array, wherein the cross-sectional front view shown in FIG. 9B is along the plane L illustrated in FIG. 9C 42 The cross-sectional top view of FIG. 9C is taken along plane L shown in FIG. 9B 41 And cutting the memory array. Referring to fig. 9A to 9C, it is shown that:
referring to FIG. 9B, the memory array includes, in addition to the insulating layer, the second metal layer, the memory layer, and the first metal layers described above, a layer of a semiconductor material disposed on each of the first metal layers in the stacking direction V 1 As shown in the first diagram of FIG. 9B, is disposed at each of the first metal layers in the stacking direction V 1 Or a FET disposed at the illustrated lower end of each first metal layer in the stacking direction V1 as in the second diagram of fig. 9B;
further, referring to fig. 9A and 9C, a second metal layer including a P (P is a positive integer) layer is assumed in the stacked structure, and V is illustrated 2 The direction is the row direction, diagram V 3 The direction is a column direction, there is at least one target second metal layer in the P-layer second metal layers, and at least two columns of adjacent second holes of each of the at least one target second metal layer may be separated by a non-conductive material, and may be, for example, separated by a non-conductive material between every two columns of adjacent second holes as illustrated in fig. 9A and 9C, so that each target second metal layer is divided into N second metal strips.
It should be appreciated that in embodiments two, any target second metal layer may be separated by a non-conductive material only between a portion of two rows of adjacent second holes or a portion of two columns of adjacent second holes, such that one target second metal layer may be divided into second metal strips of greater than or equal to 2 but less than or equal to N-1 columns, or greater than or equal to 2 but less than or equal to M-1 rows, or may be separated by a non-conductive material between every two rows of adjacent second holes or every two columns of adjacent second holes, such that one target second metal layer may be divided into second metal strips of N columns, or second metal strips of M rows, as this embodiment of the application is not specifically limited.
Further, taking the memory array illustrated in fig. 8A to 8C as an example, it is assumed that each second metal layer is divided into M rows of second metal strips, and m×n first metal layers are stacked in the stacking direction V 1 If there are m×n FETs, i.e., FET11, FET12, … …, FET1N, FET, FET22, … …, FET2N, … …, FET1, FET2, … …, FET mn, at the lower end of the diagram, fig. 10 illustrates an equivalent circuit block diagram of the memory array, and as shown in fig. 10, each row of second metal strips separated by a non-conductive material may lead out one address line AL of the memory array for selecting all memory cells located on the corresponding row of second metal strips. For example, starting from the upper side of the figure, the first layer is along V 2 M rows of second metal strips in the direction sequentially lead out address lines AL 1,1 Address line AL 1,2 … … and address lines AL 1,M Along V on the second layer 2 M rows of second metal strips in the direction sequentially lead out address lines AL 1,2 Address line AL 2,2 … … and address lines AL 2,M … …, layer P along V 2 M rows of second metal strips in the direction sequentially lead out address lines AL P,1 Address line AL P,2 … … and address lines AL P,M . And, referring to fig. 10, each FET includes a first electrode (i.e., electrode "1" illustrated in fig. 10), a second electrode (i.e., electrode "2" illustrated in fig. 10), which is the gate of the FET, the first electrode being the source of the FET, the third electrode being the drain of the FET, or the second electrode being the gate of the FET, the first electrode being the drain of the FET, and a third electrode (i.e., electrode "3" illustrated in fig. 10), wherein:
The first electrode of each FET is connected with the lower end of the corresponding first metal layer, the second electrodes of N FETs on each row are connected to form a row word line RWL of the memory array, the third electrodes of M FETs on each column are connected to form a column selection line CSL of the memory array, and the row word line RWL is used for conductingThe column select line CSL is used to select all FETs on the corresponding column. For example, the second electrodes of the FETs 11, 12, … …, 1N in the first row are connected from the left side of the figure to form a row word line RWL 1 Through row word line RWL 1 The FETs 11 to 1N in the first row are turned on, and the second electrodes of the FETs 21, 22, … … and 2N in the second row are connected to form a row word line RWL 2 Through row word line RWL 2 FETs 21 to 2N, … … on the second row are turned on, and second electrodes of FETM1, FETM2, … … and FETMN on the M-th row are connected to form a row word line RWL M Through row word line RWL M FETM1 to FETMN on the M th row can be turned on, and the FETs 11, 21, … … and FETM1 on the first column from the front side are connected to form a column selection line CSL 1 Through column select line CSL 1 The FETs 11 to FETM1 on the first column are turned on, and the FETs 12, 22, … … and FETM2 on the second column are connected to form a column selection line CSL 2 Through column select line CSL 2 The FETs 12 to FETM2, … … on the second column are turned on, and the FETs 1N, FET N, … … and FETMN on the N column are connected to form a column selection line CSL N Through column select line CSL N FETs 1N to FETMN located on the N-th column can be turned on. It should be understood that, in other examples, the third electrodes of the N FETs in each row may be connected to form a row selection line RSL of the memory array, and the second electrodes of the M FETs in each column may be connected to form a column word line CWL of the memory array, which is not limited in particular.
Further, in the memory array, each row word line RWL, each column select line CSL, and each address line AL are connected to a peripheral control circuit, which is illustratively located in the controller 120 illustrated in fig. 1. Any one of the first metal layers in the memory array, any one of the memory layers surrounding the first metal layer and the second metal layer surrounding the memory layer form a memory unit of the memory array, and the read-write operation of the memory unit is realized by controlling each connected control line through a peripheral control circuit so as to change the voltage difference at two ends of the memory layer contained in the memory unit. For ease of understanding, the following description exemplarily describes the read and write operations of any memory cell in the memory array in detail:
Write operation
Assuming that one end of the storage layer close to the second metal layer is at a high level, and one end close to the first metal layer is at a low level, binary data "1" is written in the storage layer, one end of the storage layer close to the second metal layer is at a low level, and one end close to the first metal layer is at a high level, binary data "0" is written in the storage layer, then:
when it is necessary to write binary data "1" to a memory cell located at the X-th row, Y-th column, and Z-th layer of the memory array, as shown with continued reference to fig. 10, a write operation can be performed through row word lines RWL and column select lines CSL constituted by m×n FETs: first, since the memory cell is located in the Z-th layer of the Y-th column, it is necessary to activate the second metal bar of the Z-th layer of the Y-th column but not activate other second metal bars than the second metal bar of the Z-th layer of the Y-th column, in which case the address line AL led out to the second metal bar of the Z-th layer of the Y-th column by the peripheral control circuit Z,Y Applying a first write voltage V corresponding to the written binary data "1 write1 And divide the address line AL Z,Y The other address lines are grounded or suspended; second, at address line AL Z,Y Applying a first write voltage V write1 In the case where the right side of the diagram of all the memory layers on the Z-th layer of the Y-th column corresponds to a high level, and when the memory layers on the Z-th layer of the X-th row and the Y-th column are to be turned on, it is necessary to make the left side of the diagram of the memory layers on the X-th row and the Y-th column correspond to a low level and the left sides of the diagrams of the memory layers other than the memory layers on the X-th row and the Y-th column correspond to a high level, in this case, the column selection line CSL may be set by the peripheral control circuit Y Grounded, and a column select line CSL Y Column select lines CSL other than 1 ～CSL Y-1 CSL Y+1 ～CSL N Upper apply and address line AL Z,Y The same first write voltage V write1 Or hang in the air; thereafter, the column select line CSL is to be made Y The low level of ground can be synchronized to the left side of the diagram of the memory layer on the Xth row, Y column and Z layer, and it is also necessary to turn on FETXY and turn off the FETXY other than FETXY, in which case the row word line RWL can be turned on by the peripheral control circuit X Applying a turn-on voltage to turn on FETXY to the divided word line RWL X Other row word lines RWL than 1 ～RWL X-1 RWL (RWL) X+1 ～RWL M Applying a cut-off voltage or suspending, at this time, the address line AL Z,Y First write voltage V on write1 Writing binary data "1" into the memory cells of the X-th row, Y-th column and Z-th layer can be completed.
Conversely, when it is necessary to write binary data "0" to a memory cell located in the xth row, yth column, and Z layer of the memory array, with continued reference to fig. 10, a write operation can be performed through row word lines RWL and column select lines CSL formed of mxn FETs: first, since the memory cell is located at the Z-th layer of the Y-th column, it is necessary to activate the second metal bar of the Z-th layer of the Y-th column but not activate other second metal bars except the second metal bar of the Z-th layer of the Y-th column, in which case the address line AL led out by the second metal bar of the Z-th layer of the Y-th column can be controlled by the peripheral control circuit Z,Y Grounded except for address line AL Z,Y Applying a second write voltage V corresponding to the binary data "0" to other address lines write2 Or hang in the air; second, at address line AL Z,Y In the case of grounding, the right side of the diagram of all the memory layers on the Y-th column and the Z-th column corresponds to a low level, and when the memory layers on the X-th row and the Y-th column are turned on, it is necessary to make the left side of the diagram of the memory layers on the X-th row and the Y-th column correspond to a high level, and the left sides of the diagrams of the other memory layers except the memory layers on the X-th row and the Y-th column correspond to a low level, in which case the column selection line CSL can be turned on by the peripheral control circuit Y Applying a second write voltage V corresponding to the written binary data "0 write2 And divide the column selection line CSL Y Other than column selectionLine selection CSL 1 ～CSL Y-1 CSL Y+1 ～CSL N Grounding or suspending; furthermore, to make the column select line CSL Y The high level applied thereto can be synchronized to the left side of the diagram of the memory layer on the X-th row and Y-th column, and it is also necessary to turn on FETXY and turn off other FETXY than FETXY, in which case the row word line RWL can be turned on by the peripheral control circuit X Applying a turn-on voltage to turn on FETXY to the divided word line RWL X Other row word lines RWL than 1 ～RWL X-1 RWL (RWL) X+1 ～RWL M Applying a cut-off voltage or suspending; thus, column select line CSL Y Second write voltage V on write2 Writing binary data "0" to the memory cells of the X-th row, Y-th column, and Z-th layer may be completed.
Read operation
In an alternative embodiment, binary data stored in a certain memory cell in the memory array may be read through a row word line RWL and a column select line CSL formed of mxn FETs. Each memory cell in the memory array is typically further connected to an SA, which may be located, for example, in the controller 120 illustrated in fig. 1, and binary data stored in any memory cell may be read by sensing a voltage change or a current change on the memory cell by the SA. For example, when binary data stored in a memory cell located in the Z-th layer of the X-th row, Y-th column of the memory array needs to be read:
in one example, with continued reference to FIG. 10, first, since data in the memory cells of the Xth row, the Y column, and the Z layer are to be read, FETXY of the Xth row, the Y column is required to be turned on, i.e., to the row word line RWL through the peripheral control circuit X Apply the turn-on voltage to the divided word line RWL X Applying a cut-off voltage to the word lines of other rows to turn on all FETXY on the X-th row; second, the voltage difference exists between the two ends of the memory cell of the X-th row, Y-th column and Z-th layer, and the voltage difference does not exist between the two ends of the memory cell of other memory cells, so that the column selection line C can be controlled by the peripheral control circuit SL Y Grounded, to a column-dividing selection line CSL Y Column select lines other than and address lines AL at the Z-th layer of the Y-th column Z,Y Applying a read voltage V read The method comprises the steps of carrying out a first treatment on the surface of the At this time, only the memory layers on both sides of the memory cells on the X-th row and the Y-th column have a voltage difference, so if the memory cells store binary data "1", which means that the memory layers are in a low-resistance state, the current at both ends of the memory layers will exceed a certain current threshold in the reading process, and thus, after the large current at both ends of the memory layers is read through the SA, it can be known that the memory cells store binary data "1"; on the contrary, if the binary data "0" is stored in the memory cell, which means that the memory layer is in a high resistance state, the current at two ends of the memory layer does not exceed the current threshold in the reading process, so that the binary data "0" is stored in the memory cell after the small current at two ends of the memory layer is read through the SA.
In another example, with continued reference to FIG. 10, first, a row word line RWL may be provided with peripheral control circuitry X Apply the turn-on voltage to the divided word line RWL X The other row word lines except for the one apply the off voltage, at which time all FETs on the X-th row are turned on; second, the column selection line CSL can be connected through the peripheral control circuit Y Precharging to reach the preset reading voltage V readprech At this time, the on FET located in the X-th row and Y-th column will select the column select line CSL Y Preset read voltage V readprech Synchronizing to the first metal layer located in the X row and Y column; furthermore, the address line AL on the Z layer of the Y column can be controlled by the peripheral control circuit Z,Y Applying a read voltage V read And divide the address line AL Z,Y Other address lines AL on the other Y-th column 1,Y ～AL Z-1,Y And AL z+1,Y ～AL P,Y Also precharged to a preset read voltage V readprech At this time, only the voltage difference exists between the two ends of the memory layer of the memory cell of the X row, Y column and Z layer, if the binary data "1" is stored in the memory cell, the memory cell storesThe layer is in a low resistance state, and the read current or voltage is large, so that the CSL sensed by SA Y The larger voltage or current variation can know that binary data 1 is stored in the memory cell; conversely, if the binary data "0" is stored in the memory cell, the memory layer of the memory cell is in a high resistance state, and the read current or voltage is effective, so that the CSL sensed by SA Y A small voltage or current change in the memory cell will know that binary data "0" is stored in the memory cell. It should be understood that other reading methods are also possible, and the embodiments of the present application are not listed here.
In another alternative embodiment, the sum of binary data stored in at least two memory cells in the memory array may be read through row word lines RWL and column select lines CSL formed by m×n FETs, that is, the memory array may further implement in-memory calculation of the stored data and output. With continued reference to fig. 10, each column select line CSL is typically further connected to an analog-to-digital converter (ADC), which may be illustratively located in the controller 120 illustrated in fig. 1, and the sum of the binary data stored by the at least two memory cells may be read by sensing a voltage change or a current change on the column select line CSL on which the at least two memory cells are located by the ADC. For example:
in one example, with continued reference to FIG. 10, when the sum of binary data stored in all memory cells located on the Y-th column of the memory array needs to be read: first, all row word lines RWL can be accessed by peripheral control circuits 1 Row word line RWL M Applying an on voltage, at which time all FETs are turned on; second, the column selection line CSL can be connected through the peripheral control circuit Y Precharging the column select line CSL Y The voltage reaches the preset reading voltage V readprech At this time, the on FET in the Y-th column will select the column select line CSL Y Preset read voltage V readprech Synchronizing to the M first metal layers located in the Y-th column; furthermore, the Y-th row can be controlled by the peripheral control circuitAll address lines AL on I,Y (I fetch pass [1, N)]All integers of (a) to apply a read voltage V read At the same time divide address line AL I,Y The other address lines on the other Y-th column are also precharged to a predetermined read voltage V readprech The method comprises the steps of carrying out a first treatment on the surface of the Thereafter, the column selection line CSL is connected Y Through sense column select line CSL Y The magnitude of the current on (e.g., by sensing the column select line CSL Y The current change slope of (c) is used to know how many memory cells in all memory cells on the Y-th column store binary data "1", thus completing the addition of the binary data stored in all memory cells on the Y-th column.
In another example, and with continued reference to FIG. 10, when it is desired to read the X on the Y-th column of the memory array 1 Line Z 1 Layer and X 2 Line Z 2 The sum of binary data stored in two memory cells of a layer: first, the row word line RWL can be connected to the peripheral control circuit X1 And row word line RWL X2 Applying a turn-on voltage at the X-th position 1 Line and X 2 The FETs on the row are turned on; second, the column selection line CSL can be connected through the peripheral control circuit Y Precharging the column select line CSL Y The voltage reaches the preset reading voltage V readprech At this time, at the X-th 1 The on FET of row Y column will select the column select line CSL Y Preset read voltage V readprech Synchronous to be positioned at X 1 A first metal layer on the Y-th row and on the X-th column 2 The on FET of row Y column will select the column select line CSL Y Preset read voltage V readprech Synchronous to be positioned at X 2 A first metal layer of row Y; furthermore, the Y-th column and Z-th column can be controlled by the peripheral control circuit 1 Address line AL of layer Z1,Y And column Y, Z 2 Address line AL of layer Z2,Y Applying a read voltage V read At the same time will addressLine AL Z1,Y And address line AL Z2,Y Other address lines on the other Y-th column are also precharged to a predetermined read voltage V readprech The method comprises the steps of carrying out a first treatment on the surface of the Thereafter, the column selection line CSL is connected Y Through sense column select line CSL Y The magnitude of the current on (e.g., by sensing the column select line CSL Y Current change slope of (c) on the Y-th column 1 Line Z 1 Layer and X 2 Line Z 2 The binary data "1" is stored in some of the two memory cells of the layer, and thus the addition of the binary data stored in some memory cells on the Y-th column is completed.
In yet another example, with continued reference to FIG. 10, when the sum of the binary data stored in all of the memory cells located on row X of the memory array needs to be read: first, the row word line RWL can be connected to the peripheral control circuit X Applying a turn-on voltage to the column-divided word line RWL X The other row word lines except for the one apply the off voltage, at which time all FETs on the X-th row are turned on; second, the column select lines CSL can be all selected by the peripheral control circuit 1 ～CSL N Precharging the column select line CSL 1 ～CSL N The voltage reaches the preset reading voltage V readprech At this time, the turned-on FETs located on the first column to the N column of the X row will select the column select line CSL 1 ～CSL N Preset read voltage V readprech Synchronizing to the N first metal layers located in the X row, the first column and the N column; furthermore, the read voltage V can be applied to all address lines by the peripheral control circuit read The method comprises the steps of carrying out a first treatment on the surface of the Thereafter, the column selection line CSL is connected 1 ～CSL N Through sense column select line CSL 1 ～CSL N The magnitude of the current on (e.g., by sensing the column select line CSL 1 ～CSL N The sum of the current change slopes of (a) to know how many memory cells of all memory cells located on the X-th row store binary dataData "1", thus completing the addition operation of the binary data stored in all the memory cells on the X-th row.
In yet another example, and with continued reference to FIG. 10, when a read of a Y-th row of the memory array is desired 1 Line Z 1 Layer and Y 2 Line Z 2 The sum of binary data stored in two memory cells of a layer: first, the row word line RWL can be connected to the peripheral control circuit X Applying a turn-on voltage to the column-divided word line RWL X The other row word lines except for the one apply the off voltage, and at this time, the FETs on the X-th row are turned on; second, the column selection line CSL can be connected through the peripheral control circuit Y1 And column select line CSL Y2 Precharging the column select line CSL Y1 And column select line CSL Y2 The voltage reaches the preset reading voltage V readprech At this time, at the X-th row and Y-th 1 The column-on FET will select the column select line CSL Y1 Preset read voltage V readprech Synchronous to the X line and Y line 1 A first metal layer of the column on the X-th row and Y-th row 2 The column-on FET will select the column select line CSL Y2 Preset read voltage V readprech Synchronous to the X line and Y line 2 A first metal layer of the column; furthermore, the Y-th can be controlled by the peripheral control circuit 1 Column Z 1 Address line AL of layer Z1,Y1 And Y (th) 2 Column Z 2 Address line AL of layer Z2,Y2 Applying a read voltage V read At the same time divide address line AL Z1,Y1 And address line AL Z2,Y1 Other address lines than the one also being precharged to a predetermined read voltage V readprech The method comprises the steps of carrying out a first treatment on the surface of the Thereafter, the column selection line CSL is connected Y1 And column select line CSL Y2 Through sense column select line CSL Y1 And column select line CSL Y2 The magnitude of the current on (e.g., by sensing the column select line CSL Y1 And column select line CSL Y2 The sum of the current change slopes of (a) to learn the Y-th located on the X-th row) 1 Line Z 1 Layer and Y 2 Line Z 2 The binary data "1" is stored in some of the two memory cells of the layer, so that the addition of the binary data stored in some memory cells on the X-th row is completed.
It should be noted that, since the memory array in fig. 10 is a row word line of the memory array after connecting the second electrodes of the FETs of each row and a column selection line of the memory array after connecting the third electrodes of the FETs of each column, if a certain row and a certain column (e.g. the X-th 1 Line Y 1 Column) and another row and another column (e.g. X 2 Line Y 2 Column) is added, then the Y-th control is required 1 Column select line CSL on a column Y1 And Y (th) 2 Column select line CSL on a column Y2 Grounded at the same time to the X 1 Row word line RWL on row X1 And the X < th 2 Row word line RWL on row X2 Applying an on-voltage, in this case, the X-th 1 Line Y 1 Column, X 1 Line Y 2 Column, X 2 Line Y 1 Column and X 2 Line Y 2 The FETs of the column are all turned on, thus, via column select line CSL Y1 And column select line CSL Y2 The current sensed by the connected ADC is derived and actually the sum of the binary data stored in the four rows and columns of memory cells, rather than the X-th 1 Line Y 1 Column and X 2 Line Y 2 And the sum of binary data stored in the memory cells on the columns. It will be understood that the memory array illustrated in FIG. 10 can be implemented to sum binary data stored in all or part of memory cells in a row or column, or can be implemented to sum binary data stored in all or part of memory cells in an entire plane defined by a plurality of rows and columns, butAdding binary data stored in all or part of the layers of memory cells on a partial plane defined by a plurality of rows and columns cannot be achieved.
In the second embodiment, the second metal layer is divided into the plurality of second metal strips according to the row direction or the column direction, so that part of the memory cells on each second metal layer can be read and written through each second metal strip. Furthermore, the memory array structure in the second embodiment can also realize in-memory addition calculation of the memory array, that is, the controller can directly obtain the sum value of binary data stored by at least two memory units output by the memory array, without the need of subsequent addition calculation by the controller, so that the working pressure of the controller can be reduced. Also, since the in-memory add-and-sum operation pertains to more frequently used in-memory operations in a memory array, the memory array is particularly useful in memory applications requiring in-memory operations to be performed, such as may include, but not limited to, memory arrays in CNN, RNN, DNN or MANN and modified versions thereof.
It should be noted that the related examples in the foregoing embodiments one and two may also be combined with each other to obtain a modified storage array. For example, in another example, each column select line CSL illustrated in fig. 6B in one implementation may be further connected to an ADC, so that the current change on the column select line CSL is sensed by the ADC to obtain the sum of binary data stored in all or part of the memory cells in all planes defined by a certain row or a certain column or a plurality of rows and columns, so that the memory array in one implementation can also implement the inner addition calculation. For another example, a first FET may be disposed at the top of the figure of each first metal layer of the memory array embodying the second illustration, and a second FET may be disposed at the bottom of the figure, so that the memory array embodying the second illustration can also implement the transpose operation. For another example, the one or more second metal layers of the two illustrated memory arrays may be cut in the row direction and the column direction, so that each memory cell is separately laid out in an independent second metal block, and each second metal block is used as an address line of the memory array, so that the capacitive load in the read-write operation is further reduced and the speed of the read-write operation is further improved through the read-write operation of each address line on the corresponding memory cell.
Based on the memory array shown in the above embodiment, the present application further provides a method for manufacturing the memory array. Taking a three-dimensional memory array as an example, fig. 11 schematically illustrates a process of preparing a memory array according to an embodiment of the present application, as shown in fig. 11, where the preparation process includes:
step one, depositing an insulating layer to obtain a structure shown in (A) of FIG. 11;
step two, etching and forming M multiplied by N first holes on the insulating layer to obtain a structure shown in (B) in FIG. 11;
step three, depositing a first metal layer in each of the m×n first holes, resulting in a structure as shown in (C) of fig. 11;
step four, depositing a second metal layer above the insulating layer and the first metal layer to obtain a structure shown in (D) in FIG. 11;
step five, etching to form M multiplied by N second holes on the second metal layer to obtain a structure shown in (E) in FIG. 11;
step six, depositing a storage layer in each of the m×n second holes, resulting in a structure as shown in (F) of fig. 11;
step seven, depositing a first metal layer on the inner side of the storage layer to obtain a structure shown in (G) of FIG. 11;
step eight, repeating the stacking according to the steps one to seven to obtain a memory array as shown in (H) of fig. 11, where the memory array corresponds to the memory array illustrated in fig. 4A to 4C.
It should be noted that, in the memory array illustrated in fig. 4A to 4C described above, the first metal layer may be cylindrical, and the diameter of the cylinder may be uniform throughout the stacked structure of the insulating layer and the second metal layer. In order to ensure the consistency of the first metal layer, the present application may further predesign the material amount and the deposition speed of the storage layer deposited in the sixth step, so that the aperture of the second hole remaining on the first metal layer after the storage layer is deposited is consistent with the aperture of the first hole, and thus, even if the first metal layer is separately deposited in the first hole on the insulating layer and the second hole on the second metal layer in the third step and the seventh step, the diameters of the first metal layers in the two layers can be ensured to be consistent. In addition, in consideration of the influence of the process error, a certain deviation may exist between the diameter of the second metal layer on the insulating layer and the diameter of the second metal layer on the first metal layer in the actual memory array, but as long as the deviation is within the range of the influence of the process error, the deviation is within the protection scope of the embodiment of the present application, and the embodiment of the present application is not limited in particular.
In the preparation process, when each insulating layer or the second metal layer is deposited in the stacking direction, namely, holes are etched on the deposited insulating layer, compared with the mode of stacking a plurality of insulating layers and the second metal layer first and then etching the holes, the hole depth of each etched hole is enabled to depend on the height of the deposited insulating layer rather than the height of a plurality of layers, and the aperture of the hole is further reduced to be limited by etching capability, so that more memory units can be integrated in the memory array with the same size on the plane vertical to the stacking direction by reducing the aperture of the hole, and the memory density of the memory array is effectively improved.
Further illustratively, when it is desired to prepare the memory arrays illustrated in fig. 6A-6B in one of the above implementations, the following step nine may also be performed after the above step eight:
step nine, connecting one end of each first metal layer to the first FET, and connecting the other end of each first metal layer to the second FET, thereby obtaining the memory array as shown in fig. 6A to 6B.
In this example, by providing two sets of FETs at both ends of the first metal layer, the two sets of FETs can be made to constitute two sets of word lines and select lines orthogonal to each other, and thus transposed read/write operation of the memory array can be achieved.
Further illustratively, when it is desired to prepare the memory arrays illustrated in fig. 8A-8C of the second embodiment, the following step ten may also be performed after the fifth step and before the eighth step:
and step ten, forming a cutting area between at least two adjacent rows of second holes of the second metal layer through a metal cutting process, and filling the cutting area with a non-conductive material.
And, after the eighth step, executing the following step eleventh:
step eleven, connecting one end of each first metal layer to the FET to obtain the memory array as described above in fig. 8A to 8C.
Or,
when it is required to prepare the memory array illustrated in fig. 9A to 9C in the second embodiment, the following step twelve may be further performed after the fifth step and before the eighth step:
and twelve, forming a cutting area between at least two adjacent rows of second holes of the second metal layer through a metal cutting process, and filling the cutting area with a non-conductive material.
And performing the above step eleven after the above step eight, resulting in the memory array as in the above fig. 9A to 9C.
In the example, the second metal layer is divided into the plurality of second metal strips, so that part of memory cells on each second metal layer can be read and written through each second metal strip, further, the capacitance load in the read-write operation process can be reduced, and the read-write operation speed can be effectively improved.
In addition, the above related embodiments related to the memory array are also applicable to the preparation method, and the embodiments of the present application will not be repeated here.
The present application also provides a memory comprising a memory array as described above, and a controller coupled to the memory array, the controller being for reading and writing data in the memory array.
For ease of understanding, the memory array illustrated in FIG. 6A is described above as an exampleFig. 12 illustrates a specific structural schematic diagram of a memory provided in an embodiment of the present application, as shown in fig. 12, in this example, the controller may include: an encoding control unit (including the peripheral control circuit described in the above embodiment), an output buffer, a special function unit, a key register, a digital-to-analog converter (DAC), and an amplifier F which are provided in the column direction and are sequentially connected, a weight register, a DAC, and an amplifier F which are provided in the row direction and are sequentially connected, a sample/hold (S/H) circuit, an S/H circuit, a data selector (Mux) circuit, and an analog-to-digital converter (ADC) which are provided in the row direction and in the column direction, respectively, and a Write Word Line (WWL) and a write driver. Wherein the amplifier arranged in the column direction is connected with the column word line CWL of the memory array 0 ～CWL N One end of the S/H circuit arranged in the row direction is connected with a row selection line RSL of the memory array 0 ～RSL M Column word line CWL 0 ～CWL N And row select line RSL 0 ～RSL M For example, it may be arranged in the stacking direction V as illustrated in FIG. 6A 1 Is formed by a second FET at the lower end of the diagram. Accordingly, an amplifier arranged in the row direction is connected to the row word line RWL of the memory array 0 ～RWL M One end of the S/H circuit arranged in the column direction is connected with a column selection line CSL of the memory array 0 ～CSL N Row word line RWL 0 ～RWL M And column select line CSL 0 ～CSL N For example, it may be arranged in the stacking direction V as illustrated in FIG. 6A 1 Is formed by the first FET at the upper end of the figure. The other end of the S/H circuit arranged in the column direction and the other end of the S/H circuit arranged in the row direction are connected with the ADC through the Mux circuit, and then are connected with the input end of the output buffer, the output end of the output buffer is connected with the input end of the special functional unit, and the output end of the special functional unit is connected with the weight register. Wherein the special functional units include input registers, special processing elements (synergistic processing element, SPE), vector processing elements (vector processing elements)ng element, VPE) and an output register, wherein the output end of the input register is respectively connected with the input end of the SPE and the input end of the VPE, and the output end of the SPE and the output end of the VPE are respectively connected with the input end of the output register. In addition, the code control units are respectively connected with the column word lines CWL of the memory array 0 ～CWL N Row select line RSL 0 ～RSL M Row word line RWL 0 ～RWL M And column select line CSL 0 ～CSL N 。
In the working process of the memory, the encoding control unit receives a read-write request sent by an external device (such as the external device 200 illustrated in fig. 1), generates a corresponding control signal according to an operation type (such as a read type/write type) carried in the read-write request, and sends the control signal to a column word line CWL of the memory array 0 ～CWL N And row select line RSL 0 ～RSL M Or row word line RWL 0 ～RWL M And column select line CSL 0 ～CSL N To control the memory array to perform normal read and write operations, transposed read and write operations, or in-memory addition and computation operations for one or more memory cells. For the specific implementation procedure of this part of content, please refer to the description in the above implementation one or implementation two, and the detailed description is not repeated here. In one example, when performing a write operation, the encoding control unit may also send a drive signal to the write driver to activate the corresponding write word line WWL. In one example, when performing a read operation, the output data of the memory array may also be stored to an output buffer via the S/H circuit, mux circuit, and ADC, where the output buffer may store the output data of the memory array for a period of time, so as to speed up the read speed of subsequent reacquires. In one example, the output data stored in the output buffer may also be directly docked to a special functional unit, and after performing in-memory computation by the special functional unit through a low-memory-consumption kernel, the computed data is restored to the weight register or the key value register to continue the subsequent computation step.
It should be noted that fig. 12 is merely an exemplary possible structure of the memory, and in actual operation, the memory may further include more or fewer components than those shown in fig. 12, which is not specifically limited in the embodiment of the present application.
The application also provides a read-write control method, which comprises a controller, wherein the controller is used for realizing the method executed by the controller in the memory.
The application also provides an electronic device comprising a printed circuit board (printed circuit board, PCB) and a memory as described above, wherein the memory is provided on a surface of the PCB.
Illustratively, the electronic device includes, but is not limited to: smart phones, smart watches, tablet computers, VR devices, AR devices, in-vehicle devices, desktop computers, personal computers, handheld computers, or personal digital assistants.
While some of the possible embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted to embrace all such variations and modifications as fall within the spirit and scope of the appended claims.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (15)
- A memory array, comprising:at least one insulating layer and at least one second metal layer alternately stacked;an mxn number of first holes provided in each of the insulating layers and a corresponding mxn number of second holes provided in each of the second metal layers, each of the first holes being coaxial with the corresponding second hole, and a pore diameter of each of the first holes being smaller than a pore diameter of the corresponding second hole;a first metal layer extending through each of the first and second coaxial holes;the method comprises the steps of,a memory layer disposed within each of the second holes and surrounding the first metal layer;wherein M is an integer greater than or equal to 2, N is a positive integer, or M is a positive integer, and N is an integer greater than or equal to 2.
- The memory array of claim 1, wherein the first metal layer comprises a first end and a second end, at least one of the first end and the second end having a field effect transistor disposed thereon.
- The memory array of claim 2, further comprising:m×n first field effect transistors and m×n second field effect transistors corresponding to the m×n first metal layers;the first electrode of each first field effect transistor is connected with the first end of the corresponding first metal layer, and the second electrodes of N first field effect transistors in each row in the MxN first field effect transistors are connected to form a row word line of the memory array; third electrodes of M first field effect transistors in each column in the M×N first field effect transistors are connected to form a column selection line of the memory array;the first electrode of each second field effect transistor is connected with the second end of the corresponding first metal layer, and the third electrodes of N second field effect transistors in each row in the MxN second field effect transistors are connected to form a row selection line of the memory array; the second electrodes of the M second field effect transistors in each column in the M multiplied by N second field effect transistors are connected to form a column word line of the memory array;wherein the second electrode is a grid electrode; the first electrode is a source electrode and the third electrode is a drain electrode, or the first electrode is a drain electrode and the third electrode is a source electrode.
- A memory array according to claim 2 or 3, wherein the field effect transistor is a wraparound channel field effect transistor CAAFET or a metal oxide semiconductor field effect transistor MOSFET.
- A memory array as claimed in any one of claims 1 to 4, wherein one address line of the memory array is led out on each of the second metal layers, the address line being used to select a memory cell on the corresponding second metal layer.
- A memory array according to any one of claims 1 to 4 wherein there is a target second metal layer in the memory array, at least two rows or columns of adjacent second apertures of the target second metal layer being separated by a non-conductive material, any one of the target second metal layers separated by the non-conductive material leading out an address line of the memory array for selecting a memory cell on a corresponding one of the target second metal layers.
- The memory array of any one of claim 1 to 6,the storage array is a resistance change storage array, and the storage layer is composed of metal oxide; or alternatively, the first and second heat exchangers may be,the memory array is a ferroelectric memory array, and the memory layer is made of ferroelectric materials; or alternatively, the first and second heat exchangers may be,The storage array is a magnetic storage array, and the storage layer is made of magnetic materials; or alternatively, the first and second heat exchangers may be,the storage array is a phase-change storage array, and the storage layer is made of phase-change materials.
- The preparation method of the storage array is characterized in that the storage array is prepared by P times, the last preparation is stacked on the structure prepared in the previous time, and each preparation comprises the following steps:depositing an insulating layer;forming M×N first holes on the insulating layer by etching;depositing a first metal layer within each of the mxn first holes;depositing a second metal layer over the insulating layer and the first metal layer;etching to form M multiplied by N second holes on the second metal layer;forming a memory layer and the first metal layer surrounded by the memory layer in each of the m×n second holes;wherein P, M, N is a positive integer.
- The method of claim 8, further comprising, after the P preparations:one end of each first metal layer is connected with a first FET, and the other end of each first metal layer is connected with a second FET.
- The method of claim 8, wherein,After the second holes are etched on the second metal layer to form M×N second holes, the method further comprises the following steps:forming a separation region between at least two rows or at least two columns of adjacent second holes on the second metal layer through a metal cutting process, and filling a non-conductive material in the separation region;after the preparation for P times, the method further comprises the following steps:one end of each first metal layer is connected with the FET.
- A read-write control method, characterized by being applied to a controller connected to the memory array according to any one of claims 1 to 7;the method comprises the following steps:transmitting a read control signal to the memory array;receiving a read response signal returned by the storage array, wherein the read response signal is used for indicating data to be read;or,transmitting a write control signal to the memory array;and receiving a write response signal sent by the storage array, wherein the write response signal is used for indicating write success or write failure.
- The method of claim 11, wherein the memory array comprises a column select line, a row word line, a column word line, and a row select line, the controller being connected to the column select line, the row word line, the column word line, and the row select line, respectively;The method further comprises the steps of:when the data to be read is the data in the memory array, sending the read control signal to the column select line and the row word line; or,and when the data to be read is transposed data of the data in the storage array, sending the read control signals to the column word lines and the row selection lines.
- The method of claim 11, wherein the memory array comprises a column select line and a row word line, the column select line being connected to a sense amplifier, the controller being connected to the column select line, the row word line, and the sense amplifier;the method further comprises the steps of:transmitting the read control signal to at least two memory cells through the row word line and the column selection line;acquiring the current on the column selection line sensed by the sense amplifier;and determining the sum of data stored in the at least two memory cells according to the current magnitude.
- A memory comprising a controller and a memory array according to any one of claims 1 to 7, the controller being connected to the memory array, the controller being configured to perform the read-write control method according to any one of claims 11 to 13.
- An electronic device comprising a printed circuit board PCB and the memory of claim 14, the memory being located on the PCB.
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| PCT/CN2022/072369 WO2023133893A1 (en) | 2022-01-17 | 2022-01-17 | Storage array, preparation method, read-write control method, memory, and electronic device |
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| US10756110B1 (en) * | 2019-04-10 | 2020-08-25 | Sandisk Technologies Llc | Method of forming seamless drain-select-level electrodes for a three-dimensional memory device and structures formed by the same |
| CN110349964B (en) * | 2019-06-19 | 2020-08-14 | 长江存储科技有限责任公司 | Three-dimensional memory device and method for making three-dimensional memory device |
| DE102020127584B4 (en) * | 2020-05-28 | 2024-05-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | THREE-DIMENSIONAL STORAGE DEVICE WITH FERROELECTRIC MATERIAL |
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