CN110349964B - Three-dimensional memory device and manufacturing method thereof - Google Patents
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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Abstract
The embodiment of the application discloses a three-dimensional storage device and a manufacturing method thereof, wherein the three-dimensional storage device comprises: a substrate; a stack layer over the substrate; the first etching holes are distributed in a first area of the stacked layer according to a first density; the first etching hole is used for forming a storage transistor of a storage array; second etching holes distributed in a second region of the stacked layer according to a second density; wherein the second density is different from the first density; third etch holes distributed in a third region of the stack at a third density; wherein the third region is located between the first region and the second region; the third density being between the first density and the second density; and the stress generated by the third etching hole is used for transiting the stress generated by the first etching hole and the stress generated by the second etching hole.
Description
Technical Field
The embodiment of the application relates to a semiconductor manufacturing technology, and relates to, but is not limited to, a three-dimensional memory device and a manufacturing method of the three-dimensional memory device.
Background
Subject to the limitations of integrated circuit device size, the fabrication scheme of three-dimensional memory devices (3D-NAND) is widely adopted in the direction of development with increasing demands for data throughput. A three-dimensional memory device is a device having a three-dimensional structure formed by stacking a plurality of planar memory cells layer by layer, and is capable of achieving a larger memory capacity. Since the three-dimensional memory device is precise in structure and is easily defective during the manufacturing process, and thus leakage occurs during use, it is necessary to improve the internal structure of the three-dimensional memory device to reduce the possibility of occurrence of leakage.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a three-dimensional memory device and a method for fabricating the same.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a three-dimensional memory device, including:
a substrate;
a stack layer over the substrate;
the first etching holes are distributed in a first area of the stacked layer according to a first density; the first etching hole is used for forming a storage transistor of a storage array;
second etching holes distributed in a second region of the stacked layer according to a second density; wherein the second density is different from the first density;
third etch holes distributed in a third region of the stack at a third density; wherein the third region is located between the first region and the second region; the third density being between the first density and the second density; and the stress generated by the third etching hole is used for transiting the stress generated by the first etching hole and the first etching hole of the first etching hole and the stress generated by the second etching hole.
In a second aspect, an embodiment of the present application provides a method for manufacturing a three-dimensional memory device, where the method includes:
forming a stack layer on a semiconductor substrate;
forming first etching holes with first density in a first area of the stacked layers, wherein the first etching holes are used for forming storage transistors of a storage array;
forming second etch holes at a second density in a second region of the stack of layers, wherein the second density is different from the first density;
forming a third etch hole at a third density in a third region of the stack, wherein the third region is between the first and second regions; the third density being between the first density and the second density; and the stress generated by the third etching hole is used for transiting the stress generated by the first etching hole and the stress generated by the second etching hole.
In the embodiment of the application, the transition region is added in the region where the etching hole density is greatly changed, and the stress difference on two sides is balanced, so that the phenomenon that communication between the etching holes or the communication between the etching holes and the etching groove is caused by cracking or etching deviation under the action of larger application between the first region and the second region in the etching process or after the etching holes are formed is reduced, and the leakage phenomenon caused by the communication is further reduced. In this application, increased the third region that hole density is located between two regions in first region and the second region, the hole density in this third region can slow down the change gradient of stress to reduce the phenomenon of UNICOM between the etching hole or UNICOM between etching hole and the etching tank, and then reduce the product and take place the electric leakage when using.
Drawings
FIG. 1 is a schematic diagram of a partial structure of a three-dimensional memory device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a portion of another three-dimensional memory device according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional structure diagram of a three-dimensional memory device according to an embodiment of the present application;
FIG. 4 is a schematic flow chart illustrating an implementation of a method for fabricating a three-dimensional memory device according to an embodiment of the present disclosure;
FIG. 5A is a schematic diagram of an etched region of a three-dimensional memory device;
FIG. 5B is a top view of an etched region of another three-dimensional memory device;
fig. 6 is a schematic diagram of an etched region of a three-dimensional memory device in an embodiment of the present application.
Detailed Description
3D NAND (three dimensional flash memory) is a type of flash memory that addresses the limitations imposed by flash memory area in 2D or planar configurations by stacking memory cells together. The 3D NAND has a multi-layer stacked structure, and is a large-scale integrated circuit formed by a patterned structure of conductive layers and non-metal insulating layers made of metal, semiconductor, or the like, which are alternately distributed. The main characteristic is that it has multi-layer metal wiring, and in order to prevent short circuit between metal layers, non-metal insulating layer is deposited between layers to play the role of isolation. Between the multiple metal wires, it is also necessary to form electrical vias and form a memory array from channel holes perpendicular to the stacked film layers, thereby forming a three-dimensional circuit structure.
In the manufacturing process, when a device having a stacked structure is formed, it is necessary to form a deep trench and a deep hole in the stacked film layers by etching, and further to form a conductive path by injecting a conductive material or the like into the deep trench and the deep hole. In the etching process, stress difference is generated in distribution areas of different etched patterns, so that short circuit among different holes and grooves is easily caused, and the finished storage device is subjected to electric leakage.
In view of the above, the present application provides a solution to improve the short circuit problem between different etching holes or between an etching hole and an etching trench due to the stress difference generated by etching different regions.
The technical solution of the present application is further elaborated below with reference to the drawings and the embodiments.
An embodiment of the present application provides a three-dimensional memory device, as shown in fig. 1, including:
a substrate 10;
a stack 20 over the substrate;
The substrate may be made of a semiconductor material, such as a silicon wafer. The first etching holes and the second etching holes are distributed in different areas of the stacked layer, and the density refers to the density of the distribution of the etching holes. The aperture of the second etching hole may be the same as that of the first etching hole, or may be slightly larger than that of the first etching hole, and may be set according to actual requirements.
In the process of manufacturing the three-dimensional memory, materials in the holes are removed layer by layer from the upper part of the stacked layers by adopting an etching method to form the holes.
The etching method comprises the following steps: dry etching and wet etching.
The etching may include:
and corroding the surface of the film covered with the patterned photoresist to remove the film exposed at the photoresist window, and finally forming an etching hole or an etching groove and the like. The dry etching is to bombard the surface of the film layer by plasma to corrode the film layer; the wet etching is to soak the film layer to be removed by using a corrosive chemical solution to corrode the film layer. Finally, the film layer is removed within a certain pattern to form holes or grooves.
In the etching process, the densities of the etching holes in different regions are different, so that stress difference exists between adjacent regions, and if the stress difference is too large, the etching is deviated, so that the connection between different etching holes or etching holes and other regions such as etching grooves is caused.
Thus, here a third region is added between the first region and the second region, in which the third etching holes are distributed. The density of the third etching holes is between the first density and the second density, so that the stress generated on two sides can be balanced, a transitional area is formed, and the stress difference at the junction between different areas is reduced.
The third etching holes may be uniformly distributed, or may be distributed in a manner that the density is gradually reduced from the first region to the second region, so that the stress is gradually transited from the first region to the second region.
As shown in fig. 2, the three-dimensional memory device provided by the embodiment of the present application further includes:
at least one etched trench 50 extending from the top of the stack towards the substrate; the direction of the long edge of at least one etching groove is parallel to the extending direction from the first area to the second area;
at least one etching groove is filled with a conductive material; the conductive material serves as a common source stage for the memory transistors of the memory array. The conductive material here may be a metal, for example: aluminum or cobalt, and the like.
A plurality of storage transistors are distributed in a storage array of the three-dimensional storage device, and the sources of the storage transistors are required to be provided with voltage through a common source stage.
At least one etching groove is formed by etching, the etching grooves can be distributed on the stacked layer in parallel and extend from the top of the stacked layer to the direction of the substrate, and the etching holes are distributed between every two etching grooves.
If the difference of the distribution density of the holes is large in two adjacent areas of the etching holes, a large stress difference exists at the junction of the two areas, and when an etching groove is formed near the area where the etching holes are distributed, the etching groove is easy to generate cracks at the position crossing the two areas, so that the stress is released, and the etching groove is connected with the etching holes.
In the present embodiment, the stress variation between the different regions is reduced by the transition of the third region. In the process of forming the etching groove, the generation of cracks can be avoided as far as possible, and the connection between the etching groove and the etching hole is prevented.
In some embodiments, the stacked layers include: n conductive layers and N insulating layers; the conductive layers and the insulating layers are alternately arranged, and N is a positive integer not less than 2;
the areas of the N conductive layers and the N insulating layers are sequentially reduced from the substrate to the top of the stacked layer;
the first area is located in a core area below the insulating layer or the conducting layer on the top of the stacked layer;
the second region and the third region are located in a stepped region at an outer edge of the core region.
Fig. 3 is a cross-sectional view of a three-dimensional memory device in an embodiment of the present application, as shown in fig. 3, the areas of the conductive layers 21 and the insulating layers 22 in the stacked layer 20 are gradually decreased from the substrate toward the top of the stacked layer, the area of the conductive layer 21 or the insulating layer 22 at the top of the stacked layer is the smallest, and the area of the conductive layer 21 or the insulating layer 22 near the substrate is the largest. Thus, the periphery of the stacked layers forms a stepped region 23. The area under the insulating layer or the conductive layer on top of the stacked layer is the core area 24 of the stacked layer for forming the memory array of the memory, and the first etching hole 31 is located in this core area 23. In order to accommodate as many memory transistors as possible in the core region 23, the first etching holes 31 are distributed as densely as possible; the second etching holes 32 can be filled with conductive materials to connect the conductive layers with the leads of the three-dimensional memory, and can also be filled with insulating materials to form a structure for supporting the stacked layers, so that the second etching holes 32 are not required to be excessively dense; that is, the first density is greater than the second density.
In the present embodiment, the third etching hole 33 serves to transition the stress difference between the first region and the second region. The first region is the same as the core region 24, and the third via holes 33 may be distributed in the step region 23 so as not to affect the distribution of the first via holes 31, and may have the same structure as the second via holes 32, with a third density of the third via holes 33 being between the first density and the second density.
In some embodiments, the first etch hole penetrates through the stack layer; the first density is greater than the second density; the third density is less than the first density and greater than the second density;
the first etching hole comprises: the tunneling layer is arranged on the barrier layer; the barrier layer is used for separating the stacked layer from the storage layer; the storage layer is used for acquiring charges from the channel layer; the tunneling layer is used for blocking the storage layer and the channel layer; the channel layer is used for providing electric charges; wherein when the stacked layer provides a voltage to acquire charge, the charge in the channel layer breaks down the tunneling layer to provide the charge to the memory layer.
The barrier layer, the memory layer, the tunneling layer, and the channel layer herein are main portions constituting the memory transistor. The first etching hole can be called a channel hole, each conducting layer in the stacked layers and the structure in the channel hole form a storage transistor, one channel hole is formed in the whole stacked layers, a plurality of storage transistors which are connected together in series can be formed, and electric signals are obtained through a common source and a common drain; each conductive layer provides a gate voltage signal for the memory transistors.
In some embodiments, the second etching hole is filled with a conductive material; and the second etching hole is used for connecting the conductive layer in the stacked layer and a lead of the three-dimensional memory.
In some embodiments, the third etching hole is filled with a conductive material; and a third etching hole for connecting the conductive layer in the stacked layer with a conductive line of the three-dimensional memory.
The second etching hole and the third etching hole are both located in the step region, and the etching hole of the step region may not be used for forming the memory transistor. Conductive materials can be filled in the second etching holes and connected with one conductive layer in the stacked layers, so that signals of the conductive layers are led out; and the third etching hole can be filled with a conductive material to realize the same function as the second etching hole.
Of course, the third etching hole in the embodiment of the present application realizes the effect of balancing the stress of the first region and the second region, and when the etching hole for leading out the wiring from each conductive layer is enough, the insulating material may also be injected into a part of the second etching hole and the third etching hole, so as to play a certain supporting role.
An embodiment of the present application provides a method for manufacturing a three-dimensional memory, as shown in fig. 4, the method includes:
102, forming first etching holes with a first density in a first area of the stacked layer, wherein the first etching holes are used for forming storage transistors of a storage array;
103, forming a second etching hole with a second density in a second area of the stacked layer, wherein the second density is different from the first density;
In the above process, the first etching hole, the second etching hole and the third etching hole may be formed simultaneously, that is, three etching holes with different densities are formed in the stacked layer by one etching process. The density here refers to the density of the distribution of the etching holes. The three etching holes with different densities can also be formed by etching respectively in a plurality of times.
The first etching holes may be distributed in a core region for forming a memory array, and the first etching holes may be channel holes for forming memory transistors of the memory array. The second etching hole and the third etching hole may be positioned
Because the difference between the first density and the second density is larger, a larger stress difference exists between the first region and the second region in the process of forming the etching holes, and the third region positioned between the first region and the second region can transit the stress between the first region and the second region, so that the etching is prevented from shifting, and abnormal connection between the etching holes or between the etching holes and other regions is avoided.
In some embodiments, the above method further comprises:
105, forming at least one etching groove in the stacked layer; wherein, at least one etching groove is formed by etching from the top of the stacked layer to the substrate direction; the direction of the long edge of at least one etching groove is parallel to the extending direction from the first area to the second area;
and 106, filling a conductive material in the at least one etching groove to form a common source stage of the storage transistor of the storage array.
In the above process, the etching holes including the first etching hole, the second etching hole and the third etching hole may be formed by etching, and the etching groove may be formed by etching; the etching hole and the etching groove may be formed simultaneously. The stress between the first region and the second region is transited through the third region, so that the etching groove is prevented from cracking at the junction of different regions and is connected with the etching hole nearby.
In some embodiments, the stacked layers include: n conductive layers and N insulating layers; the conductive layers and the insulating layers are alternately arranged, and N is a positive integer not less than 2;
the areas of the N conductive layers and the N insulating layers are sequentially reduced from the substrate to the top of the stacked layer;
the first area is located in a core area below the insulating layer or the conducting layer on the top of the stacked layer;
the second region and the third region are located in a stepped region at an outer edge of the core region.
In some embodiments, the first etching hole penetrates through the stack layer; the first density is greater than the second density; the third density is less than the first density and greater than the second density; the method further comprises the following steps:
sequentially forming a barrier layer, a storage layer, a tunneling layer and a channel layer in the first etching hole; the barrier layer is used for separating the stacked layer from the storage layer; the storage layer is used for acquiring charges from the channel layer; the tunneling layer is used for blocking the storage layer and the channel layer; the channel layer is used for providing electric charges; wherein when the stacked layer provides a voltage to acquire charge, the charge in the channel layer breaks down the tunneling layer to provide the charge to the memory layer.
In some embodiments, the above method further comprises:
filling a conductive material in the second etching hole; the second etching hole is used for connecting the conducting layer in the stacking layer and a lead of the three-dimensional memory; and/or the presence of a gas in the gas,
filling a conductive material in the third etching hole; and a third etching hole for connecting the conductive layer in the stacked layer with a conductive line of the three-dimensional memory.
The second etching hole and the third etching hole are both located in the above-described step region, and neither of the etching holes of the step region is used for forming the memory transistor. Conductive materials can be filled in the second etching holes and connected with one conductive layer in the stacked layers, so that signals of the conductive layers are led out; and the third etching hole can be filled with a conductive material to realize the same function as the second etching hole. Of course, the third etching hole in the embodiment of the present application realizes the effect of balancing the stress of the first region and the second region, and when the etching hole for leading out the wiring from each conductive layer is enough, the insulating material may also be injected into a part of the second etching hole and the third etching hole, so as to play a certain supporting role.
An embodiment of the present application provides a three-dimensional memory device, and fig. 5A is a schematic diagram of an etched region of the three-dimensional memory device. Fig. 5B is a top view of an etched region of another three-dimensional memory device, taken by a Scanning Electron Microscope (SEM) corresponding to the position shown in fig. 5A. As shown in fig. 5A, etching holes 210 and etching trenches 220 are distributed in an etching region of a three-dimensional memory device, the etching holes distributed in a core region are distributed in nine rows of hole regions 231, and 9 etching holes are distributed in each column in a staggered manner between two etching trenches to form a memory array. The etching holes in the step region are distributed in four rows of hole regions 232 and three rows of hole regions 233. The etching grooves are distributed among the areas where the etching holes are located in parallel, and a small distance exists between each etching groove and each etching hole.
Because the density difference of the etching holes between the nine-row hole region 231 and the four-row hole region 232 is large, a large stress difference exists at the boundary of the two regions, and when the etching trench 220 is formed, the stress is easily released at the boundary of the two regions, so that the etching trench 220 gradually deviates to the etching hole 210, and is finally connected together at the abnormal point 240. After the etching trench 220 is formed, a conductive material is filled in the etching trench 220, and since the etching trench 220 is connected to the etching hole 210, an abnormal short circuit is formed after the conductive material is filled, thereby causing leakage in use.
Therefore, in the embodiment of the present application, the structure shown in fig. 6 is adopted, and the transition region 250 of seven rows of holes to five rows of holes is added between the nine-row hole region 231 and the three-row hole region 233 in the core region, so that the region with larger stress difference is gradually and slowly transitioned, thereby reducing the local stress difference, avoiding the connection between the etching trench 220 and the etching hole 210, and solving the problem of electric leakage. Obviously, at the improved abnormal point 240, the etched trench 220 has less deviation to the via, and the etched trench 220 is not connected to the via 210.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A three-dimensional memory device, comprising:
a substrate;
a stack layer over the substrate;
the first etching holes are distributed in a first area of the stacked layer according to a first density; the first etching hole is used for forming a storage transistor of a storage array;
second etching holes distributed in a second region of the stacked layer according to a second density; wherein the second density is different from the first density;
third etch holes distributed in a third region of the stack at a third density; the third area is positioned between the first area and the second area and is respectively adjacent to the first area and the second area; the third density being between the first density and the second density; and the stress generated by the third etching hole is used for transiting the stress generated by the first etching hole and the stress generated by the second etching hole.
2. The three-dimensional memory device of claim 1, further comprising:
at least one etched trench extending from the substrate on top of the stack of layers; the direction of the long edge of the at least one etching groove is parallel to the extending direction from the first area to the second area;
the at least one etching groove is filled with a conductive material; the conductive material serves as a common source stage for the memory transistors of the memory array.
3. The three-dimensional memory device of claim 1, wherein the stacked layers comprise: n conductive layers and N insulating layers; the conductive layers and the insulating layers are alternately arranged, and N is a positive integer not less than 2;
the areas of the N conductive layers and the N insulating layers are sequentially reduced from the substrate to the top of the stacked layer;
the first area is located in a core area below an insulating layer or a conductive layer on the top of the stacked layers;
the second region and the third region are located in a stepped region at an outer edge of the core region.
4. The three-dimensional memory device of claim 3, wherein the first via extends through the stack of layers; the first density is greater than the second density; the third density is less than the first density and the third density is greater than the second density;
the first etching hole comprises: the tunneling layer is arranged on the barrier layer; the barrier layer is used for separating the stacked layer from the storage layer; the storage layer is used for acquiring charges from the channel layer; the tunneling layer is used for blocking the storage layer and the channel layer; the channel layer is used for providing electric charges; wherein when the stack layer provides a voltage to acquire charge, the charge in the channel layer breaks down the tunneling layer to provide charge to the storage layer.
5. The three-dimensional memory device according to claim 4, wherein the second via hole is filled with a conductive material; the second etching hole is used for connecting the conducting layer in the stacked layer and a conducting wire of the three-dimensional memory; and/or the presence of a gas in the gas,
conductive materials are filled in the third etching holes; the third etching hole is used for connecting the conductive layer in the stacked layer and a lead of the three-dimensional memory.
6. A method of fabricating a three-dimensional memory device, the method comprising:
forming a stack layer on a semiconductor substrate;
forming first etching holes with first density in a first area of the stacked layers, wherein the first etching holes are used for forming storage transistors of a storage array;
forming second etch holes at a second density in a second region of the stack of layers, wherein the second density is different from the first density;
forming a third etching hole with a third density in a third area of the stacked layer, wherein the third area is located between the first area and the second area and is adjacent to the first area and the second area respectively; the third density being between the first density and the second density; and the stress generated by the third etching hole is used for transiting the stress generated by the first etching hole and the stress generated by the second etching hole.
7. The method of manufacturing according to claim 6, further comprising:
forming at least one etching groove in the stacked layer; wherein the at least one etching groove is formed by etching from the top of the stacked layer to the substrate direction; the direction of the long edge of the at least one etching groove is parallel to the extending direction from the first area to the second area;
and filling a conductive material in the at least one etched groove to form a common source stage of the storage transistor of the storage array.
8. The method of manufacturing according to claim 6, wherein the stacking layer comprises: n conductive layers and N insulating layers; the conductive layers and the insulating layers are alternately arranged, and N is a positive integer not less than 2;
the areas of the N conductive layers and the N insulating layers are sequentially reduced from the substrate to the top of the stacked layer;
the first area is located in a core area below an insulating layer or a conductive layer on the top of the stacked layers;
the second region and the third region are located in a stepped region at an outer edge of the core region.
9. The method of claim 8, wherein the first via hole penetrates through the stack layer; the first density is greater than the second density; the third density is less than the first density and the third density is greater than the second density; the method further comprises the following steps:
sequentially forming a barrier layer, a storage layer, a tunneling layer and a channel layer in the first etching hole; the barrier layer is used for separating the stacked layer from the storage layer; the storage layer is used for acquiring charges from the channel layer; the tunneling layer is used for blocking the storage layer and the channel layer; the channel layer is used for providing electric charges; wherein when the stack layer provides a voltage to acquire charge, the charge in the channel layer breaks down the tunneling layer to provide charge to the storage layer.
10. The method of manufacturing according to claim 9, further comprising:
filling a conductive material in the second etching hole; the second etching hole is used for connecting the conducting layer in the stacked layer and a conducting wire of the three-dimensional memory; and/or the presence of a gas in the gas,
filling a conductive material in the third etching hole; the third etching hole is used for connecting the conductive layer in the stacked layer and a lead of the three-dimensional memory.
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| CN110649033B (en) * | 2019-10-25 | 2022-05-06 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111312713B (en) * | 2020-03-03 | 2021-07-20 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
| CN111403390B (en) * | 2020-03-23 | 2023-04-18 | 长江存储科技有限责任公司 | Semiconductor structure, manufacturing method thereof and three-dimensional memory device |
| CN111403399B (en) * | 2020-03-30 | 2023-02-03 | 长江存储科技有限责任公司 | Three-dimensional memory device and manufacturing method thereof |
| CN111540747B (en) * | 2020-04-27 | 2021-07-16 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device |
| CN112331655B (en) * | 2020-11-10 | 2021-09-10 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN117413628A (en) * | 2022-01-17 | 2024-01-16 | 华为技术有限公司 | Memory array, preparation method, read-write control method, memory and electronic equipment |
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| US9613896B2 (en) * | 2015-03-18 | 2017-04-04 | Kabushiki Kaisha Toshiba | Semiconductor memory device with conductive columnar body |
| US10083982B2 (en) * | 2016-11-17 | 2018-09-25 | Sandisk Technologies Llc | Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof |
| CN108461503B (en) * | 2018-04-25 | 2019-11-08 | 长江存储科技有限责任公司 | The manufacturing method of three-dimensional storage and the method for forming crystal silicon layer |
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