CN117316261B - Specific adapting device for memory FT test - Google Patents
Specific adapting device for memory FT test Download PDFInfo
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- CN117316261B CN117316261B CN202311595116.XA CN202311595116A CN117316261B CN 117316261 B CN117316261 B CN 117316261B CN 202311595116 A CN202311595116 A CN 202311595116A CN 117316261 B CN117316261 B CN 117316261B
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- 238000012360 testing method Methods 0.000 title claims abstract description 84
- 230000007246 mechanism Effects 0.000 claims abstract description 43
- 238000003032 molecular docking Methods 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 22
- 210000001503 joint Anatomy 0.000 claims description 12
- 230000002159 abnormal effect Effects 0.000 claims description 6
- 238000003780 insertion Methods 0.000 claims description 6
- 230000037431 insertion Effects 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 4
- 238000012546 transfer Methods 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000006978 adaptation Effects 0.000 claims 1
- 230000007306 turnover Effects 0.000 abstract 1
- 238000002408 directed self-assembly Methods 0.000 description 29
- 238000013100 final test Methods 0.000 description 14
- 238000013461 design Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011990 functional testing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000013468 resource allocation Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a specific adapting device for FT test of a memory, which belongs to the technical field of chip test and particularly comprises an automatic sorting machine, an ATE (automatic test equipment) tester, a docking mechanism and a turnover mechanism, wherein the docking mechanism is used for docking the automatic sorting machine and the ATE tester; the docking mechanism comprises a basic mechanical frame, an up-down floating mechanism, a resin mechanism, an interface board and a device specific adapting device; the equipment specific adapting device is an outermost interface for contacting the ATE tester with a storage chip in the automatic sorting machine and is used for connecting the ATE tester with the storage chip; the device specific adapting device is divided into 32 DSA units, each DSA unit comprises an interface board and a device specific adapting device, and 16 chip sockets are placed in each DSA unit and are used for realizing the test of 512 chips to be tested at a time; the invention improves the testing efficiency.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a specific adapting device for FT testing of a memory.
Background
With the increasing progress of technology, fields such as automobile electronics, wearable devices, smart home, industrial control, etc. are actively developed, and memory chips are an important component of these devices, so testing of memory chips and testing devices become particularly important.
The package test FT (Final test), which is usually the last test before the chip is shipped, is the test with the largest test items, and sometimes needs to be performed at 3 temperature, so that the test cost is high. The FT test belongs to chip level test, and is to establish electrical connection between Automatic Test Equipment (ATE) and a packaged chip through a test board (Loadboard) and a test chip socket (chip socket), perform electrical connectivity test, functional test, parameter test and the like on the chip, and screen out products meeting design specifications according to test results. Hardware devices typically required for FT testing include test boards, test chip sockets, ATE test equipment, hander, and the like.
The biggest difficulty of the FT test of the DRAM memory is how to ensure that the Unit delivered from the factory can complete all functions in the shortest time, and therefore, the invention provides a specific adapting device for the FT test of the memory.
Disclosure of Invention
The invention aims to provide a specific adapting device for a memory FT test, which solves the following technical problems:
the biggest difficulty of the FT test of the DRAM memory is how to ensure that the Unit delivered from the factory can complete all functions in the shortest time.
The aim of the invention can be achieved by the following technical scheme:
a specific adapter device for memory FT testing, comprising an automated sorter, an ATE tester, a docking mechanism, and a flipping mechanism, wherein:
the automatic sorting machine is used for realizing FT test automation, the docking mechanism is used for docking the automatic sorting machine and the ATE test machine, and the turning mechanism is used for turning over the ATE test machine;
the docking mechanism comprises a basic mechanical frame, an up-down floating mechanism, a resin mechanism, an interface board and a device specific adapting device; the equipment specific adapting device is an outermost interface for contacting the ATE tester with a storage chip in the automatic sorting machine and is used for connecting the ATE tester with the storage chip;
the device specific adapting device comprises 32 DSA units, and 16 chip sockets are placed in each DSA unit and are used for testing 512 chips to be tested at a time.
As a further scheme of the invention: the device specific adapting device corresponds to the interface board one by one, the interface board is used for placing components of a terminating circuit, the on-off of the terminating circuit controls the switching of the relay through a control signal, and the transfer signal is communicated with the mainboard of the ATE tester and the socket substrate.
As a further scheme of the invention: the DSA units include a socket Guide, a chip socket, a socket substrate, a fixed mechanical structure, a Guide Pin, a Locking screen, and an Insertion Guide.
As a further scheme of the invention: in DSA unit:
the socket Guide is positioned at the uppermost layer of the DSA and is used for fixing the chip socket;
the chip socket is a contact surface between the test resource and the chip to be tested and is replaced according to different packages of the chip to be tested;
the socket substrate is used for distributing test resources and placing a power supply filter capacitor;
the fixed mechanical structure is used for controlling the butt joint depth of the automatic sorting machine and the ATE tester, reading the contact resistance of the chip pins to be tested, and if the resistance data are normal, indicating that the butt joint depth accords with the preset depth; if the resistance data is abnormal, indicating that the butt joint is abnormal, and stopping the test;
the Guide Pin is a positioning device of the DSA unit in the docking mechanism; locking screen and Insertion Guide are used to lock the DSA units.
As a further scheme of the invention: each equipment specific adapting device corresponds to a socket substrate, each socket substrate comprises 4 connectors, each interface board is connected with 16 chips to be tested, each 4 chips to be tested are uniformly distributed around a single connector, test resources in each connector are identical, and test resources in each equipment specific adapting device are identical.
As a further scheme of the invention: each connector IS distributed with 48 IO channels, 32 DR channels, 8 DPS power supplies, 4 OPTICAL power supplies, 1 termination power supply, one path of 5V power supply and 8 paths of relay control signals, wherein the relay control signals are used for controlling a relay or an optocoupler, and 3 paths of calibration IO signals and 1 path of nDUT_IS signals;
the docking mechanism further comprises 4 ID boards, the ID boards are matched with the nDUT_IS signals, 4 groups of dial switches are arranged in the ID boards and are connected with a CPU in the ATE tester through IO signals, if the CPU reads the nDUT_IS signals, the socket substrate IS judged to be connected, and then the CPU judges the types of the socket substrate and the chip to be tested through reading the setting information of the ID boards; if the CPU does not read the nDUT_IS signal, the socket substrate IS judged to be unconnected.
As a further scheme of the invention: two dry air holes are provided in each DSA unit for preventing condensed water during low temperature testing.
As a further scheme of the invention: the DSA unit locking and ejecting process comprises the following steps:
and (3) placing the DSA unit on the docking mechanism through four Guide pins arranged on the fixed mechanical structure, screwing a Locking screen in the fixed mechanical structure, and Locking and ejecting the DSA unit.
As a further scheme of the invention: the up-down floating mechanism is used for buffering impact force generated in the butt joint process of the ATE tester and the automatic sorting machine.
As a further scheme of the invention: the resin mechanism is used for isolating temperature transmission during high-temperature testing and low-temperature testing.
The invention has the beneficial effects that:
the invention realizes the accurate butt joint of the ATE tester and the memory chips through the equipment specific adapting device, ensures the testing accuracy, realizes the signal transmission and switching through the design of the interface board and the socket base board, ensures the testing stability, realizes the control of the butt joint depth through the design of the fixed mechanical structure, and improves the testing safety.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic view of the resource allocation of the socket substrate of the present invention;
fig. 3 is a schematic structural view of an interface board of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-3, a specific adapter apparatus for memory FT testing includes an automated sorter Handler, an ATE tester, a docking mechanism HI-FIX, and a flipping mechanism, wherein:
the automatic sorting machine is used for realizing FT test automation, the docking mechanism is used for docking the automatic sorting machine and the ATE test machine, and the turning mechanism is used for turning over the ATE test machine;
the docking mechanism comprises a basic mechanical Frame, an up-down floating mechanism floating Unit, a resin mechanism Epoxy Frame, an Interface Board and a device specific adapting device Device specific adapter; the equipment specific adapting device is an outermost interface for contacting the ATE tester with a storage chip in the automatic sorting machine and is used for connecting the ATE tester with the storage chip;
the device specific adapting device comprises 32 DSA units (interface+DSA), 16 chip socket sockets are placed in each DSA unit, socket models are required to be replaced according to the change of tested chips, and the device specific adapting device is used for testing 512 chips DUTs to be tested at a time.
In a preferred embodiment of the present invention, the device specific adapting apparatus corresponds to the interface board one by one, the interface board is used for placing components of a termination circuit, the on-off of the termination circuit controls the relay to switch through a control signal, and the relay is communicated with the motherboard of the ATE tester and the socket substrate, and one HI-FIX can place 32 DSA units, and the total parallel number is 512 Para.
The interface board is provided with 8 groups of terminating circuits, each group of terminating circuits can control 4 paths of terminating signals, the total number can realize 32 paths of terminating signals, only one path of terminating power VTERM_F and one path of CW signal (namely Ubits signal) are needed, the software control or the programming of a test program are extremely convenient, and more terminating power supplies and Ubits signals, such as 4 paths of Optional power supplies and 8 paths of Ubits signals, can be provided according to the requirements of a test chip.
The signal termination is used to ensure signal quality, and typically, half of the power supply VDDQ of the memory chip is connected to the power supply through 50 ohms as a pull-up source, and the pull-up resistor in the circuit is 48.7 ohms, plus the resistors of the relay, and the total number is about 50 ohms.
The Interface Board and the Socket Board are used in a matched mode, the Interface Board can place the devices which are not placed in the Socket Board in the Interface Board so as to save space in the Socket Board, most of the Socket Board space is limited because the Top surface needs to place the Socket, absolute flatness is needed, no devices can be placed in general, the Bottom surface has a small amount of space for placing the components (usually various types of filter capacitors), the rest of the circuits need to be placed on the Interface Board, such as signal termination circuits, and besides, the Interface Board is used only as a connector to communicate with the main Board and the Socket Board, and whether the termination circuits need to be used or not can be switched through a relay. The interface board also does not need to be redesigned and can be reused if the connector portion signal assignment remains unchanged in the motherboard and Socket board.
In another preferred embodiment of the present invention, the DSA unit includes Socket Guide, chip Socket, socket Board, fixed mechanical structure Spacer Block, guide Pin, locking screen and Insertion Guide.
In a preferred case of the present embodiment, in the DSA unit:
the socket Guide is positioned at the uppermost layer of the DSA and is used for fixing the chip socket;
the chip socket is a contact surface between the test resource and the chip to be tested and is replaced according to different packages of the chip to be tested;
the socket substrate is used for distributing test resources and placing a power supply filter capacitor;
the fixed mechanical structure is used for controlling the butt joint depth of the automatic sorting machine and the ATE tester, reading the contact resistance of the chip pins to be tested, and if the resistance data are normal, indicating that the butt joint depth accords with the preset depth; if the resistance data is abnormal, indicating that the butt joint is abnormal, and stopping the test;
the Guide Pin is a positioning device of the DSA unit in the docking mechanism; locking screen and Insertion Guide are used to lock the DSA units.
The range of the locking depth of the Handler is 27.5 mm-37.45 mm, and the locking depth of the Handler needs to be matched when designing DSA, so that the tester and the chip are prevented from being damaged during locking.
The design of the present invention is 33mm from the resin mechanism surface to the chip socket surface, and the mechanical parts used to secure the interface board and socket substrate need to calculate the height at the time of design to meet the 33mm design scale here.
In another preferred case of this embodiment, each of the device-specific adapting apparatuses corresponds to a socket substrate, each of the socket substrates includes 4 connectors, each of the interface boards is connected with 16 chips to be tested, each of the 4 chips to be tested is uniformly distributed around a single connector, test resources in each of the connectors are identical, and test resources in each of the device-specific adapting apparatuses are identical.
The Socket board comprises 16 chips DUTs to be tested, the chips DUTs are uniformly distributed around 4 connectors, resources on each connector are completely consistent, 32 DSAs are distributed on each HI-FIX, and the resources are also completely consistent, so that 512 DUTs are required to be designed only by designing 4 DUTs on each connector during design.
In another preferred case of this embodiment, 48 IO channels, 32 DR (Drive only) channels, 8 DPS power supplies, 4 Optional power supplies, 1 termination power supply (for providing termination voltage to the signal) and one 5V power supply are allocated on each connector; 8-way Ubits (relay control signal) signals, wherein a single Ubits signal can provide up to 70mA current for controlling a relay or an optocoupler; 3 paths of calibration IO signals; 1-way nDUT_IS signal.
Wherein, 3 way calibration IO signals: the IO signal is used for transmitting calibration data, and the calibration data is sent to a CPU in the tester for saving and calling, so that the time delay from all digital signals to the pins of the DUT is ensured to be within a specification range, and the spec of the tester is +/-100 ps.
Wherein, 1 path nDUT_IS signal: the Socket Board can be used for judging the connectivity and the types of the Socket Board and the Device which are connected, 4 ID boards fixed on HI-FIX are required to be matched for use, 4 groups of dial switches are arranged on the ID boards, the dial switches are connected with a CPU (central processing unit) in the tester through IO signals, after the CPU reads nDUT_IS signals, the CPU confirms that the Socket boards are connected, and then reads the setting information of the ID boards, so that the types of the Socket boards and the DUT are judged, 16 bits are arranged on a single ID Board in total, and 64 bits are arranged on the 4 ID boards in total, so that various setting requirements can be met.
In the whole testing process, four main boards are used, 32 identical connectors are arranged in each main board, signals in different instruments are integrated into the connectors and transmitted to the interface boards, signal distribution in each connector is identical, 4 connectors are arranged in each interface board, each main board is connected with 8 identical interface boards through cables, and 32 identical interface boards are shared in total. The Socket boards are identical to the connectors in the interface boards in position, and each Socket board and the interface board can be in one-to-one correspondence, so that 32 Socket boards are also used. The signals in each connector can be distributed to 4 DUTs in a Socket board for testing, and 4 connectors in each DSA, so that 512 DUTs can be tested in parallel in total.
In another preferred embodiment of the present invention, there are two dry air holes per DSA unit for preventing condensed water during low temperature testing, resulting in short circuits, thereby failing the test and damaging the chip. The total flow of dry air is 30-350 LPM, conventionally set to 290 LPM, and is distributed to each DSA unit at 9 LPM/DSA, thereby ensuring that the test process is not affected by condensate.
In another preferred case of this embodiment, the DSA unit locking and ejecting process is:
and (3) placing the DSA unit on the docking mechanism through four Guide pins arranged on the fixed mechanical structure, screwing a Locking screen in the fixed mechanical structure, and Locking and ejecting the DSA unit.
In another preferred embodiment of the present invention, the up-down floating mechanism is used to buffer the impact forces generated during docking of the ATE tester and the automated sorter.
In another preferred embodiment of the present invention, the resin mechanism is used to isolate temperature transfer during both high temperature testing and low temperature testing.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (6)
1. A specific adapter device for memory FT testing, comprising an automated sorter, an ATE tester, a docking mechanism, and a flipping mechanism, wherein:
the automatic sorting machine is used for realizing FT test automation, the docking mechanism is used for docking the automatic sorting machine and the ATE test machine, and the turning mechanism is used for turning over the ATE test machine;
the docking mechanism comprises a basic mechanical frame, an up-down floating mechanism, a resin mechanism, an interface board and a device specific adapting device; the equipment specific adapting device is an outermost interface for contacting the ATE tester with a storage chip in the automatic sorting machine and is used for connecting the ATE tester with the storage chip;
the device specific adapting device corresponds to the interface boards one by one, each interface board and the device specific adapting device form a DSA unit, the docking mechanism comprises 32 DSA units, 16 chip sockets are placed in each DSA unit, and the docking mechanism is used for realizing the test of 512 chips to be tested at a time;
the DSA unit comprises a socket Guide, a chip socket, a socket substrate, a fixed mechanical structure, a Guide Pin, a Locking screen and an Insertion Guide;
in DSA unit:
the socket Guide is positioned at the uppermost layer of the DSA and is used for fixing the chip socket;
the chip socket is a contact surface between the test resource and the chip to be tested and is replaced according to different packages of the chip to be tested;
the socket substrate is used for distributing test resources and placing a power supply filter capacitor;
the fixed mechanical structure is used for controlling the butt joint depth of the automatic sorting machine and the ATE tester, reading the contact resistance of the chip pins to be tested, and if the resistance data are normal, indicating that the butt joint depth accords with the preset depth; if the resistance data is abnormal, indicating that the butt joint is abnormal, and stopping the test;
the Guide Pin is a positioning device of the DSA unit in the docking mechanism; the Locking screen and the Insertion Guide are used for Locking the DSA unit;
each equipment specific adapting device corresponds to a socket substrate, each socket substrate comprises 4 connectors, each interface board is connected with 16 chips to be tested, each 4 chips to be tested are uniformly distributed around a single connector, the testing resources in each connector are identical, and the testing resources in each equipment specific adapting device are identical;
each connector IS distributed with 48 IO channels, 32 DR channels, 8 DPS power supplies, 4 OPTICAL power supplies, 1 termination power supply, one path of 5V power supply and 8 paths of relay control signals, wherein the relay control signals are used for controlling a relay or an optocoupler, and 3 paths of calibration IO signals and 1 path of nDUT_IS signals;
the docking mechanism further comprises 4 ID boards, the ID boards are matched with the nDUT_IS signals, 4 groups of dial switches are arranged in the ID boards and are connected with a CPU in the ATE tester through IO signals, if the CPU reads the nDUT_IS signals, the socket substrate IS judged to be connected, and then the CPU judges the types of the socket substrate and the chip to be tested through reading the setting information of the ID boards; if the CPU does not read the nDUT_IS signal, the socket substrate IS judged to be unconnected.
2. A special adapting device for testing a memory FT according to claim 1, characterized in that the interface board is used for placing components of a termination circuit, the on-off of which is controlled by a control signal to switch a relay, and the transfer signal is communicated with the motherboard of the ATE tester and the socket substrate.
3. A special adaptation device for a memory FT test according to claim 1, characterized in that two dry air holes are provided in each DSA unit for preventing condensed water during low temperature testing.
4. A specific adapting device for memory FT testing according to claim 1, characterized in that the DSA unit locking and ejecting procedure is:
and (3) placing the DSA unit on the docking mechanism through four Guide pins arranged on the fixed mechanical structure, screwing a Locking screen in the fixed mechanical structure, and Locking and ejecting the DSA unit.
5. A specific adapter for memory FT testing according to claim 1, characterized in that the up-down floating mechanism is used to buffer the impact forces generated during the docking of the ATE tester and the automated sorter.
6. A specific adapting device for memory FT testing according to claim 1, characterized in that the resin means is used to isolate temperature transfer during high temperature testing and low temperature testing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311595116.XA CN117316261B (en) | 2023-11-28 | 2023-11-28 | Specific adapting device for memory FT test |
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| CN202311595116.XA CN117316261B (en) | 2023-11-28 | 2023-11-28 | Specific adapting device for memory FT test |
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| CN117316261A CN117316261A (en) | 2023-12-29 |
| CN117316261B true CN117316261B (en) | 2024-02-09 |
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| CN117555738B (en) * | 2024-01-09 | 2024-04-05 | 悦芯科技股份有限公司 | DPS power supply board for memory FT test |
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| CN102066960A (en) * | 2008-04-17 | 2011-05-18 | 泰拉丁公司 | Enclosed operating area for storage device testing systems |
| KR101386224B1 (en) * | 2013-11-06 | 2014-04-18 | 주식회사 아이티엔티 | The floating device for dsa board of automatic test equipment and hi-fix board having the floating device |
| CN109411390A (en) * | 2018-09-11 | 2019-03-01 | 深圳赛意法微电子有限公司 | The automation classification packaging method and system of semiconductor devices |
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| CN115754386A (en) * | 2022-12-29 | 2023-03-07 | 杭州长川科技股份有限公司 | Docking device and test equipment |
| CN116821045A (en) * | 2023-08-28 | 2023-09-29 | 悦芯科技股份有限公司 | Board card structure for testing 512DUT memory device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6754866B1 (en) * | 2001-09-28 | 2004-06-22 | Inapac Technology, Inc. | Testing of integrated circuit devices |
| US7370256B2 (en) * | 2001-09-28 | 2008-05-06 | Inapac Technology, Inc. | Integrated circuit testing module including data compression |
| US10613128B2 (en) * | 2015-10-22 | 2020-04-07 | Powertech Technology Inc. | Testing device and testing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102066960A (en) * | 2008-04-17 | 2011-05-18 | 泰拉丁公司 | Enclosed operating area for storage device testing systems |
| KR101386224B1 (en) * | 2013-11-06 | 2014-04-18 | 주식회사 아이티엔티 | The floating device for dsa board of automatic test equipment and hi-fix board having the floating device |
| CN109411390A (en) * | 2018-09-11 | 2019-03-01 | 深圳赛意法微电子有限公司 | The automation classification packaging method and system of semiconductor devices |
| CN110501630A (en) * | 2019-08-15 | 2019-11-26 | 国网江西省电力有限公司电力科学研究院 | A safety chip fault location analysis system |
| CN115754386A (en) * | 2022-12-29 | 2023-03-07 | 杭州长川科技股份有限公司 | Docking device and test equipment |
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