CN117276270A - Silicon controlled rectifier and manufacturing method thereof - Google Patents

Abstract

The invention provides a silicon controlled rectifier and a manufacturing method thereof, which include a first conductive type well region, a first conductive type compensation region, and a first conductive type well region spaced in a first conductive type substrate. extension of the second conductivity type well region. The first conductivity type compensation region extends from the first conductivity type well region toward the extension part and is connected to the extension part. In this way, when the first conductivity type compensation region connected to the extension part is formed through an overlay process, even if the lithography apparatus is The engraving accuracy is not high, which also greatly reduces the impact on the base width of the parasitic transistor, preventing the base width from being unstable, thus making the SCR parameters more stable and consistent. And such a structure allows greater freedom in adjusting the concentration of the first conductivity type compensation region during manufacturing, thereby allowing the trigger voltage of the silicon controlled rectifier to have a wider range.

Description

Silicon controlled rectifier and manufacturing method thereof

Technical field

The invention relates to the field of semiconductor technology, and in particular to a silicon controlled rectifier and a manufacturing method thereof.

Background technique

Silicon Controlled Rectifier (SCR), also known as thyristor, is used in various high-power input and/or output situations such as controlled rectifiers, power supply voltage regulation, and power inverter due to its extremely strong current conduction ability. Be widely used. Due to its high current density, SCR can have a smaller active area area under the same current conditions, and the corresponding junction capacitance is also lower than other structures, so it is suitable as a low-capacitance protection device. As a protection device, under the same layout area, the current flow capacity of SCR after triggering is better than that of other electrostatic discharge (ESD) devices such as diodes, bipolar junction transistors (BJT), and metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor, MOS). Electro-Static Discharge (ESD) protection devices have absolute advantages. In addition, SCR also has a series of advantages in ESD protection such as low maintenance voltage, small on-resistance, low parasitic capacitance, and high peak power.

SCR is a four-layer structure power semiconductor device with three PN junctions, which is a semi-controlled current control device. Figure 1 is a schematic plan view of a structure of an SCR in the prior art, and Figure 2 is a schematic cross-sectional view of Figure 1 in the A-A direction. As shown in Figures 1 to 2, SCR mainly consists of a P-type substrate, a P+ region (anode) with a high doping concentration, an N-well extraction electrode (an N-type well region, generally with a low concentration), a high-doping concentration It is composed of N+ region (cathode) and P-well extraction electrode (P-type well region). Among them, P+/N-well, N-well/P-well, and P-well/N+ can form three PN junctions.

At present, depending on the operating point of the device, the trigger voltage of the SCR is generally set between 5V and 200V. After determining the operating point, the SCR trigger voltage is usually adjusted by adjusting the doping concentration of the N-type well region and P-type well region. However, due to the changes in the doping concentration of the N-type well region and P-type well region, it is inevitable It will affect other parameters of the SCR, such as holding current, holding voltage and parasitic capacitance. Therefore, although the trigger voltage can be adjusted in this way, it will also bring additional and undesirable adverse effects. Therefore, in the related art, one side of the PN junction (the side with lower concentration, that is, the side with the N-type well region) can be modified by adding a higher-concentration P-type compensation region (lp+ region) that is in direct contact with the N-type well region. The concentration of the P-type substrate side in contact is modulated so that its voltage can be adjusted within a wide range.

However, the lateral PNP transistor composed of the P+ region, the N-type well region and the P-type substrate region, that is, the base region width of the parasitic PNP transistor (the width of the N-type well region between the P+ region and the P-type substrate region , the width represented by w in Figure 1) is strictly limited by the overlay accuracy of the photolithography equipment. If the overlay accuracy of the photolithography equipment is low, the width of the N-type well region between the P+ region and the lp+ region will be too narrow. Or too wide, which can easily lead to lack of stability and poor consistency of SCR parameters.

Contents of the invention

In order to overcome the above defects, the present invention is proposed to provide a solution or at least a partial solution to the problem that the base width of the parasitic PNP transistor is strictly limited by the overlay accuracy of the photolithography equipment, which easily leads to the lack of stability and poor consistency of the SCR parameters. Technical issues of SCR and its manufacturing method.

In a first aspect, the present invention provides a silicon controlled rectifier SCR, which includes:

A first conductive type substrate;

A first conductivity type well region and a second conductivity type well region located in the first conductivity type substrate and spaced apart, wherein the second conductivity type well region has an extension portion toward the direction of the first conductivity type well region;

The first conductivity type compensation region extends from the first conductivity type well region toward the extension portion and is connected to the extension portion.

Further, in the above-mentioned silicon controlled rectifier, the first conductive type compensation area overlaps the extension part to form a first overlapping area.

Further, the silicon controlled rectifier described above also includes:

A second conductive type compensation region is disposed in a region of the extension portion close to the first overlapping region and in contact with the first overlapping region, wherein the doping concentration of the second conductive type compensation region is greater than the first overlapping region. Doping concentration of the extension.

Further, the silicon controlled rectifier described above also includes:

The doping concentration of the second conductive type compensation area is greater than the doping concentration of the extension part, and the first conductive type compensation area is connected to the extension part through the second conductive type compensation area.

Further, in the above-mentioned silicon controlled rectifier, the second conductivity type compensation area overlaps with the first conductivity type compensation area and the extension part respectively, forming a second overlapping area and a third intersection area respectively. overlapping area.

In a second aspect, the present invention provides a method for manufacturing SCR, including:

A first conductive type well region and a second conductive type well region are formed in the first conductive type substrate, wherein the first conductive type well region and the second conductive type well region are spaced apart, and the second conductive type well region is formed as having an extension in a direction toward the first conductivity type well region;

A first conductivity type compensation region is formed in the first conductivity type substrate, and the first conductivity type compensation region extends from the first conductivity type well region toward the extension portion and is connected to the extension portion.

Further, in the above-mentioned manufacturing method, forming the first conductive type compensation area includes:

The first conductive type compensation area is formed to overlap the extension part to form a first overlapping area.

Further, the above-mentioned manufacturing method also includes:

A second conductive type compensation area is formed in a region of the extension portion close to the first overlapping area, the second conductive type compensation area is in contact with the first overlapping area, and the second conductive type compensation area The doping concentration of the region is greater than the doping concentration of the extension.

Furthermore, in the manufacturing method described above,

The first conductive type compensation area is spaced apart from the extension;

The manufacturing method also includes:

A second conductivity type compensation area is formed in the first conductivity type substrate, the second conductivity type compensation area is connected to the first conductivity type compensation area and the extension part respectively, and the second conductivity type compensation area The doping concentration of the compensation region is greater than the doping concentration of the extension portion.

Further, in the above-mentioned manufacturing method, the second conductive type compensation area includes a second overlapping area overlapping the first conductive type compensation area and a third overlapping area overlapping the extension part. district.

One or more of the above technical solutions of the present invention have at least one or more of the following beneficial effects:

When implementing the technical solution of the present invention, an extension is provided in the direction of the second conductivity type well region toward the first conductivity type well region, and a first conductivity type compensation region connected to the extension is formed from the first conductivity type well region , compared with the prior art, the distance between the first conductivity type compensation region and the first conductivity type high doping concentration region in the second conductivity type well region is increased, so that when the first conductivity type compensation region is formed through an overlay process and is connected to the extension When the first conductivity type compensation area is used, even if the overlay accuracy of the photolithography equipment is not high, it will not affect the base area width of the transistor, preventing the first conductivity type high doping concentration area in the second conductivity type well area from being The width between the first conductive type compensation areas is unstable, thereby making the SCR parameters more stable and consistent. In addition, such a structure allows a greater degree of freedom in adjusting the concentration in the extended portion of the first conductivity type compensation region and the second conductivity type well region, thereby allowing the trigger voltage of the SCR to have a wider range.

Description of the drawings

The disclosure of the present invention will become more understandable with reference to the accompanying drawings. Those skilled in the art can easily understand that these drawings are for illustrative purposes only and are not intended to limit the scope of the present invention. Additionally, like numbers in the figures identify similar parts, where:

Figure 1 is a schematic plan view of a structure of SCR in the prior art;

Figure 2 is a schematic cross-sectional view of Figure 1 in the A-A direction;

Figure 3 is a schematic plan view of the SCR according to the first embodiment of the present invention;

Figure 4 is a schematic cross-sectional view of Figure 3 in the A1-A1 direction;

Figure 5 is a schematic plan view of an SCR according to a second embodiment of the present invention;

Figure 6 is a schematic cross-sectional view of Figure 5 in the A2-A2 direction;

Figure 7 is a schematic plan view of an SCR according to a third embodiment of the present invention;

Figure 8 is a schematic cross-sectional view of Figure 7 in the direction A3-A3.

Detailed ways

In order to make the above objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, the present invention can be implemented in many other ways different from those described here. Those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In addition, in the present invention, unless otherwise explicitly stipulated and limited, the terms "connected", "connected" and other terms should be understood in a broad sense. For example, it can be directly connected, or it can be indirectly connected through an intermediary, or it can be two The internal connection between two elements or the interaction between two elements, unless otherwise expressly limited. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

First embodiment

FIG. 3 is a schematic plan view of the SCR according to the first embodiment of the present invention, and FIG. 4 is a schematic cross-sectional view of FIG. 3 in the A1-A1 direction.

As shown in FIGS. 3 and 4 , the SCR in the embodiment of the present invention mainly includes a first conductivity type substrate 1 , a first conductivity type well region 2 , a second conductivity type well region 3 and a first conductivity type compensation region 4 .

Specifically, the first conductive type well region 2 and the second conductive type well region 3 are spaced apart in the first conductive type substrate 1 , and the second conductive type well region 3 has an extension portion toward the direction of the first conductive type well region 2 31.

The first conductivity type compensation region 4 extends from the first conductivity type well region 2 toward the extension portion 31 and is connected to the extension portion 31 , wherein the doping concentration of the first conductivity type compensation region 4 is greater than the doping concentration of the first conductivity type substrate 1 . impurity concentration.

In a specific example, the first conductive type well region 2 is provided with a first conductive type high doping concentration region 5 and a second conductive type high doping concentration region 6, and the second conductive type well region 3 is also provided with a first conductive type high doping concentration region 5. A conductive type high doping concentration region 5 and a second conductive type high doping concentration region 6 .

In the examples shown in FIGS. 3 and 4 , the first conductivity type is P type and the second conductivity type is N type. Those skilled in the art can understand that the first conductivity type may also be N-type, and the second conductivity type may be P-type, and the present invention is not limited thereto. In the following description, it is still assumed that the first conductivity type is P type and the second conductivity type is N type. In FIGS. 3 and 4 , the first conductive type substrate 1 can be represented as P-type substrate 1 , the first conductive type well region 2 can be represented as P-type well region 2 , and the second conductive type well region 3 can be represented as The N-type well region 3 and the first conductive type compensation region 4 can be represented as lp+ region 4, the first conductive type high doping concentration region 5 can be represented as P+ region 5, and the second conductive type high doping concentration region 6 can be represented as N+ region 6 will be described in the following embodiments using the above representation.

It should be noted that in the embodiment shown in FIGS. 3 to 4 , the aforementioned term “connected” means that the lp+ region 4 and the extension 31 are directly connected, such as contacting or overlapping. In this embodiment, the overlapping of the two is used as an example for description, that is, a part of the lp+ region 4 is located in the extension part 31 .

In the prior art, referring to Figures 1 and 2, since the lp+ region is in direct contact with the N-type well region, the spacing between the lp+ region and the P+ region located in the N-type well region, that is, the width of the base region of the parasitic PNP transistor is strictly Limited by the overlay accuracy of photolithography equipment. Different from the prior art solution, in the embodiment of the present invention, due to the existence of the extension 31, the lp+ region 4 contacts or overlaps with the extension 31, so that the lp+ region 4 can be relatively far away from the P+ in the N-type well region 3 Region 5, that is, the base region width of the parasitic PNP transistor only depends on the distance between the P+ region 5 in the N-type well region 3 and the boundary of the N-type well region 3 (excluding the extension region 31). In this way, when forming When the lp+ region 4 overlaps with the extension 31, even if the overlay accuracy of the photolithography equipment is not high, it will not affect the base width of the parasitic PNP transistor, thereby making the SCR parameters more stable and consistent. In addition, such a structure has a greater degree of freedom in adjusting the concentration of the lp+ region 4 and the concentration in the extension 31, so as to compensate (increase) the concentration of the P-type substrate where the PN junction is formed in the extension 31 , so that the trigger voltage of the SCR has a wider range.

Based on the above content, it is easy to understand that the length of the extension part 31 is as short as possible within the accuracy range of the lithography equipment. In this way, compared with the entire N-type well region 3, the area of the extension part 31 is very small. That is to say , the extension 31 only contributes a small area to the N-type well region 3, so it has no impact on the sustaining current and sustaining voltage of the SCR device, and the impact on parameters such as parasitic capacitance is also negligible.

In a specific implementation, the structure shown in Figures 3 to 4 can be manufactured according to the following process method:

S10. Form a P-type well region 2 and an N-type well region 3 in the P-type substrate 1 respectively, where the P-type well region 2 and the N-type well region 3 are spaced apart, and the N-type well region 3 faces the P-type well region 2 has an extension 31 in the direction.

In this step, conventional semiconductor processes such as photolithography and ion implantation can be used to form the P-type well region 2 and the N-type well region 3 with the extension 31 respectively. This application does not limit the specific process and formation sequence. For example, a photoresist mask layer may be first formed on the P-type substrate 1, and then the photoresist mask layer may be patterned to remove part of the photoresist mask layer, thereby forming a window for ion implantation; and then ion implantation may be performed. Implantation is performed to form a P-type well region 2 in the P-type substrate 1; for the N-type well region 3 having the extension 31, the above-mentioned process can also be used and will not be described again.

S12. Form P+ region 5 and N+ region 6 in P-type well region 2 and N-type well region 3 respectively;

In this step, conventional semiconductor processes such as photolithography and ion implantation can be used to form the P+ region 5 and the N+ region 6. This application does not specifically limit the specific process and the formation sequence of the P+ region 5 and the N+ region 6. For the specific process, reference can be made to the process of forming the P-type well region 2 , which will not be described again here. Among them, as shown in Figures 3 to 4, the P-type well region 2 is composed of P+ region 4 and N+ region 6 from left to right, and the N-type well region 3 is composed of N+ region 6 and P+ region from left to right. Zone 5.

S14. Form an lp+ region 4 extending from the P-type well region 2 toward the extension part 31 in the P-type substrate 1, and the lp+ region 4 overlaps with the extension part 31 to form a first overlapping region a.

Specifically, a photoresist mask layer can be first formed on the P-type substrate 1, and then the partial photoresist mask layer can be removed through patterning processing to form a window corresponding to the lp+ region 4; then boron ions are injected through the window to form lp+ area 4 overlapping extension 31 .

In this embodiment, by arranging the N-type well region 3 with the extension 31, the PN junction that adjusts the breakdown voltage is kept away from the P+ region 5 in the N-type well region 3. This not only reduces the requirements for the photolithography process , at the same time, the adjustment of the concentration of lp+ zone 4 will basically not affect other parameters of SCR, ensuring stable SCR performance and improving consistency.

Second embodiment

In the structure of the first embodiment, due to the low concentration of the N-type well region 3, even if the concentration of the lp+ region 4 side is simply increased, it is difficult to expect the SCR of this structure to have a lower trigger voltage. Therefore, in the first On the basis of the embodiments, the present invention provides a second embodiment, whose specific structure and manufacturing process are as follows:

In a specific implementation, in order to obtain an SCR with a lower trigger voltage, a second conductive type compensation region (hereinafter referred to as is the ln+ region), wherein the ln+ region overlaps the first overlapping region a, and the doping concentration of the ln+ region is greater than the doping concentration of the extension 31 . That is, the second embodiment is obtained based on the first embodiment (shown in FIGS. 3 and 4 ).

FIG. 5 is a schematic plan view of the SCR according to the second embodiment of the present invention, and FIG. 6 is a schematic cross-sectional view of FIG. 5 in the A2-A2 direction. As shown in Figures 5 and 6, the ln+ region overlaps the first overlapping region a to form a fourth overlapping region d.

The structure shown in Figures 5 to 6 can be manufactured according to the following process:

After steps S10 to S14, proceed to the following step S16:

S16. An ln+ region is formed in the extended portion 31 of the N-type well region 3 close to the first overlapping region a, where the ln+ region overlaps with the first overlapping region a to form a fourth overlapping region d.

Specifically, a photoresist mask layer can first be formed on the P-type substrate 1, and then a window corresponding to the ln+ region can be formed through patterning processing, and then ion implantation, such as phosphorus ions or arsenic ions, can be performed to form the ln+ region. And the ln+ region overlaps with the first overlapping region a to form a fourth overlapping region d.

In addition to the same benefits as the SCR in the first embodiment, the SCR provided by this embodiment is also provided in this embodiment by arranging an ln+ overlapping the lp+ region 4 in the extension 31 of the N-type well region 3 region, the doping concentration of the extension 31 can be increased, thereby reducing the breakdown voltage of the PN junction formed by the lp+ region 4 and the ln+ region, thereby reducing the trigger voltage of the SCR.

Third embodiment

FIG. 7 is a schematic plan view of an SCR according to a third embodiment of the present invention, and FIG. 8 is a schematic cross-sectional view of FIG. 7 in the A3-A3 direction.

As shown in FIGS. 7 to 8 , this embodiment is an alternative to the first embodiment ( FIGS. 3 to 4 ). The difference lies in that the lp+ region 4 and the extension 31 in the N-type well region 3 are spaced apart, that is, two are not directly connected, but connected through the ln+ area. Among them, the ln+ region overlaps with the lp+ region 4 and the extension 31 in the N-type well region 3 respectively, forming the second overlapping region b and the third overlapping region c respectively.

In one embodiment, the structure shown in Figures 7 to 8 can be implemented according to the following process method:

S30. Form a P-type well region 2 and an N-type well region 3 in the P-type substrate 1 respectively, where the P-type well region 2 and the N-type well region 3 are spaced apart, and the N-type well region 3 faces the P-type well region 2 has an extension 31 in the direction.

In this step, conventional semiconductor processes such as photolithography and ion implantation can be used to form the P-type well region 2 and the N-type well region 3 with the extension 31 respectively. This application does not specifically limit the specific process and formation sequence. For example, photolithography technology can be used to first form a photoresist mask layer on a P-type substrate, and then remove part of the photoresist mask layer through patterning processing to form a window for ion implantation, and then perform ion implantation on the P-type substrate. A P-type well region 2 is formed in the P-type substrate 1 . The N-type well region 3 having the extended portion 31 can also be formed according to the above process, which will not be described again.

S32. Form P+ region 5 and N+ region 6 in P-type well region 2 and N-type well region 3 respectively;

In this embodiment, the formation process and formation sequence of the P+ region 5 and the N+ region 6 are not particularly limited. They can be formed according to conventional techniques in the semiconductor field, and reference can also be made to the relevant content in the previous embodiments, which will not be described again here.

S34. Form an lp+ region 4 extending from the P-type well region 2 toward the extension portion 31 in the N-type well region 3 in the P-type substrate 2. The two regions are spaced apart.

Specifically, a photoresist mask layer can be formed on the P-type substrate 1 through photolithography technology, and then a partial photoresist mask layer can be removed through patterning processing to form a window corresponding to the lp+ region 4; and then injected through the window. Boron ions form the lp+ region 4 spaced apart from the extension 31 .

S36. Form an ln+ region that overlaps with the lp+ region 4 and the extension 31 in the N-type well region 3 respectively. The ln+ region includes a second overlapping region b that overlaps with the lp+ region 4 and an N-type well region. The third overlapping area c where the extending portion 31 in 3 overlaps.

Specifically, a photoresist mask layer can be formed on the P-type substrate 1, and then subjected to patterning processing to remove part of the photoresist mask layer to form a window for ion implantation, and then phosphorus ions or arsenic ions are injected through the window to form The ln+ area overlaps the lp+ area 4 and the extension 31 respectively.

In addition to having the same benefits as the first and second embodiments, the SCR provided by this embodiment also has the advantage that the ln+ region only needs to partially overlap with the N-type well region 3, and it is not necessary that the entire ln+ region be located in the N-type well region. Within the extension 31 of the well region 3, the line width requirements for the ln+ region are further reduced, which further reduces the processing difficulty of the photolithography process and the dependence on the overlay accuracy of the photolithography equipment, thereby making the SCR have higher consistency.

So far, the technical solution of the present invention has been described with reference to the preferred embodiments shown in the drawings. However, those skilled in the art can easily understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principles of the present invention, those skilled in the art can make equivalent changes or substitutions to relevant technical features, and technical solutions after these modifications or substitutions will fall within the protection scope of the present invention.

Claims (10)

1. A silicon controlled rectifier, characterized in that it includes: A first conductive type substrate; A first conductivity type well region and a second conductivity type well region located in the first conductivity type substrate and spaced apart, wherein the second conductivity type well region has a extension; A first conductivity type compensation region extends from the first conductivity type well region toward the extension portion and is connected to the extension portion. 2. The silicon controlled rectifier according to claim 1, wherein the first conductive type compensation area overlaps the extension part to form a first overlapping area. 3. The silicon controlled rectifier according to claim 2, further comprising: A second conductive type compensation region is disposed in a region of the extension portion close to the first overlapping region and in contact with the first overlapping region, wherein the doping concentration of the second conductive type compensation region is greater than the first overlapping region. Doping concentration of the extension. 4. The silicon controlled rectifier according to claim 1, further comprising: The second conductivity type compensation region has a doping concentration greater than that of the extension portion, and the first conductivity type compensation region is connected to the extension portion through the second conductivity type compensation region. 5. The silicon controlled rectifier according to claim 4, wherein the second conductivity type compensation area overlaps the first conductivity type compensation area and the extension portion respectively to form a second overlap. area and the third overlapping area. 6. A method of manufacturing a silicon controlled rectifier, characterized by comprising: A first conductive type well region and a second conductive type well region are formed in the first conductive type substrate, wherein the first conductive type well region and the second conductive type well region are spaced apart, and the second conductive type well region a region formed with an extension toward a direction of the first conductivity type well region; A first conductivity type compensation region is formed in the first conductivity type substrate, and the first conductivity type compensation region extends from the first conductivity type well region toward the extension portion and is connected to the extension portion. 7. The manufacturing method according to claim 6, wherein forming the first conductive type compensation region includes: The first conductive type compensation area is formed to overlap the extension part to form a first overlapping area. 8. The manufacturing method according to claim 7, characterized in that the method further comprises: A second conductive type compensation area is formed in a region of the extension portion close to the first overlapping area, the second conductive type compensation area is in contact with the first overlapping area, and the second conductive type compensation area The doping concentration of the region is greater than the doping concentration of the extension. 9. The manufacturing method according to claim 6, characterized in that, The first conductive type compensation area is spaced apart from the extension; The manufacturing method also includes: A second conductivity type compensation area is formed in the first conductivity type substrate, the second conductivity type compensation area is connected to the first conductivity type compensation area and the extension part respectively, and the second conductivity type compensation area The doping concentration of the compensation region is greater than the doping concentration of the extension portion. 10. The manufacturing method according to claim 9, characterized in that, The second conductive type compensation area includes a second overlapping area overlapping the first conductive type compensation area and a third overlapping area overlapping the extending portion.