CN117234425B

CN117234425B - Flash memory binding optimization method, device, equipment and storage medium

Info

Publication number: CN117234425B
Application number: CN202311300387.8A
Authority: CN
Inventors: 钟金; 陈向兵; 张辉; 张如宏; 胡来胜
Original assignee: Shenzhen Sandi Yixin Electronics Co ltd
Current assignee: Shenzhen Sandi Yixin Electronics Co ltd
Priority date: 2023-10-09
Filing date: 2023-10-09
Publication date: 2024-09-06
Anticipated expiration: 2043-10-09
Also published as: CN117234425A

Abstract

The application discloses a flash memory binding optimization method, a device, equipment and a storage medium. The method comprises the following steps: reading the required number of error correction bits per Plane before binding; binding a plurality of planes in the flash memory; reading the number of the required error correction bits of each Plane after binding, and calculating the change value of the number of the required error correction bits before and after binding of each Plane; the binding relation between the planes with the change value of the error correction bit number which is required before and after binding and is larger than or equal to the change threshold value and the rest planes is released; and establishing a logical partition based on the existing binding relationship. The application decides whether to bind or not through the change value of the required error correction bit number of planes before and after binding, can avoid the planes which do not meet the binding requirement from being brought into the binding relation, ensures that the flash memory produced by volume has stronger stability, can improve the storage safety and accuracy of data, and can also improve the use experience of the terminal user.

Description

Flash memory binding optimization method, device, equipment and storage medium

Technical Field

The present invention relates to the field of flash memory technologies, and in particular, to a method, an apparatus, a device, and a storage medium for binding and optimizing a flash memory.

Background

Flash memory (NANDFLASH, NF) is a storage medium for storing data, and is one type of Flash memory. The memory has the advantages of large capacity, high reading/writing speed and the like, and is popular with mass memory finished product manufacturers.

In order to enable the flash memory to have the function of storing data, a memory master control is mounted to perform mass production on the flash memory, and the mass production comprises a series of projects such as capacity calculation, pre-analysis, scanning and the like, wherein the scanning takes a lot of time due to the tasks such as full-disk reading/writing, data comparison, analysis and the like of the flash memory. In the related art, in order to solve the problem that the scanning consumes a lot of time, the read/write speed of the flash memory is increased by binding all planes in the flash memory, so as to accelerate the scanning process, but characteristic differences exist among different planes, if the binding is forced for increasing the read/write speed of data, the number of error correction bits required by planes before and after the binding may be obviously changed, and the stability of the flash memory is further affected.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a flash memory binding optimization method, device, equipment and storage medium, which can solve the problem that the number of error correction bits required by planes before and after binding is obviously changed and ensure the stability of a flash memory.

The first aspect of the present application provides a method for optimizing binding of flash memory, comprising:

reading the required number of error correction bits for each of said planes prior to binding;

binding a plurality of planes in the flash memory;

Reading the number of the required error correction bits of each Plane after binding, and calculating the change value of the number of the required error correction bits before and after each Plane binding;

releasing the binding relation between the planes, the change value of which is greater than or equal to the change threshold, of the error correction bit number before and after binding and the rest planes;

and establishing a logical partition based on the existing binding relationship.

In one possible implementation manner of the present application, after the binding relationship between the Plane and the rest of planes, in which the change value of the number of error correction bits required before and after binding is greater than or equal to the change threshold, is released, the method further includes:

If the number of the planes which are not bound is at least more than one, binding the planes which are not bound again, reading the number of the required error correction bits of each Plane after binding, calculating the change value of the number of the required error correction bits of the planes before and after binding, and releasing the binding relation between the planes which are not bound and the planes which are not bound until the change value of the number of the required error correction bits before and after binding is greater than or equal to the change threshold, and repeating the steps until the planes which are not bound.

In one possible embodiment of the present application, after the reading the number of required error correction bits for each of the planes before binding, the method further includes:

if the number of the error correction bits required by the current Plane is greater than a preset invalid threshold, marking the current Plane as an invalid Plane, wherein the invalid Plane does not carry out subsequent binding.

In one possible implementation manner of the present application, the unbinding the planes with the change value of the number of error correction bits required before and after the binding being greater than or equal to the change threshold value from the other planes includes:

releasing the binding relation between the planes with the change value of the error correction bit number which is required before and after binding and is larger than or equal to the change threshold value and the rest planes, or

And releasing the binding relation between the planes with the number of the error correction bits required after binding and the planes with the number of the error correction bits greater than or equal to the preset invalid threshold.

In one possible embodiment of the present application, the reading of the number of required error correction bits for each of the planes before binding or the number of required error correction bits for each of the planes after reading may be performed as follows:

selecting a predetermined number of blocks based on the current Plane;

Reading page templates in each of the blocks;

generating a required error correction bit number corresponding to each block according to bad column information of the page template;

the number of required error correction bits for which the maximum value is selected is determined as the number of required error correction bits for the current Plane.

A second aspect of the present application provides a flash binding optimization apparatus, including:

The reading module is used for reading the required error correction bit number of each Plane before binding;

the binding module is used for binding a plurality of planes in the flash memory;

The calculation module is used for reading the number of the error correction bits required by each Plane after binding and calculating the change value of the number of the error correction bits required before and after binding of each Plane;

the releasing module is used for releasing the binding relation between the planes, of which the change values of the error correction bit numbers required before and after binding are larger than or equal to the change threshold value, and the rest planes;

And the partition module is used for establishing a logical partition based on the existing binding relation.

In one possible embodiment of the present application, the method further includes:

And the advanced binding module is used for binding the remaining unbound planes again if the number of the remaining unbound planes is at least one, reading the required error correction bit number of each Plane after binding, calculating the change value of the required error correction bit number of the planes before and after binding, and releasing the binding relation between the planes, the change value of which is greater than or equal to the change threshold, and the remaining unbound planes, and repeating the steps until binding cannot be performed between the remaining unbound planes.

And the marking module is used for marking the current Plane as an invalid Plane if the number of the error correction bits required by the current Plane is larger than a preset invalid threshold, wherein the invalid Plane cannot be subjected to subsequent binding.

In one possible implementation manner of the present application, the releasing module is configured to release the binding relationship between the Plane and the rest of planes when the change value of the number of error correction bits required before and after binding is greater than or equal to the change threshold, where the releasing module includes:

In one possible embodiment of the present application, the calculation module includes:

a selecting unit configured to select a predetermined number of blocks based on the Plane at present;

a template reading unit for reading a page template in each of the blocks;

a generating unit, configured to generate a required error correction bit number corresponding to each block according to bad column information of the page template;

And the determining unit is used for selecting the maximum required error correction bit number as the current required error correction bit number of the Plane.

The technical scheme of the application comprises the following steps: reading the required number of error correction bits per Plane before binding; binding a plurality of planes in the flash memory; reading the number of the required error correction bits of each Plane after binding, and calculating the change value of the number of the required error correction bits before and after binding of each Plane; the binding relation between the planes with the change value of the error correction bit number which is required before and after binding and is larger than or equal to the change threshold value and the rest planes is released; and establishing a logical partition based on the existing binding relationship. Compared with the technical scheme of the related art, the method and the device for binding the planes not only force the binding of all planes for improving the reading/writing speed of data, but also determine whether the binding is carried out or not through the change value of the required error correction bit number of the planes before and after the binding, so that the planes which do not meet the binding requirement can be well prevented from being included in the binding relation, the stability of the flash memory produced in a large amount is higher, the storage safety and accuracy of the data can be greatly improved, and the use experience of a terminal user can be improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for optimizing binding of flash memory according to an embodiment of the application;

FIG. 2 is a flow chart of a method for optimizing binding of flash memory according to another embodiment of the present application;

FIG. 3 is a flow chart of a method for optimizing binding of flash memory according to another embodiment of the present application;

FIG. 4 is a schematic diagram of a flash binding optimization device according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a flash binding optimization device according to another embodiment of the present application;

FIG. 6 is a schematic diagram of a flash binding optimization device according to another embodiment of the present application;

FIG. 7 is a schematic diagram of an electronic device according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a flash memory according to an embodiment of the present application;

FIG. 9 is a diagram showing the variation of the highest number of error correction bits, the number of required error correction bits, of the bonding front and back planes 1,2, 3, 4 according to an embodiment of the present application;

FIG. 10 is a diagram showing the variation of the number of the highest error correction bits and the number of the required error correction bits of the planes 1, 4 before and after binding according to an embodiment of the present application.

Detailed Description

In order that the invention may be understood more fully, the invention will be described with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In the related art, in order to solve the problem that the scanning consumes a lot of time, the read/write speed of the flash memory is increased by binding all planes in the flash memory, so as to accelerate the scanning process, but characteristic differences exist among different planes, if the binding is forced for increasing the read/write speed of data, the number of error correction bits required by planes before and after the binding may be obviously changed, and the stability of the flash memory is further affected.

Therefore, in order to solve the technical problems, the application discloses a flash memory binding optimization method to solve the problem that the number of error correction bits required by planes before and after binding is obviously changed.

Before introducing the technical scheme of the application, a few related knowledge concepts of the flash memory are described.

As shown in fig. 8, the internal structure of the flash memory is divided into a DIE (DIE or LUN), a Plane, a Block (Block), and a Page (Page) in this order according to the hierarchy. The common flash memory on the market is typically a 1,2 or 4 Plane flash memory, each with its own independent CACHEREGISTER and PAGEREGISTER.

Redundancy area spark is a region of space for storing error correction codes, the length of which is typically configured with the highest number of error correction bits (i.e., 72 bits per 1-dry word can be configured, 72 bits/1K). The redundancy area spark is configured with the highest number of error correction bits, considering that the planes in the flash memory are bound to require that the redundancy area spark be the same length (i.e., the same number of error correction bits), and considering that the number of error bits that the planes actually will occur is exactly equal to the highest number of error correction bits, the redundancy area spark needs to be configured with the highest number of error correction bits.

The number of error correction bits required refers to the number of error correction bits actually required in the current storage area. For Plane in the flash memory, although the length of the redundant area spark of Plane is configured according to the highest value of 72 bits, the number of error bits actually occurring in Plane is not necessarily 72 bits, and may be 30 bits, 40 bits or 52 bits.

The technical scheme of the application is described in detail below with reference to the accompanying drawings.

Fig. 1 is a flow chart illustrating a flash binding optimization method according to an embodiment of the application.

Referring to fig. 1, a flash binding optimization method includes the following steps:

Step S110, the required error correction bit number of each Plane before binding is read.

For better understanding of the technical solution of the present embodiment, an explanation will be given with the case shown in fig. 9.

Fig. 9 shows a schematic diagram of the change of the number of error correction bits before and after binding of a plurality of planes in the flash memory, and as can be seen from fig. 9, the flash memory includes 4 planes, namely, plane1, plane2, plane3 and Plane4, and since the redundancy area spark of each Plane is configured according to 72 bits/1K, the 4 planes conform to the basic condition of binding.

Before binding the 4 planes, the required error correction bit number of each Plane is read, and the required error correction bit number before binding the planes is shown in table 1.

Plane number	Number of error correction bits required per 1 dry byte
		Plane1	30bit
Plane2	35bit
		Plane3	40bit
Plane4	60bit

TABLE 1

Step S120, binding a plurality of planes in the flash memory.

As can be seen from the foregoing, if binding is to be performed on several planes in the flash memory, it is required to ensure that the redundancy area spark in each Plane is the same in length, i.e. the highest error correction bit number corresponding to each Plane is the same, so that the binding operation on the planes can be performed. In an actual application scenario, when a manufacturer of a flash memory factory leaves the flash memory, the Data area Data and the redundant area spark of each Plane in the flash memory are all adjusted to be the same length, so that the binding basic condition of the planes is met.

The required number of error correction bits for plate 1, plate 2, plate 3 and plate 4 are shown in Table 2, respectively.

Plane number	Maximum error correction bit number per 1 dry byte
		Plane1	72bit
Plane2	72bit
		Plane3	72bit
Plane4	72bit

TABLE 2

Since the highest error correction bit numbers of the 4 planes are the same, the 4 planes conform to the basic condition of binding, and operations on the 4 planes can be performed, and after the 4 planes are bound, the Multi-Plane operation, which is a mode for improving the flash memory read/write speed, can be supported in the flash memory protocol.

Step S130, reading the number of the error correction bits required by each Plane after binding, and calculating the change value of the number of the error correction bits required before and after binding of each Plane.

After a binding operation is performed on several planes, 4 planes are bound to form a "whole" (the "whole" herein is not to be understood as forming a true "whole", the binding operation forms a "whole" on a logical level, and not a "whole" on a physical level, and the planes are still independent on a physical level), and because of the difference in sensitivity between planes before binding, the number of required error correction bits for each Plane after binding may vary to some extent, and thus it is necessary to ensure that the number of required error correction bits varies within an allowable controllable range due to the binding operation. For the above reasons, it is necessary to calculate the change value of the number of error correction bits required before and after each of the planes before and after binding, and select the planes whose number of error correction bits required after binding has changed significantly.

With reference to fig. 9, by calculation, the change values of the number of error correction bits required before and after each Plane binding are shown in table 3, and it should be noted that the change value of the number of error correction bits required before and after the current Plane binding = |number of error correction bits required before the current Plane binding-number of error correction bits required after the current Plane binding|.

TABLE 3 Table 3

And step 140, the binding relation between the planes with the change value of the error correction bit number which is required before and after the binding and the planes with the change value which is larger than or equal to the change threshold value and the rest planes is released.

After calculating the change value of the number of the required error correction bits before and after each Plane binding, planes with obvious change of the number of the required error correction bits before and after the binding are selected, the parameters are referenced through a pre-configured change threshold value, planes with the change value of the number of the required error correction bits before and after each Plane binding being greater than or equal to the change threshold value are determined as target planes, and the binding relation between the target planes and the rest planes is released. In this embodiment, the change threshold is set to 5 bits. It should be noted that, the change threshold value may be flexibly set according to the actual situation, and is not particularly limited, it is understood that the smaller the value of the change threshold value is set, the higher the requirement for the overall stability of the flash memory after binding is, and the setting of the basic condition of binding is also strict.

In connection with table 3, in the case described above, it was confirmed that the planes 1 and 4 were the target planes, and the number of error correction bits required after the binding of the planes 1 and 4 was too large, so that the planes 1 and 4 could not participate in the binding with the planes 2 and 3, and therefore, the binding relationship between the planes 1, 4 and the planes 2, 3 was removed.

This embodiment performs this step with the aim of two aspects:

1) Compared with the technical scheme of the related art, the embodiment does not force binding of a plurality of planes for improving the read/write speed of data only, so that the flash memory produced in quantity is higher in stability, the storage safety and accuracy of the data can be greatly improved, and meanwhile, the use experience of a terminal user can be improved.

2) For flash memory, there are not only types but also quality. The flash memory is derived from a wafer, and after the wafer is produced, the wafer is cut into a plurality of chips, the chip grade which can pass the factory test is defined as Good Die, and the chip grade which can not pass the factory test is defined as Inked Die. Both Good Die flash and Inked Die flash are in the market. For Good Die's flash memory, since the quality of the flash memory is high quality, even if the binding relation of planes corresponding to the error correction bit number change value greater than or equal to the change threshold is not released in the mass production stage, the influence on the overall stability of the flash memory is relatively low, but as the service time of the flash memory is prolonged, the oxide layer in the floating gate transistor in the flash memory is gradually aged, electrons get in and out of the floating gate transistor become easier, the charges stored in the floating gate transistor become easier to be abnormal, and the stability problem of the flash memory becomes worse. For Inked Die flash memories, since the quality of the flash memory is low, if the binding relation of planes corresponding to the error correction bit number change value greater than or equal to the change threshold is not released in the mass production stage, the problem of stability of the flash memory is only aggravated, and the phenomenon becomes more prominent after the service time of the flash memory reaches a certain time, so that the data written into the flash memory becomes quite unstable.

Therefore, based on the two reasons, the technical solution of the present embodiment can well avoid the problem, and select those planes that meet the binding precondition but do not meet the binding post-condition, and contact the binding relationship between the target planes and the rest planes, so as to ensure that the flash production is successful and the flash production is performed, and also maintain high stability to operate.

Step S150, establishing a logical partition based on the existing binding relation.

After the above steps, it is determined that the planes 2 and 3 are bound together and the logical partition is established for management, and the planes 1 and 4 are separately established for management, which is equivalent to the need to establish 3 logical partitions for management of the flash memory, such as the logical partition a for managing the planes 2 and 3, the logical partition B for managing the Plane1, and the logical partition C for managing the Plane4.

Fig. 2 is a flow chart of a flash binding optimization method according to another embodiment of the application.

Referring to fig. 2, a method for optimizing binding of flash memory includes the following steps:

step S210, the required error correction bit number of each Plane before binding is read.

Before binding the 4 planes, the number of required error correction bits for each Plane is read, and the number of required error correction bits before binding each Plane is shown in table 1 in step S110.

Step S220, binding a plurality of planes in the flash memory.

The required error correction bit numbers of the Plane1, plane2, plane3 and Plane4 are shown in table 2 in step S120, respectively.

Step S230, the number of the error correction bits required by each Plane after binding is read, and the change value of the number of the error correction bits required before and after binding of each Plane is calculated.

Referring to fig. 9, by calculation, the change value of the number of error correction bits required before and after each Plane binding is shown in table 3 in step S130, and it should be noted that the change value of the number of error correction bits required before and after the current Plane binding= |number of error correction bits required before the current Plane binding-number of error correction bits required after the binding|.

And step S240, the binding relation between the planes with the change value of the error correction bit number which is required before and after the binding and the planes with the change value which is larger than or equal to the change threshold value and the rest planes is released.

The purpose of this embodiment is to refer to steps 1) and 2) in step S140, and will not be described herein.

Step S250, if the number of the remaining unbound planes is at least more than one, binding the remaining unbound planes again, reading the required error correction bit number of each Plane after binding, calculating the change value of the required error correction bit number of the planes before and after binding, and releasing the binding relation between the planes with the required error correction bit number before and after binding and the remaining planes with the change value greater than or equal to the change threshold, and repeating the steps until binding cannot be performed between the remaining unbound planes.

Referring to fig. 10, in the foregoing case, after the binding relation between the Plane1 and the Plane4 and the Plane2 and the Plane3 is released, in order to further optimize the binding space, the binding possibility of the Plane1 and the Plane4 may be independently verified, the change values of the required error correction bit numbers before and after the binding may be calculated, and if the change values of the required error correction bit numbers after the binding are smaller than the change threshold, the two may be bound; otherwise, binding is not possible. It is verified that the Plane1 and the Plane4 are properly bound together (i.e., after the Plane1 and the Plane4 are bound, the change value of the number of error correction bits required before and after the binding is smaller than the change threshold).

It should be noted that, in the case of this embodiment, only 4 planes are listed for illustration, in the practical application process, the flash memory may include more than 5 planes (assuming 6 planes), if there are 4 planes that are unbundled from the binding relationship with the remaining 2 planes, it is further necessary to verify the possibility of binding the 4 planes, if it is determined that 2 of the 4 planes can be bound together, it is further necessary to verify the possibility of binding the last remaining 2 planes until binding cannot be performed between the remaining unbound planes. The reason for repeating this advanced binding step is that for flash memory, the writing and reading speed of data is critical, while performing Multi-Plane operations is the core critical to increasing the data read/write speed of flash memory, so it is desirable to shape Plane bindings in flash memory as much as possible into one "whole". Through the step, the proper binding of the planes can be verified as far as possible, the improper binding of the planes is not performed, the proper binding of the planes is performed, the improper binding of the planes is not performed, the reading/writing speed of the flash memory is ensured, and meanwhile the overall stability of the flash memory is ensured as far as possible.

Step S260, establishing a logical partition based on the existing binding relation.

After the above steps, it is determined that the Plane2 and the Plane3 are bound together, and the logical partition is established to manage, and the Plane1 and the Plane4 are bound together, and the logical partition is established to manage, which is equivalent to the need to establish 2 logical partitions to manage the flash memory, such as the logical partition a manages the Plane2 and the Plane3, and the logical partition B manages the Plane1 and the Plane4.

Whether the number of required error correction bits per Plane before the binding is read or the number of required error correction bits per Plane after the reading is determined as follows: selecting a predetermined number of blocks based on the current Plane; reading a page template in each block; generating a required error correction bit number corresponding to each block according to bad column information of the page template; the number of required error correction bits for which the maximum value is selected is determined as the number of required error correction bits for the current Plane.

The page templates are recorded with bad column information, and the required error correction bit number corresponding to the page templates can be obtained through the bad column information, and the maximum required error correction bit number in all the page templates is selected as the required error correction bit number of the current Plane. In this embodiment, the number of blocks in the current Plane is 8, and in the practical application process, the number of other blocks can be selected, and 8 is the best block number value after trial and error, and meanwhile, too many blocks are not selected, otherwise, the mass production efficiency is affected.

In addition, after the binding relationship is clear, a corresponding binding relationship code (MASK code) can be generated, and in the foregoing case, it is confirmed that Plane2 and Plane3 are bound together, and Planel and Plane4 are bound together. Based on the binding relation between the Plane2 and the Plane3, generating a binding relation code of "0110" corresponding to hexadecimal "0 x 06"; the binding relationship based on Plane1 and Plane4 is "1001", corresponding to hexadecimal "0 x 09". And storing the two binding relation codes into a management block for the flash memory, and then obtaining 0x06 and 0x09 by Lossc when the storage master control writes data into the flash memory, wherein the storage master control clearly shows that the Plane2 and the Plane3 have binding relation, and the Plane1 and the Plane4 have binding relation, and can simultaneously operate the Plane2 and the Plane3 to perform data writing tasks or simultaneously operate the Plane1 and the Plane4 to perform data writing tasks when the storage master control performs data writing tasks.

Fig. 3 is a flow chart illustrating a flash binding optimization method according to another embodiment of the application.

Referring to fig. 3, a method for optimizing binding of flash memory includes the following steps:

Step S310, the required error correction bit number of each Plane before binding is read.

The relevant content of step S310 is shown in step S210, and will not be described here again.

Step S320, if the number of the error correction bits required by the current Plane is greater than the preset invalid threshold, marking the current Plane as an invalid Plane, wherein the invalid Plane does not perform subsequent binding.

It should be noted that, the purpose of performing this pre-step is to screen the planes as first as possible before binding, and select those planes that are invalid, in this embodiment, since the number of required error correction bits of the current Plane is already beyond the highest number of error correction bits, if the data is written into the current Plane, a situation that the data cannot be corrected back will occur, resulting in a data error, so these planes should be marked as invalid directly, and any subsequent operations cannot be performed any more.

Step S330, binding a plurality of planes in the flash memory.

The relevant content of step S330 is described in step S220, and will not be described here again.

Step S340, the number of the error correction bits required by each Plane after binding is read, and the change value of the number of the error correction bits required before and after binding of each Plane is calculated.

The relevant content of step S340 is shown in step S230, and will not be described here again.

And step 350, the binding relation between the planes with the change value of the required error correction bit number greater than or equal to the change threshold before and after binding and the rest planes is released, or the binding relation between the planes with the required error correction bit number greater than or equal to the preset invalid threshold after binding and the rest planes is released.

In step S350, the reason and purpose of the condition of "the binding relationship between the Plane with the number of error correction bits required before and after binding is greater than or equal to the change threshold and the rest of planes is released" refer to step S240, and will not be repeated here.

It should be noted that, in step S350, compared with step S240, a condition is additionally added, that is, a Plane whose error correction bit number change value is greater than or equal to the change threshold value or a Plane whose error correction bit number after binding is greater than the highest error correction bit number is selected. The additional addition of the condition is to consider that the number of error correction bits required by the planes after binding exceeds the maximum number of error correction bits, and the problem that the data errors cannot be corrected back is also caused, so that the data security and the accuracy of the flash memory are caused.

And step S360, if the number of the remaining unbound planes is more than one, binding the remaining unbound planes again, reading the required error correction bit number of each Plane after binding, calculating the change value of the required error correction bit number of the planes before and after binding, and releasing the binding relation between the planes with the change value of the required error correction bit number before and after binding being greater than or equal to the change threshold and the remaining planes, and repeating the steps until the binding between the remaining unbound planes is impossible.

The relevant content of step S360 is referred to step S250, and will not be described herein.

Step S370, establishing a logical partition based on the existing binding relationship.

The relevant content of step S370 is described in step S260, and will not be described here again.

Corresponding to the method embodiment, the application discloses a flash memory binding optimization device and a corresponding embodiment.

Fig. 4 is a schematic structural diagram of a flash binding optimization device according to an embodiment of the application.

Referring to fig. 4, a flash binding optimization apparatus 400 includes: a reading module 410, a binding module 420, a computing module 430, a de-binding module 440, and a partitioning module 450. Wherein:

The reading module 41O is configured to read the number of error correction bits required for each Plane before binding;

The binding module 420 is used for binding a plurality of planes in the flash memory;

The calculating module 430 is configured to read the number of bits of the error correction bits required for each Plane after binding, and calculate a change value of the number of bits of the error correction bits required before and after binding for each Plane;

the unbinding module 440 is configured to unbind a Plane with a change value of the number of error correction bits required before and after binding being greater than or equal to a change threshold from the other planes;

partition module 450 is used to establish logical partitions based on existing binding relationships.

It should be noted that, the method for optimizing the binding of the flash memory implemented by the device for optimizing the binding of the flash memory disclosed in this embodiment is as described in the above embodiment, so that detailed description thereof will not be given here. Alternatively, each module in the present embodiment and the other operations or functions described above are respectively for realizing the method in the foregoing embodiment.

Fig. 5 is a schematic structural diagram of a flash binding optimization device according to another embodiment of the present application.

Referring to fig. 5, a flash binding optimization apparatus 400 includes: a read module 410, a binding module 420, a calculation module 430, a de-module 440, an advanced binding module 460, and a partition module 450. The functions of the reading module 410, the binding module 420, the calculating module 430, the releasing module 440, and the partitioning module 450 are described with reference to fig. 4, and are not repeated herein.

The advanced binding module 460 is configured to bind the remaining unbound planes again if the number of the remaining unbound planes is at least one, read the number of required error correction bits of each Plane after binding, calculate a change value of the number of required error correction bits of planes before and after binding, and release the binding relationship between planes with the number of required error correction bits before and after binding being greater than or equal to the change threshold and the remaining planes, and repeat the step until binding cannot be performed between the remaining unbound planes.

Fig. 6 is a schematic structural diagram of a flash binding optimization device according to another embodiment of the present application.

Referring to fig. 6, a flash binding optimization apparatus 400 includes: a reading module 410, a marking module 470, a binding module 420, a computing module 430, a de-binding module 440, an advanced binding module 460, and a partitioning module 450. The functions of the reading module 410, the binding module 420, the calculating module 430, the removing module 440, the advanced binding module 460 and the partitioning module 450 are described with reference to fig. 5, and are not described herein.

The marking module 470 is configured to mark the current Plane as an invalid Plane if the required number of error correction bits of the current Plane is greater than a preset invalid threshold, wherein the invalid Plane does not perform subsequent binding.

Further, in this embodiment, when the releasing module 440 is configured to release the binding relationship between the planes with the change value of the number of error correction bits required before and after binding being greater than or equal to the change threshold and the remaining planes, the releasing module includes:

and releasing the binding relation between the planes with the change value of the required error correction bit number greater than or equal to the change threshold before and after binding and the rest planes or releasing the binding relation between the planes with the required error correction bit number greater than or equal to the preset invalid threshold after binding and the rest planes.

Further, in the present embodiment, the computing module 430 includes a selecting unit 431, a template reading unit 432, a generating unit 433, and a determining unit 434. Wherein:

the selection unit 431 is used to select a predetermined number of blocks based on the current Plane.

The template reading unit 432 is for reading a page template in each block.

The generating unit 433 is configured to generate a required number of error correction bits corresponding to each block according to bad column information of the page template.

The determining unit 434 is configured to select the maximum number of required error correction bits as the number of required error correction bits for the current Plane.

Referring to FIG. 7, another embodiment of the application shows a computing electronic device 700 including a memory 710 and a processor 720.

Processor 720 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field programmable gate array (Field Programmable GATE ARRAY, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like.

A general purpose processor may be a microprocessor or the processor may be any conventional processor memory 710 that may include various types of storage elements, such as system memory, read Only Memory (ROM), and persistent storage.

Where the ROM may store static data or instructions that are required by the processor 720 or other modules of the computer. The persistent storage may be a readable and writable storage. The persistent storage may be a non-volatile memory device that does not lose stored instructions and data even after the computer is powered down. In some embodiments, the persistent storage device employs a mass storage device (e.g., magnetic or optical disk, flash memory) as the persistent storage device.

In other embodiments, the persistent storage may be a removable storage device (e.g., diskette, optical drive). The system memory may be a read-write memory device or a volatile read-write memory device, such as dynamic random access memory. The system memory may store instructions and data that are required by some or all of the processors at runtime.

Furthermore, memory 710 may include any combination of computer-readable storage media including various types of semiconductor memory chips (e.g., DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks, and/or optical disks may also be employed.

In some implementations, memory 710 may include readable and/or writable removable storage devices such as Compact Discs (CDs), digital versatile discs (e.g., DVD-ROMs, dual layer DVD-ROMs), blu-ray discs read only, super-density discs, flash memory cards (e.g., SD cards, min SD cards, micro-SD cards, etc.), magnetic floppy disks, and the like. The computer readable storage medium does not contain a carrier wave or an instantaneous electronic signal transmitted by wireless or wired transmission. The memory 710 has stored thereon executable code that, when processed by the processor 720, can cause the processor 720 to perform some or all of the methods described above.

Furthermore, the method according to the application may also be implemented as a computer program or computer program product comprising computer program code instructions for performing part or all of the steps of the above-described method of the application.

Or the application may also be embodied as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) having stored thereon executable code (or a computer program or computer instruction code) which, when executed by a processor of an electronic device (or server, etc.), causes the processor to perform some or all of the steps of the above-described method according to the application.

The foregoing description of embodiments of the application has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. The flash memory binding optimization method is characterized by comprising the following steps of:

reading the required number of error correction bits per Plane before binding;

Binding a plurality of planes in the flash memory;

2. The method for optimizing flash binding according to claim 1, wherein after the binding relation between the Plane and the rest of the planes, in which the change value of the number of error correction bits required before and after binding is greater than or equal to the change threshold, is released, further comprising:

3. The method of claim 1, further comprising, after said reading the number of required error correction bits for each of said planes prior to binding:

4. The method for optimizing flash binding according to claim 3, wherein said releasing the binding relation between the Plane and the rest of the planes, in which the change value of the number of error correction bits required before and after binding is greater than or equal to the change threshold, comprises:

5. The method according to any one of claims 1 to 4, wherein the reading of the number of the required error correction bits for each of the planes before binding or the number of the required error correction bits for each of the planes after reading is performed as follows:

selecting a predetermined number of blocks based on the current Plane;

Reading page templates in each of the blocks;

6. A flash binding optimization apparatus, comprising:

7. The flash binding optimization apparatus of claim 6, further comprising:

8. The flash binding optimization apparatus of claim 6, further comprising:

9. The flash binding optimization apparatus according to claim 8, wherein the unbinding module is configured to unbinding the planes having the change value of the number of error correction bits required before and after binding greater than or equal to a change threshold from the remaining planes, and comprises:

10. The flash binding optimization apparatus according to any one of claims 6 to 9, wherein the computing module includes:

a template reading unit for reading a page template in each of the blocks;