CN117174726B - Semiconductor substrate, preparation method and image sensor - Google Patents

Abstract

The application discloses a semiconductor substrate, a preparation method and an image sensor. The semiconductor substrate of the present application includes: a substrate having a first surface; a trapping layer located on a side of the substrate remote from the first surface, the trapping layer being for trapping metal ions from or through the substrate; and the back sealing layer is positioned on one side of the capture layer away from the substrate. The application improves the external gettering capability of the semiconductor substrate by arranging the trapping layer on one side of the substrate of the semiconductor substrate. The semiconductor substrate provided by the application is used as a matrix of the image sensor, so that the dark current and the white pixel number of the image sensor are reduced.

Description

Semiconductor substrate, preparation method and image sensor

Technical Field

The present application relates to the field of semiconductor technology, and in particular to a substrate, an image sensor and a method for preparing the same.

Background Art

Semiconductor substrates are the basic materials used to manufacture semiconductor devices. Silicon substrates have good electrical properties, thermal stability and processability and are commonly used semiconductor substrate materials. The quality of silicon substrates is crucial to the performance and manufacturing of semiconductor devices.

Summary of the invention

The purpose of this application is to provide a semiconductor substrate, a preparation method and an image sensor, which can solve the above-mentioned technical problems.

The present application provides a semiconductor substrate, including:

a substrate having a first surface;

a capture layer, the capture layer being located on a side of the substrate away from the first surface;

A backing layer is located on a side of the capture layer away from the substrate.

In some embodiments, the capture layer is used to capture metal ions, including metal ions in the substrate and metal ions that pass through the first surface and enter the substrate.

In some embodiments, the capture layer has a thickness of

In some embodiments, the resistivity of the substrate is 0.010 ohm-cm to 0.020 ohm-cm.

Accordingly, an embodiment of the present application provides a method for preparing a semiconductor substrate, comprising:

providing a substrate having a first surface;

forming a capture layer, wherein the capture layer is located on a side of the substrate away from the first surface;

A backing layer is formed, and the backing layer is located on a side of the capture layer away from the substrate.

In some embodiments, along the thickness direction of the substrate, the capture layer has a thickness of

In some embodiments, the step of forming the capture layer comprises:

A second polysilicon layer is formed, wherein the second polysilicon layer is located on the first surface; a first polysilicon layer is formed, wherein the substrate has a second surface which is away from the first surface, and the second polysilicon layer is located on the second surface; the second polysilicon layer is removed, and the first polysilicon layer is retained; the first polysilicon layer serves as the capture layer.

In some embodiments, the first polysilicon layer and/or the second polysilicon layer are prepared by the following method: using silicon-containing gas to deposit a polysilicon layer on the surface of the substrate; the consumption of the silicon-containing gas is

In some embodiments, in the step of forming the first polysilicon layer, the substrate is placed in an environment with a temperature range of 600°C to 660°C; and/or, in the step of forming the second polysilicon layer, the substrate is placed in an environment with a temperature range of 600°C to 660°C.

In some embodiments, the second polysilicon layer is removed by a chemical mechanical polishing method, and the chemical mechanical polishing method includes: grinding the second polysilicon layer to remove the second polysilicon layer.

In some embodiments, the first substrate is adsorbed on a polishing head having a chamber. Along the thickness direction of the semiconductor substrate, the chamber has a first thickness H ₁ μm. The first substrate has a second thickness H ₂ μm, satisfying: 0＜H ₁ -H ₂ ≤20 μm.

Accordingly, an embodiment of the present application provides an image sensor, which includes the above-mentioned semiconductor substrate; or, the image sensor includes a semiconductor substrate prepared by the above-mentioned semiconductor substrate preparation method; the semiconductor substrate serves as a base of the image sensor.

In some embodiments, the semiconductor substrate includes a P-type substrate.

The beneficial effect of the present application is that compared with the prior art, the present application provides a semiconductor substrate, a preparation method and an image sensor. The semiconductor substrate of the present application includes: a substrate having a first surface; a capture layer, the capture layer is located on the side of the substrate away from the first surface, and the capture layer is used to capture metal ions from the substrate or capture metal ions passing through the substrate; a back-sealing layer, the back-sealing layer is located on the side of the capture layer away from the substrate. The present application improves the external impurity absorption ability of the semiconductor substrate by setting a capture layer on the base side of the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

FIG1 is a flowchart of a manufacturing process of a semiconductor substrate in an embodiment of the present application;

FIG2 is a flowchart of a manufacturing process of a semiconductor substrate in an embodiment of the present application;

FIG3 is a flowchart of a manufacturing process of a semiconductor substrate in an embodiment of the present application;

FIG4 is a schematic diagram of the structure of a semiconductor substrate in an embodiment of the present application;

FIG5 is a schematic diagram of the structure of an image sensor in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of a grinding disc and a semiconductor substrate in an embodiment of the present application;

FIG7 is a geometric flatness test result of a semiconductor substrate prepared in an embodiment of the present application, wherein FIGA is a maximum local flatness SFQR test result; FIGB is a maximum edge flatness ESFQR test result; FIGC is a maximum local flatness mean result; FIGD is a maximum edge flatness mean result; and FIGE is a maximum local flatness test result of 95% distribution quantity;

FIG8 is a schematic diagram of the structure of an image sensor prepared in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of a front-illuminated image sensor in an embodiment of the present application;

FIG10 is a dark current test result of a semiconductor substrate applied to an image sensor in an embodiment of the present application;

FIG11 is a white pixel detection result of a semiconductor substrate applied to an image sensor in an embodiment of the present application;

In the figure, 1-semiconductor substrate, 100-base, 101-first surface, 102-second surface, 110-first substrate, 200-capture layer, 210-first polysilicon layer, 220-second polysilicon layer, 300 back sealing layer; 2-grinding disk, 3-polishing head, 300-chamber, 301-bottom surface.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms first, second, third, etc. are used only as labels, and no numerical requirements or order are imposed. Various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a hard limit to the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the numbered range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. In addition, whenever a numerical range is indicated herein, it is intended to include any cited numeral (fraction or integer) within the indicated range. In the present application, the X direction is the thickness direction, and the Y direction is the extending direction of the semiconductor substrate.

As shown in FIG4 , an embodiment of the present application provides a semiconductor substrate, comprising: a substrate 100, the substrate 100 having a first surface 101; a capture layer 200, the capture layer 200 is located on a side of the substrate 100 away from the first surface 101, and the capture layer 200 is used to capture metal ions from the substrate 100 or capture metal ions passing through the substrate 100; and a backing layer 300, the backing layer 300 is located on a side of the capture layer 200 away from the substrate 100. The present application sets the capture layer 200 on one side of the substrate 100 to enhance the external impurity absorption capability of the semiconductor substrate, effectively reduce metal ion contamination, and improve the finished product yield of the product.

In some embodiments, the capture layer 200 has a thickness of For example, the thickness of the capture layer 200 The value of is any value among 1000, 2000, 3000, 4000, 5000, 6000, 7000, 8000 or a range consisting of any two values. For example, the thickness of the capture layer 200 is or, In the present application, since the provision of the capture layer 200 will deteriorate the geometric flatness of the substrate, the thickness of the capture layer 200 of the present application is Within the range, the external doping function of the semiconductor substrate of the present application is satisfied, and the degree of degradation of the device flatness caused by the setting of the capture layer 200 can be improved.

In some embodiments, the substrate 100 is a silicon substrate, and the resistivity of the substrate 100 is 0.010 ohm-cm to 0.020 ohm-cm. For example, the resistivity (ohm-cm) of the substrate 100 is any value among 0.01, 0.011, 0.012, 0.013, 0.014, 0.015, 0.016, 0.017, 0.018, 0.019, 0.020, or a range consisting of any two values.

In some embodiments, the resistivity of the substrate 100 is changed by the following methods, such as ion doping the silicon substrate, which may be done by ion implantation. Alternatively, during the preparation of the silicon substrate, doping elements of different concentrations are added to the silicon material to change the resistivity of the substrate 100.

In some embodiments, the capture layer 200 includes polysilicon, which is used as a gettering material to capture metal ions from the epitaxial layer. When the semiconductor substrate of the present application is used in a device, it can capture metal ions in the device layer and reduce the dark current and the number of white pixels of the device.

In some embodiments, the back sealing layer 300 is a silicon oxide layer, and the thickness of the back sealing layer 300 is For example, the thickness of the back cover layer 300 It is any value among 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, or a range consisting of any two values.

In some embodiments, the backing layer 300 includes low temperature silicon oxide (LTO).

In some embodiments, the temperature of low temperature silicon oxide deposition is 400°C to 800°C, such as the deposition temperature (°C) is any value of 400, 450, 500, 550, 600, 650, 700, 750, 800 or a range consisting of any two values. In some embodiments, the preparation temperature of the backing layer 300 is 600-650°C.

In some embodiments, the backing layer 300 is prepared by the following method: the substrate 100 having the capture layer 200 is subjected to chemical vapor deposition to prepare the backing layer 300. In some embodiments, the flow rate of oxygen (Standard Cubic Centimeters per Minute, sccm) ranges from 495 to 616. In some embodiments, the flow rate of _SiH4 (Standard Cubic Centimeters per Minute, sccm) ranges from 45 to 56.

In some embodiments, the present application provides a method for preparing a semiconductor substrate, comprising:

As shown in FIG1 , a substrate 100 is provided, and the substrate 100 has a first surface 101 ;

A capture layer 200 is formed, and the capture layer 200 is located on a side of the substrate 100 away from the first surface 101 ; a backing layer 300 is formed, and the backing layer 300 is located on a side of the capture layer 200 away from the substrate 100 .

In some embodiments, along the thickness direction X of the substrate, the capture layer 200 has a thickness of

As shown in FIG. 2 , the steps of forming the capture layer 200 include:

forming a second polysilicon layer 220 , wherein the second polysilicon layer 220 is located on the first surface 101 ;

A first polysilicon layer 210 is formed, the substrate 100 has a second surface 102 away from the first surface 101, and a second polysilicon layer 220 is located on the second surface 102;

As shown in FIG. 3 , the second polysilicon layer 220 is removed, and the first polysilicon layer 210 is retained; the first polysilicon layer 210 serves as the capture layer 200 .

In some embodiments, the first polysilicon layer 210 is prepared by the following method: using a silicon-containing gas to deposit the first polysilicon layer 210 on the surface of the substrate 100; the consumption of the silicon-containing gas is Such as the consumption of silicon-containing gas The value of is any value among 2.0, 2.5, 3.0, 3.5, 4.0 or a range consisting of any two values. The present application can control the thickness of the first polysilicon layer 210 and the deposition speed of the first polysilicon layer 210 on the surface of the substrate 100 by controlling the consumption of the silicon-containing gas, and can reduce the influence of the preparation of the polysilicon layer on the flatness of the semiconductor substrate 1.

In some embodiments, the second polysilicon layer 220 is prepared by the following method: using a silicon-containing gas to deposit the second polysilicon layer 220 on the surface of the substrate 100; the consumption of the silicon-containing gas is Such as the consumption of silicon-containing gas The value of is any value among 2.0, 2.5, 3.0, 3.5, 4.0 or a range consisting of any two values. The present application can control the thickness of the second polysilicon layer 220 and the deposition speed of the second polysilicon layer 220 on the surface of the substrate 100 by controlling the consumption of the silicon-containing gas, thereby improving the quality of the semiconductor substrate.

In some embodiments, during the step of forming the first polysilicon layer 210 , the substrate 100 is placed in an environment with a temperature ranging from 600° C. to 660° C.

In some embodiments, during the step of forming the second polysilicon layer 220 , the substrate 100 is placed in an environment with a temperature ranging from 600° C. to 660° C.

In some embodiments, the temperature (° C.) for forming the first polysilicon layer 210 is any value among 600, 610, 620, 630, 6405, 650, 660, or a range consisting of any two values.

In some embodiments, the temperature (° C.) for forming the second polysilicon layer 220 is any value among 600, 610, 620, 630, 6405, 650, 660, or a range consisting of any two values.

In some embodiments, polysilicon layers are formed on both sides of the substrate 100 at the same time, that is, a first polysilicon layer 210 and a second polysilicon layer 220 are formed on both sides of the substrate 100 at the same time, to obtain a first substrate 110. The first polysilicon layer 210 and the second polysilicon layer 220 are formed at a temperature range of 600°C to 620°C, or a temperature range of 640°C to 660°C.

When the thickness of the prepared polysilicon layer It can be prepared by the following method:

In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are prepared by: a first temperature range of 600° C. to 620° C., a silicon-containing gas at a first flow rate of The polysilicon layer is prepared under the conditions of.

In some embodiments, the second temperature range is 640° C. to 660° C., and the silicon-containing gas at the second flow rate is The polysilicon layer is prepared under the conditions of.

When the thickness of the prepared polysilicon layer is greater than It can be prepared by the following method:

In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are prepared by: the first temperature range is 600° C. to 620° C., the silicon-containing gas is heated at a third flow rate of The polysilicon layer is prepared under the conditions of.

In some embodiments, the second temperature range is 640° C. to 660° C., and the silicon-containing gas is at a fourth flow rate of The polysilicon layer is prepared under the conditions of.

In some embodiments, the silicon-containing gas includes SiH ₄ .

In some embodiments, the second polysilicon layer 220 is removed by a chemical mechanical polishing method.

As shown in FIG6 , the device for performing the chemical mechanical polishing method includes a grinding disc 2 and a polishing head 3. The polishing head 3 has a chamber 300. During chemical mechanical polishing, the surface of the semiconductor substrate is adsorbed by a pressurized air bag through an intermediate air pipe, that is, the first substrate 110 is closely attached to the polishing head 3 above by vacuum adsorption, and the delivery pipeline delivers a grinding liquid including a corrosive liquid and abrasive particles. The second polysilicon layer 220 is removed by the high-speed rotation of the polishing head 3.

In some embodiments, along the thickness direction (X direction) of the semiconductor substrate 1, the chamber 300 has a first thickness _H1 μm, and the base has a second thickness _H2 μm, satisfying: 0＜ _H1 - _H2≤20μm . For example, the value of _H1 - _H2 is any value among 5, 10, 15, 20 or a range consisting of any two values. For example, _5≤H1 - _H2≤15 , or _5≤H1 - _H2≤10 , or _10≤H1 - _H2≤15 .

In some embodiments, the distance between _H1 - _H2 refers to the distance Sμm between the bottom surface 301 of the polishing head 3 and the top surface of the first substrate 110. In the present application, the bottom surface or the top surface is described in relative directions and does not limit the specific structure of the present application.

In some embodiments, the distance S between the bottom surface 301 of the polishing head 3 and the top surface of the first substrate 110 satisfies: 0＜S≤20μm. For example, the value of S is any value among 5, 10, 15, 20 or a range consisting of any two values.

In some embodiments, the first thickness _H1 of the chamber 300 is 780 μm to 790 μm, for example, the first thickness _H1 is any value among 780, 785, 790 or a range consisting of any two values.

In some embodiments, the second thickness H ₂ of the first substrate 110 is 765 μm to 785 μm _, such as any value of 765, 770, 775, 780, 785 or a range consisting of any two values.

When H ₁ -H ₂ of the present application is greater than 20 μm, for example, the height of the chamber 300 is 800 μm, the thickness of the first substrate 110 is 775 μm, and the thickness of the prepared polysilicon layer is Within the range of , a geometric flatness test was performed on the obtained substrate, and it was found that the geometric flatness of the substrate was poor. When the distance between the lower surface of the chamber 300 and the first substrate 110 was reduced, the influence of the polycrystalline silicon layer prepared in the present application on the deterioration of the geometric flatness of the substrate could be improved.

In some embodiments, the geometric flatness of the semiconductor substrate 1 in the present application can be characterized by maximum local flatness and maximum edge flatness.

In some embodiments, an optical microscope, a scanning electron microscope (SEM), or an atomic force microscope (AFM) is used as a flatness testing instrument in the present application.

As shown in FIG. 5 and FIG. 7 , an embodiment of the present application provides an image sensor (CIS, CMOS Image Sensor), which includes the above-mentioned semiconductor substrate 1, and the semiconductor substrate 1 serves as a base of the image sensor, wherein a device layer 400 is provided in the epitaxial layer of the semiconductor substrate 1.

As shown in FIG7 , in some embodiments, the semiconductor substrate of the present application is a P-type substrate, and the image sensor includes an NMOS transistor structure and a PMOS transistor structure. The image sensor shown in FIG7 of the present application is only used as an example structure, and the semiconductor substrate 1 of the present application can also be an N-type substrate, and the image sensor can be a front-illuminated image sensor or a back-illuminated image sensor.

In some embodiments, as shown in FIG8 , the present application provides a schematic diagram of the structure of a front-illuminated sensor, wherein the image sensor includes a sensor body, a color filter 500 and a lens 600. The sensor body includes a substrate and a CMOS device structure, namely, a device layer 400, disposed on the substrate.

In some embodiments, the color filter 500 is used to capture light of different colors, and the following types of color filters can be selected: Bayer filter, X-Trans filter, etc.

In some embodiments, the lens 600 is used to focus the light and direct it onto the sensor, and the following types of lenses may be selected: such as a plano-convex lens, a bi-convex lens, etc.

In some embodiments, the semiconductor substrate prepared in the above embodiments of the present application is applied to an image sensor, which can improve the leakage caused by excessive metal ions in the device, which will affect the dark current and the number of white pixels generated under different operating temperature conditions.

In some embodiments, the average number of dark current pixels (pixels) of an image sensor using the semiconductor substrate 1 of the present application ranges from 16.3 to 16.6.

In some embodiments, the number of white pixels (pixels) of an image sensor using the semiconductor substrate 1 of the present application ranges from 200 to 250.

Embodiment 1:

Semiconductor substrate: A P-type single crystal silicon polished wafer with a diameter of 300 mm is selected as the substrate 100, with a resistivity of 0.010-0.020 ohm-cm and a total thickness _H2 of 775 μm before epitaxy.

A LPCVD furnace is selected to process the substrate 100, the purity of the silicon-containing gas _SiH4 is selected to be above 99.9999%, and the purity of _N2 is selected to be above 99.9999999%. The LPCVD furnace is used for polysilicon deposition, and the same single crystal silicon material is selected for processing to prepare a polysilicon layer. The preparation process is shown in Table 1.

Removing the second polysilicon layer 220: Along the thickness direction X of the substrate, the polishing head 3 has a grinding chamber 300, and the chamber 300 has a first thickness _H1 of 780 μm.

Preparation of back seal layer 300: Use APCVD furnace to process substrate 100, select silicon-containing gas SiH ₄ with a purity of more than 99.9999%, O ₂ with a purity of more than 99.9999999%, and N ₂ with a purity of more than 99.9999999%, use APCVD furnace to deposit low-temperature oxide layer, the deposition temperature range is 640-650°C, and select the same single crystal silicon material for processing to prepare oxide layer back seal film thickness A semiconductor substrate as shown in FIG. 4 is obtained.

Example 2 to Example 12: The preparation method is the same as that of Example 1, except that the preparation parameters of the polysilicon layer are adjusted, as shown in Table 1 for details.

Comparative Example 1: No capture layer 200 was prepared.

Table 1 Preparation process parameters of semiconductor substrate

The geometric flatness of Example 5 (5k), Example 7 (4k), Example 8 (3k), Example 10 (2k), Example 11 (1K), and Comparative Example 1 (BSL) were tested, and the test results are shown in Table 2 and Figure 7.

Table 2 Test results of semiconductor substrate geometric flatness

Maximum local flatness (SFQR Max/nm) Maximum edge flatness (ESFQR Max/nm) Example 5 182.583 182.684 Example 7 154.735 128.798 Example 8 106.021 118.025 Example 10 61.277 56.463 Embodiment 11 43.985 35.909 Comparative Example 1 58.507 55.889

From the results in Table 2 and FIG. 2 , it can be seen that the thickness of the capture layer 200 prepared in the present application is In the range of , the deterioration of the geometric flatness of the semiconductor substrate 1 is improved compared with the comparative example 1 in which the capture layer 200 is not deposited. In addition, after the CMP method is improved in the present application, the thickness of the prepared capture layer 200 is The degree of geometric flatness degradation within the range is suppressed. The capture layer thickness range prepared in this application is The maximum local flatness (nm) ranges from 130nm to 250nm, and the capture layer thickness prepared in this application ranges from The maximum edge flatness (μm) ranges from 130nm to 250nm.

It can also be seen from Figure 2 that the mean value of the maximum local flatness (SFQR Mean/nm) and the mean value of the maximum edge flatness (ESFQR Mean/nm) of the capture layer 200 of the present application are consistent with the trend of the maximum local flatness and the maximum edge flatness, indicating that the preparation of the capture layer 200 of the present application improves the deterioration of the flatness of the semiconductor substrate 1.

Application examples:

The semiconductor substrate 1 prepared in Example 2 (Poly+LTO 8k+3k), Example 5 (Poly+LTO 5k+3k), Example 8 (Poly+LTO 3k+3k) and Comparative Example 1 (POR) was applied to an image sensor (CMOS).

The image sensor is prepared by the following method:

A circuit structure including NMOS and PMOS as shown in FIG. 8 is formed on a semiconductor substrate 1 by using an ion implantation method.

Preparation of gate: A gate electrode is formed on a semiconductor substrate 1 using polysilicon to control the flow of current.

Oxide layer formation: Silicon dioxide is formed on the semiconductor substrate 1 as an oxide layer for isolating and protecting the circuit.

Metal deposition: Copper metal is deposited on the oxide layer to form electrodes and connecting lines.

Photolithography and etching: Use photolithography to define the shape and structure of the circuit on the oxide layer. Then, etching is used to remove excess material to form the desired circuit structure.

Dielectric layer formation: A dielectric layer is formed between metal electrodes and connecting lines to isolate and protect the circuit.

Metal Fill: Filling metal on the dielectric layer to form the top of the electrodes and connecting lines.

Packaging and testing: After the image sensor is prepared, packaging and testing are carried out. The sensor body is encapsulated in the packaging material and the electrical performance test and image quality test are carried out.

Test Method:

Dark current: Dark current image sensor (Dark Current Imaging) is used to detect dark current.

White pixel: dark field test method.

Table 2 Test results of the semiconductor substrate prepared in this application used in a front-illuminated image sensor

Average dark current pixel number (pixel) Number of white pixels (pixel) Example 2 16.3～16.6 200～250 Example 5 16.3～16.6 200～250 Example 8 16.3～16.6 200～250 Comparative Example 1 16.6～17.0 600～900

From the data in Figure 10 (D-Mean in Figure 10 represents the test data of dark current), Figure 11 (Peak02 in Figure 11 represents the test data of white pixels) and Table 3, it can be seen that the verification results of the semiconductor substrate 1 prepared by the present application in the device show that the image sensor with a back polysilicon layer (green, blue and orange lines) has a significant improvement trend compared with the semiconductor substrate without a back polysilicon layer (red line), and the dark current and white pixels have been greatly reduced and tightened, proving that the leakage phenomenon caused by metal ion contamination generated during the processing can be better controlled by using the semiconductor substrate with a back polysilicon layer prepared by the present application. The present application can effectively improve the dark current and white pixels of CIS products, thereby improving the quality of CIS chip devices.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

The semiconductor substrate, preparation method and image sensor provided in the embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (10)

1. A semiconductor substrate, comprising: A substrate (100), wherein the substrate (100) has a first surface (101); A capture layer (200), the capture layer (200) being located on a side of the substrate (100) away from the first surface (101); A back-sealing layer (300), the back-sealing layer (300) being located on a side of the capture layer (200) away from the substrate (100); Along the thickness direction (X) of the substrate (100), the thickness of the capture layer (200) is The thickness of the back cover layer (300) is ; Wherein, the step of forming the back cover layer (300) comprises: The substrate (100) having the capture layer (200) is placed in an environment with a temperature range of 600° C. to 650° C. to form a backing layer (300), wherein the backing layer (300) is located on a side of the capture layer (200) away from the substrate (100). 2. The semiconductor substrate according to claim 1, characterized in that the resistivity of the base (100) is 0.010 ohm-cm to 0.020 ohm-cm. 3. A method for preparing a semiconductor substrate, characterized in that it comprises: Providing a substrate (100), wherein the substrate (100) has a first surface (101); forming a capture layer (200), wherein the capture layer (200) is located on a side of the substrate (100) away from the first surface (101); forming a back-sealing layer (300), wherein the back-sealing layer (300) is located on a side of the capture layer (200) away from the substrate (100); Along the thickness direction (X) of the substrate (100), the thickness of the capture layer (200) is The thickness of the back cover layer (300) is ; Wherein, the step of forming the back cover layer (300) comprises: The substrate (100) having the capture layer (200) is placed in an environment with a temperature range of 600° C. to 650° C. to form a backing layer (300), wherein the backing layer (300) is located on a side of the capture layer (200) away from the substrate (100). 4. The method for preparing a semiconductor substrate according to claim 3, characterized in that the step of forming the capture layer (200) comprises: forming a second polysilicon layer (220), wherein the second polysilicon layer (220) is located on the first surface (101); A first polysilicon layer (210) is formed, the base (100) having a second surface (102) that is away from the first surface (101), and the second polysilicon layer (220) is located on the second surface (102), thereby obtaining a first substrate (110); The second polysilicon layer (220) is removed, and the first polysilicon layer (210) is retained; the first polysilicon layer (210) serves as the capture layer (200). 5. The method for preparing a semiconductor substrate according to claim 4, characterized in that the first polysilicon layer (210) and/or the second polysilicon layer (220) are prepared by the following method: using a silicon-containing gas to deposit polysilicon on the surface of the substrate (100); the consumption of the silicon-containing gas is . 6. The method for preparing a semiconductor substrate according to claim 4, characterized in that, in the step of forming the first polysilicon layer (210), the substrate (100) is placed in an environment with a temperature range of 600°C to 660°C; and/or, in the step of forming the second polysilicon layer (220), the substrate (100) is placed in an environment with a temperature range of 600°C to 660°C. 7. The method for preparing a semiconductor substrate according to claim 4, characterized in that the second polysilicon layer (220) is removed by a chemical mechanical polishing method, and the chemical mechanical polishing method comprises: grinding the second polysilicon layer (220) to remove the second polysilicon layer (220). 8. The method for preparing a semiconductor substrate according to claim 7, characterized in that the first substrate (110) is adsorbed on a polishing head (3), the polishing head (3) has a chamber (300), along a thickness direction (X) of the semiconductor substrate (1), the chamber (300) has a first thickness _H1 μm, the first substrate (110) has a second thickness _H2 μm, and satisfies: 0＜ _H1 - _H2≤20μm . 9. An image sensor, characterized in that the image sensor comprises the semiconductor substrate (1) according to any one of claims 1 to 2; or the image sensor comprises the semiconductor substrate (1) prepared by the method for preparing the semiconductor substrate (1) according to any one of claims 3 to 8; The semiconductor substrate (1) serves as a base of the image sensor. 10. The image sensor according to claim 9, characterized in that the semiconductor substrate (1) comprises a P-type substrate.