CN117174695A - Test structures, semiconductor devices, wafers, electronic products and methods - Google Patents

Abstract

The embodiment of the application provides a test structure, a semiconductor device, a wafer, an electronic product and a method, wherein the test structure comprises the following components: at least one first metal pad coupled to a high level voltage; at least one second metal bonding pad coupled with a low-level voltage, wherein each second metal bonding pad is alternately arranged with the first metal bonding pad, and an interlayer dielectric is accommodated between the adjacent first metal bonding pad and the second metal bonding pad; a plurality of test layers secured within said interlayer dielectric between adjacent ones of said first metal pads and said second metal pads, each of said test layers comprising: the first test metal blocks and the second test metal blocks are alternately arranged at intervals, and the metal density of the test structure is reduced, so that the generated thermal stress is smaller in the subsequent laser cutting process, the generated heat is not easy to conduct into the chip, and the low dielectric constant material in the chip is not easy to be layered due to mismatch of thermal expansion coefficients.

Description

Test structures, semiconductor devices, wafers, electronic products and methods

Technical field

This application relates to the field of semiconductors, specifically to a test structure, semiconductor device, wafer, electronic product and method.

Background technique

The chip wafer-level reliability test structure is generally used to monitor the process stability of the wafer production line and identify qualified chips before the wafers are sent to the packaging factory. In the design stage, some test structures are usually designed in the dicing groove of the wafer, including some structures related to devices and metal wiring. Through electrical measurement, data analysis, and the distribution of data on the wafer, the production line is judged. process stability and volatility. Since the wafer test structure is generally placed in the dicing groove, when the subsequent packaging factory performs cutting, whether it is laser cutting or knife cutting, the wafer test structure will generally be touched. In the existing wafer test structure, due to stress during cutting, such as thermal stress generated by the heat generated by the laser, it will act on the inside of the chip, and it is easy to delaminate in the low dielectric constant dielectric layer inside the chip, thus Causes device failure, so there are many shortcomings.

Contents of the invention

In order to solve the problem of current wafer test structures causing dielectric layer delamination due to stress, thereby causing device failure, embodiments of the present application provide a test structure, a semiconductor device, a wafer, an electronic product and a method, which reduce the metal density of the test structure , the thermal stress generated during subsequent laser cutting is small, the heat generated is not easily conducted to the inside of the chip, and the low dielectric constant material inside the chip is not prone to delamination due to mismatch in thermal expansion coefficient.

The first embodiment of the present application provides a test structure, including: at least one first metal pad, coupled to a high-level voltage; at least one second metal pad, coupled to a low-level voltage, each Two metal bonding pads are alternately arranged with the first metal bonding pad, and an interlayer dielectric is accommodated between the adjacent first metal bonding pad and the second metal bonding pad; a multi-layer test layer is fixed on In the interlayer dielectric between the adjacent first metal pads and the second metal pads, each layer of the test layer includes: first test metal blocks and second test metal blocks arranged at alternating intervals. block; wherein the first test metal block is coupled to the first metal pad, and the second test metal block is coupled to the second metal pad.

In this application, the test layer between the first metal pad and the second metal pad is configured as a first test metal block and a second test metal block arranged at alternating intervals. The first test metal block is coupled to a high level, and the second test metal block is coupled to a high level. The test metal block is coupled to a low level, so that the breakdown test is performed between the two metal blocks, which can realize the wafer-level inter-metal dielectric breakdown test, because there is a gap formed between the first test metal block and the second test metal block. gap, thus compared with configuring a complete test metal layer structure between the first metal pad and the second metal pad, the metal density is greatly reduced, and the effective side length of the metal is not reduced, which can effectively capture production line abnormalities. While the probability has basically not changed, due to the reduced metal density, the thermal stress generated during subsequent laser cutting is smaller, the heat generated is not easily conducted to the inside of the chip, and the low dielectric constant material inside the chip is not easily expanded due to thermal expansion. Mismatch in coefficients (CTE) creates delamination.

In some embodiments, the number of the first metal bonding pads and the number of the second metal bonding pads are the same or different.

Specifically, the number of the first metal bonding pads is N, the number of the second metal bonding pads is N+1, and N is an integer greater than or equal to 1. In this way, when N is equal to 1, the test structure of the present application includes two second metal pads and one first metal pad, and a structure of two groups of test units can be formed. From this point of view, this implementation The method can form a structure of 2N groups of test units, so that the test structure of this application can be expanded to between more metal pads, thereby further increasing the effective side length of the metal, thereby increasing the probability of catching inter-metal dielectric anomalies in the production line. .

Specifically, the number of the first metal bonding pads is N, the number of the second metal bonding pads is N, and N is an integer greater than or equal to 1. In this way, when N is equal to 2, the test structure of this application includes two second metal pads and two first metal pads, and a structure of three groups of test units can be formed. From this point of view, this application The implementation can form a structure of 2N-1 sets of test units, so that the test structure of the present application can be expanded to between more metal pads, thereby further increasing the effective side length of the metal, thereby increasing the capture of intermetallic media in the production line Abnormal probability.

In some embodiments, the number of the first metal bonding pads is N+1, the number of the second metal bonding pads is N, and N is an integer greater than or equal to 1. In this way, when N is equal to 1, the test structure of the present application includes two first metal pads and one first metal pad, and a structure of two groups of test units can be formed. From this point of view, this implementation The method can form a structure of 2N groups of test units, so that the test structure of this application can be expanded to between more metal pads, thereby further increasing the effective side length of the metal, thereby increasing the probability of catching inter-metal dielectric anomalies in the production line. .

In some embodiments, in at least part of the test layer, the number of the first test metal blocks and the number of the second test metal blocks are the same or different.

For example, in some embodiments, in at least part of the test layer, the number of the first test metal blocks is M, and the number of the second test metal blocks is M+1. In this way, 2M test gaps are formed between the first test metal blocks and the second test metal blocks, and the inter-metal dielectric breakdown test can be performed within the test gaps.

The inter-metal dielectric (IMD) structure is used to characterize the weak links of the inter-metal dielectric in the back-end process (BEOL). The currently commonly used inter-metal dielectric (IMD) breakdown test structure tests the structure of all layers during the test. Pressurization is performed at the same time. Generally, breakdown mainly occurs at small intervals between metals in the same layer and mis-align defects in two metal layers. In the embodiment of the present application, 2M first test metal blocks and second test metal blocks are formed between The test gaps form 2M test gaps. Since the first test metal block is coupled to high level and the second test metal block is coupled to low level, after the alternate setting, the gap forms a certain voltage difference, which can Intermetal dielectric (IMD) breakdown testing is performed by continuously adjusting the applied voltage.

In some embodiments, in at least part of the test layer, the number of the first test metal blocks is M, and the number of the second test metal blocks is M, where M is an integer greater than or equal to 1. In this way, 2M+1 test gaps between the first test metal blocks and the second test metal blocks can be formed between the first metal pads and the second metal pads, and metal-to-metal testing can be performed within the test gaps. For the dielectric breakdown test, the embodiment of the present application forms 2M+1 test gaps by forming 2M+1 test gaps between the first test metal block and the second test metal block. Since the first test metal block is coupled High level, the second test metal block is coupled to low level, so that after alternating settings, a certain voltage difference is formed in the gap, and the inter-metal dielectric (IMD) breakdown test can be performed by continuously adjusting the applied voltage.

In some embodiments, in at least one test layer, the test metal block adjacent to the first metal pad is a second test metal block, and the test metal block adjacent to the second metal pad The block is the first test metal block. In this way, since the first test metal block is coupled to high level, the second test metal block is coupled to low level, the first metal pad is coupled to high level, and the second metal pad is coupled to low level, After this setting, the first metal pad and the second test metal block also form a high and low level difference, so that the inter-metal layer between the first metal pad and the adjacent test metal block can also be continuously adjusted by continuously adjusting the applied voltage. Dielectric (IMD) breakdown test.

In some embodiments, in the same test layer, all the first test metal blocks have the same length, and/or all the second test metal blocks have the same length. In this embodiment, all the first test metal blocks have the same length, or all the second test metal blocks have the same length. On the one hand, the same etching parameters can be used for etching during production, without separation. One-step etching simplifies the manufacturing process. On the other hand, the first test metal block or the second test metal block of equal length has the same impact on the voltage. Therefore, there is no need to consider the impact of resistance factors such as length on the voltage output during testing, thus This makes the test results of the inter-metal dielectric (IMD) breakdown test more accurate and the measured breakdown voltage more accurate.

In some embodiments, each test layer includes at least two first test metal blocks with different lengths, and/or each test layer includes at least two second test metal blocks with different lengths. In this way, a variety of different tests can be carried out in the same test structure, and second test metal blocks with different lengths can be set to adjust different metal densities and metal effective side lengths. For example, part of the first test metal block or part of the second test metal block can be set. If the test metal block is a longer structure, the effective side length of the metal can be increased to a certain multiple of the original, and the metal density can be adjusted as needed.

In some embodiments, the lengths of all the first test metal blocks and the second test metal blocks are the same, and among the two adjacent test layers, the test layer located on the upper layer is provided with the length of the first test metal block. Position, set the position of the second test metal block corresponding to the test layer located on the lower layer. In this way, the orthographic projection of the position of the first test metal block coupled to the high-level flat in the upper test layer overlaps with the position of the second test metal block coupled to the low-level in the lower test layer, thereby forming a The high and low voltage difference is eliminated, so inter-metal dielectric breakdown testing can also be carried out, thereby realizing dielectric breakdown testing between upper and lower metal layers.

In some embodiments, in each test layer, the length of the K first test metal blocks is the first length, the length of the N-K first test metal blocks is the second length, and K is a positive number less than or equal to N/2. An integer, N is the number of first test metal blocks; wherein at least one first test metal block of second length is spaced between the K first test metal blocks of first length. In this way, the first test metal blocks of different lengths can be set separately.

In some embodiments, the length of the second test metal block is different from the length of the first test metal block. In this way, the metal density and metal effective side length can be adjusted as needed, providing a higher degree of freedom for the adjustment of metal density and metal effective side length.

In some embodiments, each layer of the test layer further includes: a first metal layer and a second metal layer, the first metal layer includes a first connection for electrically connecting to the first test metal block. The second metal layer includes a second connection member for electrically connecting with the second test metal block. In this way, the first test metal block and the first metal pad are coupled through the first connector, so that a high level can be applied to the first test metal block through the first metal pad, and a high level can be applied to the first test metal block through the second metal pad. The low level is given to the second test metal block to complete the inter-metal dielectric breakdown test between the first test metal block and the second test metal block.

In some embodiments, the spacing between the adjacent first test metal blocks and the second test metal blocks is the same or different. In this way, the thickness of the metal medium with different spacing is higher and it is more difficult to break down. Therefore, the dielectric breakdown can be tested by the thickness of the spacing. The breakdown effect of different media thicknesses can be tested, and the test metal blocks with the same spacing The thickness of the metal dielectric between them is the same, which can ensure the uniformity of the influencing factors of the breakdown test, and can test the difference in breakdown effects at different locations under the same voltage.

In some embodiments, the multi-layer test layer is a top metal layer of a semiconductor device, and/or the thickness of each test layer is greater than or equal to 3 microns. In this way, the embodiment of the present application can be applied to devices where the back-stage metal dielectric is made of low k (k<3.9) material to prevent damage to the chip during cutting, and when the back-stage metal interconnect dielectric layer is made of low k material. The ultra-thick metal layer (generally around 3um) and the metal dielectric breakdown test structure are designed to prevent cracks in the medium during cutting.

A second embodiment of the present application provides a semiconductor device, including a substrate, a semiconductor structure formed on the substrate, and a test structure as described above.

The semiconductor device provided by this application includes the above-mentioned test structure, so it can realize the basic function of monitoring metal dielectric defects in the production line. Compared with the traditional inter-metal dielectric breakdown test structure, in the same area, the new metal The metal density of the inter-dielectric breakdown test structure dropped to 55% of the original, but the effective side length of the metal did not decrease and was basically the same as before. The probability of catching abnormalities in the production line has basically not changed. Because this structure reduces the metal density, the thermal stress generated during subsequent laser cutting is smaller, and the generated heat is not easily conducted to the inside of the chip. The low k material inside the chip is not easily delamination due to CTE mismatch.

A third embodiment of the present application provides an electronic product, including a housing, multiple functional hardware, and a semiconductor device as described above.

Among them, multi-functional hardware can include functional hardware such as cameras, displays, microphones, and gyroscopes. The thermal stress generated during the laser cutting process of the above-mentioned semiconductor devices is small, so that the low k material inside the chip is not easily damaged due to CTE. The preparation produces stratification, which can ensure the stability of the subsequent use of the product.

A fourth embodiment of the present application provides a semiconductor wafer, including a wafer panel in which a plurality of semiconductor devices as described above are formed.

Among them, multi-functional hardware can include functional hardware such as cameras, displays, microphones, and gyroscopes. The thermal stress generated during the laser cutting process of the above-mentioned semiconductor devices is small, so that the low k material inside the chip is not easily damaged due to CTE. The preparation produces stratification, which can ensure the stability of the subsequent use of the product.

The fifth aspect of the implementation of the present application provides a method for conducting inter-metal dielectric breakdown testing using the test structure as described above, including:

Write a high level voltage to the first metal welding pad and the first test metal block in each test layer, and write a low level voltage to the second metal welding pad and the second test metal block in each test layer. level voltage;

The test structure is used to monitor the stability of the metal interconnection medium of the production line.

Specifically, in some embodiments, the potential difference between the two metal pads can be gradually increased from 0, and the current between the two metal pads can be tested. When the current rises sharply, the two metal pads The potential difference between them (that is, the potential difference between the adjacent first test metal block and the second test metal block) can be considered as the breakdown voltage of the interlayer dielectric. The stability of the production line metal interconnect dielectric is monitored by comparing the measured breakdown voltage to a threshold range.

Description of drawings

Figure 1 is a schematic diagram of the process structure of configuring the test structure in the dicing groove before wafer cutting provided by Example Technology;

Figure 2 is a schematic diagram of the process structure when the dicing groove is opened after wafer cutting provided by the example technology;

Figure 3 is a schematic diagram of the test structure used for comparison in this application;

Figure 4 is a schematic diagram of the defect photo shown in Figure 3;

Figure 5 is one of the schematic diagrams of the test structure in the embodiment of the present application;

Figure 6 is the second schematic diagram of the test structure in the embodiment of the present application;

Figure 7 is the third schematic diagram of the test structure in the embodiment of the present application;

Figure 8 is the fourth schematic diagram of the test structure in the embodiment of the present application;

Figure 9 is the fifth schematic diagram of the test structure in the embodiment of the present application;

Figure 10 is a schematic flow chart of the testing method in the embodiment of the present application;

Figure 11 is one of the structural schematic diagrams of a semiconductor wafer including the test structure provided by the embodiment of the present application;

Figure 12 is the second structural schematic diagram of a semiconductor wafer including the test structure provided by the embodiment of the present application;

FIG. 13 is a top view of a semiconductor wafer provided by an embodiment of the present application.

Reference signs: 20-test structure, vx-etch stop layer, 11-first metal pad, 12-second metal pad, 21-metal strip, 22-first test metal block, 23-second test Metal block, 24-first metal layer, 25-first connector, 26-second metal layer, 27-second connector, 28-span structural metal connection layer.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the specific technical solutions of the present application will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

Figure 1 shows a schematic structural diagram of the current wafer before cutting, and Figure 2 shows a schematic structural diagram of the wafer after cutting. According to Figures 1 and 2, in the design stage, the design is usually done in the dicing groove of the wafer. Some test structures 20 , including some structures related to devices and metal wiring, determine the process stability and volatility of the production line through electrical measurement, data analysis, and data distribution on the wafer. Since the wafer test structure is generally placed in the dicing groove, the test structure 20 will generally be touched during subsequent cutting in the packaging factory, whether by laser cutting or knife cutting. On a wafer, hundreds or thousands of chips are usually formed, with a certain gap between them, such as 60μm to 150μm. This gap is called a dicing groove. After the semiconductor manufacturing process is completed and tested with test chips, these chips are cut from the wafer along dicing grooves to form individual chips. In some embodiments, the test structure 20 of the present application is located in the chip area, and the structure used to detect defects in the inter-metal dielectric layer is located in the cutting groove area, which can save chip area.

Figure 3 shows a schematic diagram of the test structure for inter-metal dielectric breakdown in the example technology. Figure 4 shows a schematic diagram of the actual object when the inter-metal dielectric is broken down. As shown in Figure 3, the structure is a comb-to-comb comb shape. Structure, the long metal strips 21 are staggered with the first metal pads 11 and the second metal pads 12 to meet the metal spacing and metal size, which are the minimum sizes in the design rules. This test structure is used for ultra-thick metal (UTM). The ultra-thick metal layer can be about 3um and is the top metal of the chip. During the specific test, the first metal pad 11 of this structure is connected to high voltage, and the second metal pad 12 is connected to ground. By sweeping the voltage from low to high, the test current changes with the voltage until the intermetallic medium occurs as shown in Figure 4. The breakdown is shown to complete the inter-metal dielectric breakdown test. However, this test structure is prone to delamination of the dielectric layer with low dielectric constant inside the chip during laser cutting, and the cause of this phenomenon has not yet been discovered.

The inventor of the present application has found through research that the high metal density of the dicing groove is an important reason for the delamination of the later dielectric layer. If the test structure in the dicing groove is an area with relatively high metal density, and the metal dielectric layer of the rear part of the chip is When low k (k<3.9, Young's modulus is low, hardness is low, toughness is low, and adhesion to the underlying material is insufficient), due to stress, such as thermal stress generated by the heat generated by the laser, it will Inside the chip, if this stress is greater than the adhesion between materials, delamination will easily occur in the low k dielectric layer inside the chip, leading to device failure.

Based on the above findings of the inventor of the present application, the present application designed a new type of metal dielectric breakdown test structure by reducing the metal density of the test structure. This structure will produce less thermal stress during subsequent laser cutting. Heat is not easily conducted to the inside of the chip, and the low dielectric constant material inside the chip is not easy to delaminate due to mismatch in thermal expansion coefficients.

In order to detect defects in the interlayer dielectric, embodiments of the present application provide a test structure for detecting defects in the interlayer dielectric. Through the special design of this structure, this structure can detect defects generated in the intermetallic medium under certain process conditions. When this structure for detecting defects in the interlayer dielectric is placed on the same wafer as the chip to be produced, During on-circle manufacturing, this test structure is used to monitor the stability of the metal interconnect medium on the production line.

According to some embodiments of the present application, Figure 5 shows a schematic structural diagram of a test structure, including: a first metal pad 11, coupled to a high-level voltage; a second metal pad 12, coupled to a low-level voltage. flat voltage, the second metal pads 12 and the first metal pads 11 are alternately arranged, and an interlayer dielectric is accommodated between the first metal pads 11 and the second metal pads 12; multi-layer Test layer, fixed in the interlayer dielectric between the first metal pad 11 and the second metal pad 12 , each layer of the test layer includes: first test metal blocks 22 arranged at alternating intervals. and a second test metal block 23; wherein, the first test metal block 22 is coupled to the first metal pad 11, and the second test metal block 23 is coupled to the second metal pad 12.

In this application, the test layer between the first metal pad 11 and the second metal pad 12 is configured as a first test metal block 22 and a second test metal block 23 arranged at alternating intervals. The first test metal block 22 is coupled to a high level, the second test metal block 23 is coupled to the low level, so that the breakdown test is performed between the two metal blocks, and the wafer-level inter-metal dielectric breakdown test can be realized. Since the first test metal block 22 and the second test metal block 22 A gap is formed between the test metal blocks 23, so that compared with configuring a complete test metal layer structure between the first metal pad 11 and the second metal pad 12, the metal density is greatly reduced, and the effective side length of the metal is not reduced. , the probability of being able to effectively capture production line abnormalities has basically not changed. At the same time, due to the reduced metal density, the thermal stress generated during subsequent laser cutting is smaller, and the generated heat is not easily conducted to the inside of the chip. Inside the chip Low dielectric constant materials are less prone to delamination due to coefficient of thermal expansion (CTE) mismatch.

It should be noted that the embodiments of the present application can be used in devices where the back-stage metal medium is a low k (k<3.9) material to prevent damage to the chip during cutting.

In addition, the embodiments of the present application can be used for performance testing of interlayer dielectrics. Specifically, in the manufacturing process of integrated circuits, multi-layer metal interconnection line structures are usually used to realize circuit connections. A dielectric material, the so-called interlayer dielectric (IMD), is used between multi-layer metal interconnect lines to achieve electrical isolation. Commonly used dielectric materials include silicon oxide and low-k materials. However, due to the complexity of the semiconductor manufacturing process, it is easy to form defects in the interlayer dielectric, such as cracks, pinholes, particles, etc., thus affecting the dielectric properties of the interlayer dielectric, causing leakage, and leading to yield and reliability issues.

In the embodiment of the present application, the material of the test metal block (including the above-mentioned first test metal block 22 and the second test metal block 23 ) may include aluminum and/or copper. The present application is not limited thereto, and the test metal block may also be Other suitable materials in the field.

In the embodiment of the present application, the material of the interlayer dielectric is silicon oxide or a low-k material.

In the embodiment of the present application, the metal density is the sum of the metal areas between the first metal pad 11 and the second metal pad 12 / the total area between the first metal pad 11 and the second metal pad 12 .

In the embodiment of the present application, the effective metal side length is the sum of the relative metal side lengths of the first test metal block 22 and the adjacent second test metal block 23 .

Please continue to refer to Figure 5. When the test structure of the present application is specifically used, the first metal pad 11 is connected to the high level, and the second metal pad 12 is connected to the low level. At the same time, the first metal pad 11 is connected to the low level. The test metal block 22 is coupled to the first metal pad 11 , and the second test metal block 23 is coupled to the second metal pad 12 , so that the voltage between the first metal pad 11 and the first test metal block 22 is high, the voltage of the second metal pad 12 and the second test metal block 23 is low, and since the first test metal block 22 and the second test metal block 23 are alternately arranged, a voltage difference is formed between the two, and through continuous The applied voltage can be adjusted to control the magnitude of the voltage difference, thereby achieving breakdown voltage testing of the gap between the first test metal block 22 and the second test metal block 23 .

During specific testing, different test voltages are applied to the first metal pad 11 and the second metal pad 12. Since the first metal pad 11 and the first test metal block 22 are electrically connected, the second metal pad 12 is pre-tested. The two test metal blocks 23 are electrically connected, thereby applying different test voltages, and the current between the adjacent first test metal block 22 and the second test metal block 23 can be detected. For example, the steps of applying a test voltage and monitoring current can be performed through the above-mentioned first metal bonding pad 11 and second metal bonding pad 12, and then it is determined whether there is a defect in the dielectric layer based on the current.

Specifically, in some embodiments, the potential difference between the two metal pads can be gradually increased from 0, and the current between the two metal pads can be tested. When the current rises sharply, the two metal pads The potential difference between them (that is, the potential difference between the adjacent first test metal block 22 and the second test metal block 23 ) can be considered as the breakdown voltage of the interlayer dielectric. Compare the measured breakdown voltage with the threshold range. When the breakdown voltage is less than the above threshold, there may be instability in the production line.

It should be noted that the above threshold range can be determined according to specific processes and dielectric materials, or can also be determined by testing the breakdown voltage of an interlayer dielectric without defects determined by other means.

In other embodiments, a preset test voltage can be applied between two metal bonding pads and the voltage value remains unchanged to test the change of the current between the two metal bonding pads over time. If there are defects in the interlayer dielectric, metal (such as copper) will diffuse in, forming conductive channels in the interlayer dielectric. In this case, if the test current increases significantly as the pressure test time increases, it means that the insulation performance of the interlayer dielectric has declined significantly and there are defects in the interlayer dielectric.

In order to further expand the test structure of the present application to between more metal pads, increase the effective side length of the metal, and thereby increase the probability of catching inter-metal dielectric anomalies in the production line, Figure 6 shows the test structure in the embodiment of the present application. As shown in Figure 6, two or more test structures can be combined in the implementation of this application (more than two implementations are not shown in this application due to the length of the drawings). To form a structure together, specifically, three different implementations may be included at this time: 1. The number of the first metal bonding pads 11 and the second metal bonding pads 12 is equal, 2. The number of the first metal bonding pads 11 is larger than that of the second metal bonding pads. The number of 12 is one more. 3. The number of the second metal bonding pads 12 is one more than the number of the first metal bonding pads 11 .

The above three embodiments will be described in detail below respectively.

1. The numbers of the first metal bonding pads 11 and the second metal bonding pads 12 are equal:

Figures 5 and 8 show a schematic structural diagram of an equal number of first metal pads 11 and second metal pads 12 in the embodiment of the present application. As shown in Figure 7, in this embodiment, the first metal pads The number of 11 is N, the number of the second metal pads 12 is N, and N is an integer greater than or equal to 1. In this way, when N is equal to 2, the test structure of the present application includes two second metal pads 12 and two first metal pads 11, and a structure of three groups of test units can be formed. From this point of view , this embodiment can form a structure of 2N-1 groups of test units, so that the test structure of this application can be expanded to more metal pads, thereby further increasing the effective side length of the metal, thereby increasing the amount of metal captured in the production line. probability of media anomaly.

2. The number of the first metal bonding pad 11 is one more than the number of the second metal bonding pad 12:

FIG. 7 shows a schematic structural diagram in which the number of the first metal bonding pads 11 is one more than the number of the second metal bonding pads 12 in the embodiment of the present application. As shown in FIG. 8 , in this embodiment, the first metal bonding pads 11 The number of second metal pads 12 is N+1, and N is an integer greater than or equal to 1. In this way, when N is equal to 1, the test structure of the present application includes two first metal pads 11 and one first metal pad 11, and a structure of two groups of test units can be formed. From this point of view, This implementation can form a structure of 2N groups of test units, so that the test structure of the present application can be expanded to between more metal pads, thereby achieving a further increase in the effective side length of the metal, thereby increasing the ability to capture inter-metal dielectric anomalies in the production line. The probability.

3. The number of the second metal bonding pads 12 is one more than the number of the first metal bonding pads 11:

Figure 6 shows a schematic structural diagram in which the number of second metal pads 12 is one more than that of the first metal pads 11 in the embodiment of the present application. As shown in Figure 6, in this embodiment, the first metal pads 11 The number is N, the number of the second metal pads 12 is N+1, and N is an integer greater than or equal to 1. In this way, when N is equal to 1, the test structure of the present application includes two second metal pads 12 and one first metal pad 11, and a structure of two groups of test units can be formed. From this point of view, This implementation can form a structure of 2N groups of test units, so that the test structure of the present application can be expanded to between more metal pads, thereby achieving a further increase in the effective side length of the metal, thereby increasing the ability to capture inter-metal dielectric anomalies in the production line. The probability.

It should be noted that in the above structure, in order not to introduce redundant voltage access pins, all first metal pads 11 can be electrically connected through the cross-structure metal connection layer 28 on the top layer, so that each first metal pad 11 All the bonding pads 11 can be written to a high level. Similarly, all the second metal bonding pads 12 can be electrically connected through the cross-structure metal connection layer 28 at the bottom layer, so that each of the second metal bonding pads 12 can be written to a low level. level.

The first test metal block 22 and the second test metal block 23 of the present application will be described in detail below.

Figures 5 to 8 show one of the schematic diagrams showing the quantity of the first test metal block 22 and the second test metal block 23 of the present application. Specifically, the present application can be provided in at least part of the test layer. The first test metal block The number of blocks 22 is M (M is equal to 2 in FIGS. 5 to 8 ), and the number of second test metal blocks 23 is M+1. In this way, 2M test gaps are formed between the first test metal blocks 22 and the second test metal blocks 23, and the inter-metal dielectric breakdown test can be performed in the test gaps. The inter-metal dielectric (IMD) structure is used to characterize the weak links of the inter-metal dielectric in the back-end process (BEOL). The currently commonly used inter-metal dielectric (IMD) breakdown test structure tests the structure of all layers during the test. Pressurization is performed at the same time. Generally, breakdown mainly occurs at small intervals between metals in the same layer and mis-align defects in two metal layers. In the embodiment of the present application, 2M first test metal blocks 22 and second test metal blocks 23 are formed. The test gaps between them form 2M test gaps. Since the first test metal block 22 is coupled to the high level and the second test metal block 23 is coupled to the low level, after the alternate setting, the gap forms a certain Voltage difference, inter-metal dielectric (IMD) breakdown testing can be performed by continuously adjusting the applied voltage.

At the same time, in the embodiment shown in FIGS. 5 to 8 , since the number of the second test metal blocks 23 is one more than the number of the first test metal blocks 22 , it is equivalent to the arrangement of the second test metal blocks 23 The first and last test layers are located in a layer, and the middle part is the first test metal block 22 and the second test metal block 23 alternating, so that one of the second test metal blocks 23 is close to the first metal pad at this time. 11. At this time, since the first metal pad 11 is coupled to a high-level voltage and the second test metal block 23 is coupled to a low-level voltage, the first and last test metal blocks located in a test layer ( The second test metal block 23) forms a high and low voltage difference with one of the metal pads, so that the breakdown test of the inter-metal dielectric can also be performed.

Figure 9 shows that in at least part of the test layer, the number of the first test metal blocks 22 is M (M is equal to 2 in Figure 9), the number of the second test metal blocks 23 is M, and M is An integer greater than or equal to 1. In this way, 2M+1 test gaps between the first test metal blocks 22 and the second test metal blocks 23 can be formed between the first metal pad 11 and the second metal pad 12, and the test gap can be The inter-metal dielectric breakdown test is performed within the application. In the embodiment of the present application, 2M+1 test gaps are formed between the first test metal block 22 and the second test metal block 23. Since the third test gap is One test metal block 22 is coupled to a high level, and the second test metal block 23 is coupled to a low level, so that after alternate settings, a certain voltage difference is formed in the gap, and the inter-metal dielectric (IMD) can be performed by continuously adjusting the applied voltage. ) breakdown test.

According to the embodiment shown in Figure 9, since there are M first test metal layers and second test metal layers, it is equivalent to when the first one located in a layer of test layers is the first test metal layer during arrangement , the last one in a layer of test layers is the second test metal layer, conversely, when the first one is the second test metal layer, the last one is the first test metal layer, and the middle part is the first test metal block 22 and the second test metal block 23 alternately, so there are two situations at this time. One is that the test metal block close to the first metal pad 11 is the first test metal block 22, which is close to the second metal pad 12. The test metal block is the second metal block. In this case, since the first test metal block 22 and the first metal pad 11 are both coupled to high level, the second test metal block 23 and the second metal pad 12 are coupled to low level. level, there is no voltage difference between the two, so there will be no breakdown test between the first metal pad 11 and the first test metal block 22; the second is a test close to the first metal pad 11 The metal block is the second test metal block 23, and the test metal block close to the second metal pad 12 is the first metal block. In this case, since both the first test metal block 22 and the first metal pad 11 are coupled to high level, the second test metal block 23 and the second metal pad 12 are coupled to a low level, then the first metal pad 11 and the second test metal block 23, and the second metal pad 12 and the first test A voltage difference is formed between the metal blocks 22, so the first and last test metal blocks (both the second test metal blocks 23) located in a test layer form a high and low voltage difference with one of the metal pads, so that the first The inter-metal dielectric (IMD) breakdown test can also be performed by continuously adjusting the applied voltage between the metal pad 11 and the adjacent test metal block.

Similarly, the number of the first test metal blocks 22 can also be set to M+1, and the number of the second test metal blocks 23 can be set to M, which will not be described in detail in this application.

In addition, it can be seen from FIGS. 5 to 8 that in the same test layer, all the first test metal blocks 22 have the same length, and/or all the second test metal blocks have the same length. In this embodiment, all the first test metal blocks 22 have the same length, or all the second test metal blocks 23 have the same length. On the one hand, the same etching parameters can be used for etching during production. There is no need for step-by-step etching, which simplifies the manufacturing process. On the other hand, the first test metal block 22 or the second test metal block 23 of equal length has the same impact on the voltage, so there is no need to consider the impact of resistance factors such as length on the voltage output during testing. influence, thus making the test results of the inter-metal dielectric (IMD) breakdown test more accurate and the measured breakdown voltage more accurate.

Figure 9 shows a schematic diagram of the test structure provided by the embodiment of the present application. As shown in Figure 12, the present application can also set the test metal blocks to have different lengths, that is, each test layer includes at least two first test metal blocks with different lengths. 22, and/or, each test layer includes at least two second test metal blocks 23 with different lengths. In this way, a variety of different tests can be carried out in the same test structure, and the second test metal blocks 23 with different lengths can be set to adjust different metal densities and metal effective side lengths. For example, part of the first test metal block 22 or part of the first test metal block 22 can be set. If the second test metal block 23 has a longer structure, the effective side length of the metal can be increased to a certain multiple of the original, and the metal density can be adjusted as needed.

Since the test structure provided by this application includes multiple test layers, the influence between the adjacent upper and lower test layers can be further considered. In this embodiment, all of the first test metal block 22 and the second test metal The lengths of the blocks 23 are the same, and among the two adjacent test layers, the upper test layer is set with the position of the first test metal block 22 , and the corresponding lower test layer is set with the position of the second test metal block 23 . In this way, the orthographic projections of the position of the first test metal block 22 coupled to the high level in the upper test layer and the position of the second test metal block 23 coupled to the low level in the lower test layer overlap, so that the two A high and low voltage difference is formed between them, so inter-metal dielectric breakdown testing can also be carried out, thus realizing dielectric breakdown testing between upper and lower metal layers.

Please continue to refer to Figure 9. It can be seen that the local metal density of the test metal block with a longer length is greater. Therefore, in order to ensure the uniformity of the local metal density and the effective side length of the metal, in some embodiments of the present application, In each test layer, the length of the K first test metal blocks 22 is the first length, the length of the N-K first test metal blocks 22 is the second length, K is a positive integer less than or equal to N/2, and N is the second length. A number of test metal blocks 22; wherein the K first test metal blocks 22 of the first length are spaced apart by at least one first test metal block 22 of the second length. In this way, the first test metal blocks 22 of different lengths can be arranged separately, so that the local metal density is high and the metal effective side length is longer, while the metal density in other places is low and the metal effective side length is shorter. , ensuring the uniformity of local metal density and effective side length of metal.

It can be seen from the above embodiments that the length of the second test metal block 23 in this application is different from the length of the first test metal block 22 . In this way, the metal density and metal effective side length can be adjusted as needed, providing a higher degree of freedom for the adjustment of metal density and metal effective side length.

Please continue to refer to Figure 5. The coupling method in the embodiment of the present application can be achieved by etching via holes on the metal layer and the test metal block, then depositing conductive metal in the via hole, and then leading the metal layer to the metal On the soldering pad or on a voltage terminal, the test metal block is coupled to high and low voltages. In this embodiment, each test layer further includes: a first metal layer 24 and a second metal layer 26 . The first metal layer 24 includes a third metal layer for electrically connecting to the first test metal block 22 . A connector 25 , the second metal layer 26 includes a second connector 27 for electrical connection with the second test metal block 23 . In this way, the first test metal block 22 is coupled to the first metal pad 11 through the first connector 25, so that a high level can be applied to the first test metal block 22 through the first metal pad 11. The two metal pads 12 apply a low level to the second test metal block 23 to complete the inter-metal dielectric breakdown test of the first test metal block 22 and the second test metal block 23 .

Further, in the embodiment of the present application, the spacing between the adjacent first test metal blocks 22 and the second test metal blocks 23 is the same, and the minimum spacing size in the design rules should be used, so that it can be detected Breakdown voltage under the most severe structural conditions.

Furthermore, the embodiments of the present application can be applied to devices in which the back-end metal medium is a low k (k<3.9) material, that is, on the one hand, it can be used for the top metal layer of the chip, and the multi-layer test layer is the top layer of the semiconductor device. The metal layer, and/or the thickness of each test layer is greater than or equal to 3 microns. In this way, the embodiment of the present application can be applied to devices where the back-end metal medium is a low k (k<3.9) material to prevent damage to the chip during cutting, and can be applied to ultra-thick metal layers (generally around 3um) , the top metal used for chips.

The following is a further detailed description of the effects of the embodiment shown in Figure 5 of the present application. In the embodiment shown in Figure 5, the original UTM metal is in the shape of comb to comb strips, while the new structure of the UTM is in the shape of a square. Each metal block has the opposite voltage applied to adjacent blocks. For example, the first metal pad 11 is connected to low voltage, the second metal pad 12 is connected to high voltage, and the high voltage terminal is connected to the third metal through the lower metal (ie, the first metal layer 24) and the top through hole (the first connector 25 is provided). A metal bonding pad 11, the low voltage terminal is connected to the second metal bonding pad 12 through the lower metal layer (ie, the second metal layer 26) and the lower through hole (the second connector 27 is provided). Since there is space between each metal square in the new structure, the metal density is low, from 45.9% of the metal density of the original structure to 25.5% of the new structure. Similarly, the first metal pad 11 is connected to high voltage, and the second metal pad 12 is connected to low voltage. Because each metal square and the surrounding metal squares of the new structure can capture the abnormality of the metal medium of the production line, through calculation, the effective metal side length of the new structure (that is, the metal side length that can detect the breakdown of the metal medium of the production line) is the original The structure is 1.09 times larger, basically the same as the original structure, but the metal density is only 55% of the original structure. Such a structure not only meets the requirement for the effective side length of the metal (the longer the metal side length, the easier it is to catch production line abnormalities), but also reduces the metal density, reducing the risk of low k dielectric layer delamination during cutting. This wafer-level intermetallic dielectric breakdown test structure can realize the basic function of monitoring metal dielectric defects in the production line. Compared with the traditional intermetallic dielectric breakdown test structure, in the same area, the new intermetallic dielectric breakdown test structure can achieve the basic function of monitoring metal dielectric defects in the production line. The metal density of the test structure dropped to 55% of the original, but the effective side length of the metal did not decrease and was basically the same as before. The probability of catching abnormalities in the production line has basically not changed. Because this structure reduces the metal density, the thermal stress generated during subsequent laser cutting is smaller, and the generated heat is not easily conducted to the inside of the chip. The low k material inside the chip is not easily delamination due to CTE mismatch.

In the embodiment shown in Figure 9, the square test metal block is changed into a rectangular shape. The effective side length of the metal in this design is 1.17 times the original, and the metal density is 30%, which is reduced to 55% of the original. The risk of cutting cracks is also reduced.

Figures 11 and 12 show the cross-sectional view in the A1-A2 direction of Figure 5 provided by the embodiment of the present application, wherein Figure 11 is a cross-sectional view in the B1 to B2 direction, and Figure 12 is a cross-sectional view in the A2 to A1 direction, as shown in As shown in Figure 11 and Figure 12, the test structure forms the M1-Mn layer test layer. V1-Vn are the first metal layer and the second metal layer corresponding to each test layer. For example, V1 is the first metal layer corresponding to the M1 test layer. and the second metal layer, V2 is the first metal layer and the second metal layer corresponding to the M2 test layer, and UTM is the ultra-thick metal layer in this structure, which will not be described in detail here in this application.

Specifically, the semiconductor device is obtained by cutting a semiconductor wafer, and the test structure is included inside the semiconductor device. Since the semiconductor device provided by this application includes the above test structure, it can realize the basic function of monitoring metal dielectric defects in the production line, and Compared with the traditional inter-metal dielectric breakdown test structure, within the same area, the metal density of the new inter-metal dielectric breakdown test structure is reduced to 55% of the original, but the effective side length of the metal is not reduced, and is basically the same as the original one. flat. The probability of catching abnormalities in the production line has basically not changed. Because this structure reduces the metal density, the thermal stress generated during subsequent laser cutting is smaller, and the generated heat is not easily conducted to the inside of the chip. The low k material inside the chip is not easily delamination due to CTE mismatch.

Figure 13 shows a semiconductor wafer provided by an embodiment of the present application. The semiconductor wafer is used to manufacture the semiconductor device in the above embodiment. Specifically, the semiconductor wafer is layer-by-layer masked and etched to form the layers of the semiconductor device. structure, and then multiple semiconductor devices are obtained by cutting on the semiconductor wafer, in which the test structures are placed in the dicing grooves.

An electronic product provided by an embodiment of the present application includes a housing, multiple functional hardware, and a semiconductor device as described above.

Among them, multi-functional hardware can include functional hardware such as cameras, displays, microphones, and gyroscopes. The thermal stress generated during the laser cutting process of the above-mentioned semiconductor devices is small, so that the low k material inside the chip is not easily damaged due to CTE. The preparation produces stratification, which can ensure the stability of the subsequent use of the product.

Figure 10 shows the method of this application using the fixed test structure in the above embodiment to conduct inter-metal dielectric breakdown testing, including:

S1: Write a high-level voltage to the first metal pad and the first test metal block in each test layer, and write a high-level voltage to the second metal pad and the second test metal block in each test layer. Enter low level voltage;

S2: Use the test structure to monitor the stability of the metal interconnection medium of the production line. It can be understood that when the test structure of the present application is specifically used, the first metal pad is connected to a high level, and the second metal pad is connected to a low level. At the same time, the first test metal block is coupled to the The first metal welding pad, the second test metal block is coupled to the second metal welding pad, so that the voltage of the first metal welding pad and the first test metal block is high, the second metal welding pad and the second test metal The voltage of the block is low, and since the first test metal block and the second test metal block are alternately arranged, a voltage difference is formed between the two. By constantly adjusting the applied voltage, the size of the voltage difference can be controlled to achieve the first Breakdown voltage test of the gap between the test metal block and the second test metal block. If no defects are detected in the interlayer dielectric in all gaps in a test layer, then it can be considered that the same layer in the chip produced at the same time is Other semiconductor devices set up are also free of interlayer dielectric defects.

During a specific test, different test voltages are applied to the first metal pad and the second metal pad. Since the first metal pad and the first test metal block are electrically connected, the second metal pad is electrically connected to the second test metal block. The connection is made so that different test voltages are applied, and the current between the adjacent first test metal block and the second test metal block can be detected. For example, the steps of applying a test voltage and monitoring current can be performed through the above-mentioned first metal pad and second metal pad, and then it is determined whether there is a defect in the dielectric layer based on the current.

Specifically, in some embodiments, the potential difference between the two metal pads can be gradually increased from 0, and the current between the two metal pads can be tested. When the current rises sharply, the two metal pads The potential difference between them (that is, the potential difference between the adjacent first test metal block and the second test metal block) can be considered as the breakdown voltage of the interlayer dielectric. The measured breakdown voltage is compared with the threshold range. When the breakdown voltage is less than the above threshold, it is considered that there is a defect in the interlayer dielectric between the first metal pad and the second metal pad. This is because in the dielectric After a layer defect occurs, metal (such as copper) will diffuse in, forming a conductive path or reducing the effective isolation distance.

The following is a test method for reliability analysis of the interlayer dielectric in the embodiment of the present application. The test method at least includes the following steps:

1) Provide a test structure, the test structure includes: at least one first metal pad, coupled to a high-level voltage; at least one second metal pad, coupled to a low-level voltage, each second metal pad Welding pads are alternately arranged with the first metal welding pads, and an interlayer dielectric is accommodated between the adjacent first metal welding pads and the second metal welding pads; multi-layer test layers are fixed on adjacent In the interlayer dielectric between the first metal pad and the second metal pad, each layer of the test layer includes: a first test metal block and a second test metal block arranged at alternate intervals; Wherein, the first test metal block is coupled to the first metal pad, and the second test metal block is coupled to the second metal pad.

2) Apply a bias voltage to the first metal welding pad, the second metal welding pad, all first test metal blocks and all second test metal blocks, and detect the first metal welding pad and the second metal welding pad. , the read values of all the first test metal blocks and all the second test metal blocks, thereby detecting the interlayer dielectric between the first metal bonding pad and the second metal bonding pad.

It should be noted that the test structure provided in this test method is consistent with the description of the test structure in the above-mentioned test structure implementation of this application. For the specific description of the test structure, please refer to the foregoing implementation and will not be discussed here. Let’s go over them one by one.

To detect the reliability of the interlayer dielectric, the voltage boost method (Vramp methodology) and the time-based dielectric breakdown voltage (Time Dependent Dielectric Breakdown, TDDB) method can be applied.

The voltage boosting method is to apply a voltage that increases in constant steps to both ends of the interlayer dielectric (i.e., the first metal pad, the second metal pad, all the first test metal blocks, and all the second test metal blocks) , while continuously detecting the current readout value. When the voltage rises to a certain level, the interlayer dielectric is broken down, and then based on the corresponding readout value data recorded during this process, the reliability of the tested interlayer dielectric is evaluated. . Such inspection results can also often reflect the number of defects in the material.

The time-based dielectric breakdown voltage (TDDB) is the value of the test structure (i.e., the first metal bonding pad, the second metal bonding pad) when the test structure is in an ambient temperature range of 80 to 150°C. A constant high voltage is applied to the pad, all first test metal blocks, and all second test metal blocks) while a current reading is continuously detected. After a period of time, if the detected leakage of the dielectric layer (current reading value) exceeds a certain value, the dielectric layer is considered to have failed, and the time point is recorded, which is the failure of the test sample. Time to Failure (TTF), based on the failure time TTF value of a large number of samples, the actual service life (lifetime) of the dielectric layer corresponding to the tested structure under general working conditions can be calculated through the model, so as to predict the interlayer dielectric under test. reliability is evaluated.

It can be seen that the above-mentioned embodiments of the present application can realize the basic function of monitoring metal dielectric defects in the production line, and compared with the traditional inter-metal dielectric breakdown test structure, in the same area, the new inter-metal dielectric breakdown test The metal density of the structure has been reduced to 55% of the original, but the effective side length of the metal has not been reduced and is basically the same as before. The probability of catching abnormalities in the production line has basically not changed. Because this structure reduces the metal density, the thermal stress generated during subsequent laser cutting is smaller, and the generated heat is not easily conducted to the inside of the chip. The low k material inside the chip is not easily delamination due to CTE mismatch.

The above embodiments only illustrate the principles and effects of the present application, but are not used to limit the present application. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in this application shall still be covered by the claims of this application.

Claims (18)

1. A test structure, characterized by including: At least one first metal pad is coupled to a high-level voltage; At least one second metal pad is coupled to a low-level voltage, each second metal pad is alternately arranged with the first metal pad, and the adjacent first metal pad and the second The interlayer dielectric is accommodated between the metal pads; Multiple test layers are fixed in the interlayer dielectric between the adjacent first metal pads and the second metal pads. Each layer of the test layer includes: first test layers arranged at alternating intervals. The metal block and the second test metal block; Wherein, the first test metal block is coupled to the first metal pad, and the second test metal block is coupled to the second metal pad. 2. The test structure according to claim 1, wherein the number of the first metal bonding pads and the number of the second metal bonding pads are the same or different. 3. The test structure according to claim 1, wherein in at least part of the test layer, the number of the first test metal blocks and the number of the second test metal blocks are the same or different. 4. The test structure according to claim 2, wherein the number of the first metal bonding pads is N, and the number of the second metal bonding pads is N+1; or, the number of the first metal bonding pads is N+1. The number of metal bonding pads is N, the number of the second metal bonding pads is N, and N is an integer greater than or equal to 1; or, the number of the first metal bonding pads is N+1, and the number of the second metal bonding pads is N+1. The number of two metal bonding pads is N, and N is an integer greater than or equal to 1. 5. The test structure according to claim 3, characterized in that, in at least part of the test layer, the number of the first test metal blocks is M, and the number of the second test metal blocks is M+1. ; Or, the number of the first test metal blocks is M, and the number of the second test metal blocks is M; or, the number of the first test metal blocks is M+1, and the second test metal blocks The number of test metal blocks is M, and M is an integer greater than or equal to 1. 6. The test structure according to claim 3, characterized in that the number of the first test metal blocks is M, the number of the second test metal blocks is M, and in at least one test layer, The test metal block adjacent to the first metal bonding pad is a second test metal block, and the test metal block adjacent to the second metal bonding pad is a first test metal block. 7. The test structure according to claim 1, characterized in that, in the same test layer, all the first test metal blocks have the same length, and/or all the second test metal blocks have the same length. . 8. The test structure according to claim 1, characterized in that each test layer includes at least two first test metal blocks with different lengths, and/or each test layer includes at least two second test metal blocks with different lengths. Test the metal block. 9. The test structure according to claim 1, characterized in that all the first test metal blocks and the second test metal blocks have the same length, and in two adjacent test layers, the first test metal block has the same length. A test metal block is staggered with the second test metal block. 10. The test structure according to claim 1, wherein in each test layer, the length of the K first test metal blocks is the first length, and the length of the N-K first test metal blocks is the second length, K is a positive integer less than or equal to N/2, and N is the number of first test metal blocks; At least one first test metal block of the second length is spaced between the K first test metal blocks of the first length. 11. The test structure according to claim 1, wherein the length of the second test metal block is different from the length of the first test metal block. 12. The test structure according to claim 1, wherein each test layer further includes: A first metal layer and a second metal layer. The first metal layer includes a first connector for electrically connecting to the first test metal block. The second metal layer includes a first connector for electrically connecting to the first test metal block. The two test metal blocks are electrically connected to the second connector. 13. The test structure according to any one of claims 1 to 12, characterized in that the spacing between the adjacent first test metal blocks and the second test metal blocks is the same or different. 14. The test structure according to any one of claims 1 to 12, wherein the multi-layer test layer is a top metal layer of a semiconductor device, and/or the thickness of each test layer is greater than or equal to 3 microns. 15. A semiconductor device, characterized by comprising a substrate, a semiconductor structure formed on the substrate, and the test structure according to any one of claims 1-14. 16. An electronic product, characterized by comprising a housing, multiple functional hardware and the semiconductor device as claimed in claim 15. 17. A semiconductor wafer, characterized in that it includes a wafer panel, and a plurality of semiconductor devices according to claim 15 are formed in the wafer panel. 18. A method for conducting intermetallic dielectric breakdown testing using the test structure according to any one of claims 1 to 14, characterized in that it includes: Write a high level voltage to the first metal welding pad and the first test metal block in each test layer, and write a low level voltage to the second metal welding pad and the second test metal block in each test layer. level voltage; The test structure is used to monitor the stability of the metal interconnection medium of the production line.