CN1171311C - Semiconductor package - Google Patents

Abstract

A semiconductor package with a concave part on a lead frame comprises the lead frame, a plurality of chips, a packaging colloid and a cover plate for sealing. The lead frame has a concave part on the part where the lead welding area is connected with the packaging colloid, so that after the resin mold flow for forming the packaging colloid flows into the concave part during molding, the speed of absorbing the heat of the packaging mold is increased due to the shallow flow channel, the viscosity is increased, the flow speed is reduced, the resin mold flow does not overflow the glue on the lead welding area and the chip bonding area, and the overflowing glue does not need to be removed, thereby simplifying the packaging manufacturing process, reducing the manufacturing cost and improving the quality of chip bonding and lead welding.

Description

semiconductor package

The invention relates to a manufacturing method of a semiconductor package, in particular to a semiconductor package for encapsulating a chip in an encapsulant with a slot, and the encapsulant has a cover to airtightly cover the slot The method of making the package.

In order to meet the needs of different types of electronic products, semiconductor packages (Semiconductor Package) have different structures. One of the common ones is Image Sensor Package, such as EP-ROM or CMOS that can be erased by ultraviolet rays. The structure of this image sensor package is to seal a lead frame in a potting compound with a slot, make the chip bond to the chip seat exposed in the slot of the lead frame, and then electrically connect the lead frame with a wire. The guide pins connecting the chip and the lead frame are exposed to the inner guide pins in the slot, so that the chip is electrically connected to the outside through the guide pins, and finally the slot is covered with a transparent cover sheet, so that The wafer is hermetically isolated from the outside world.

Due to the particularity of the structure of this known image sensing package, it causes many problems in the packaging and manufacturing process and affects the yield and reliability of the finished product. Several improved manufacturing processes have been proposed to solve the manufacturing process. on the question. U.S. Patent No. 5,070,041 "Method of Removing Glue Overflow from a Coated Lead Frame Using a Solvent" discloses a method for removing the overflow glue on the lead frame without damaging the encapsulant and improving the contact between the lead frame and the lead frame. The packaging process for the electrical connectivity between chips. The U.S. patent is to coat a layer of organic polymer substance on the part of a lead frame that is not covered by the encapsulation compound after molding, and then partially cover the coated lead frame with encapsulation resin to form an encapsulation compound. and forming a groove on the place coated with the polymer substance, and immersing the encapsulation colloid coated with the lead frame in a solvent for dissolving the organic polymer substance layer, so as to remove the organic polymer substance layer , and then adhere and electrically connect a chip to the part of the lead frame exposed in the slot, and then use a cover sheet to hermetically seal the slot of the encapsulant to complete the encapsulation of the semiconductor package process.

Although this packaging manufacturing process can improve some shortcomings of the known image sensor packaging method, the steps of coating the organic polymer substance on the lead frame with the molding agent and dissolving it in the solvent after molding are not only complicated and complicated. It is time-consuming and causes an increase in manufacturing cost, and the solution produced by dissolving the organic polymer substance with a solvent will cause environmental pollution, which is not conducive to environmental protection, but if it is disposed of, it will increase additional costs. Thereby, the method for making of this U.S. patent still has many shortcomings to be solved.

An object of the present invention is to provide a semiconductor package with a lead frame having a concave portion, which can avoid glue overflow on the chip bonding area and the wire bonding area of the lead frame during the molding process.

Another object of the present invention is to provide a semiconductor package with a lead frame having a concave portion. After the molding process is completed, there is no need to remove overflowing glue, which can simplify the package manufacturing process, reduce manufacturing costs, and cause no environmental pollution.

In order to achieve the above and other objects of the present invention, the semiconductor package with a lead frame of the present invention having a concave portion includes a lead frame with a chip bonding area and a wire bonding area; a chip bonded to the chip bonding area of the lead frame ; a plurality of wires for electrically connecting the chip to the wire bonding area of the lead frame; the encapsulant partially covering the lead frame has a slot so that the chip bonding area and the lead frame can be bonded when the encapsulant is molded The wire soldering area is exposed in the slot; and a cover sheet is used to cover the slot, so that the chip and the wire are airtightly isolated from the outside; A recess is formed on the part where the encapsulation compound is connected, and at least one recess is formed on the part where the wire welding area and the encapsulation compound are in contact.

The concave portion on the lead frame can be formed by known stamping (stamping) or etching (Etching). When the resin mold used to form the encapsulant flows into the narrow space formed between the concave part and the inner wall of the mold for encapsulation, the flow rate is slowed down so that the glue does not overflow on the chip bonding area and the wire bonding area of the lead frame. . At the same time, in order to strengthen the effect of slowing down the flow velocity of the resin mold flow to the concave portion, the formation of the concave portion can be multi-staged.

In a preferred embodiment of the present invention, the lead frame is composed of a chip base and a plurality of guide pins. At this time, the upper surface of the wafer base forms a chip bonding area for the chip to stick to, and the recess is Formed on the periphery of the chip seat; each lead has an inner lead partially covered by the encapsulant and an outer lead exposed outside the encapsulant as a medium for the chip to be electrically connected to the outside world, and the upper surface of the inner lead is adjacent to the The part of the chip is formed as a wire welding area for the termination of the wire, and the wire welding area is not covered by the encapsulant, but exposed in the slot of the encapsulant. The above-mentioned concave portion is provided at the junction of the surface where the encapsulating gel coats the portion, but a concave portion is also provided on the end of the inner lead relative to the wafer seat.

In another preferred embodiment of the present invention, the lead frame is only composed of a plurality of guide pins, that is, the chip is directly bonded to the inner guide using the inner guide pin of the guide pin as a supporting structure (Supporting Carrier). Foot, to reduce the contact area between the chip and the lead frame, to avoid the occurrence of delamination (Delamination). Therefore, in this embodiment, on the upper surface of the inner lead pin of each lead pin, the direction from the inner end of each lead pin towards the direction of the outer lead pin is successively formed as a chip bonding area for bonding a chip, for wire welding. The wire bonding area, and the colloid covering area covered by the encapsulation gel; at this time, the concave part of the chip bonding area is set on the end of the inner lead, and the concave part of the wire bonding area is formed on the inner lead Above the junction of the wire welding area and the colloid coverage area.

The characteristics and effects of the present invention will be further described in detail below with reference to the accompanying drawings.

1 is a sectional view of a lead frame according to a first embodiment of the present invention;

Fig. 2 is a cross-sectional view of the lead frame of the first embodiment of the present invention inserted into the packaging mold;

3 is a cross-sectional view of the lead frame partially covered by the encapsulant according to the first embodiment of the present invention;

4 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention;

5 is a cross-sectional view of a lead frame placed in a packaging mold according to a second embodiment of the present invention;

6 is a cross-sectional view of a lead frame according to a third embodiment of the present invention; and

7 is a cross-sectional view of a lead frame according to a fourth embodiment of the present invention.

Explanation of icon symbols

1, 1a, 1b, 1c lead frame 10 chip holders

11, 11a, 11b guide pins 101, 101c, 117b chip bonding area

102 Perimeter

103, 103a, 103c, 115, 115a, 115b, 115c, 116a, 116b

concave part

111, 111a, 111b outer guide pin 112, 112a, 112b inner guide pin

113, 113a, 113b ends 114 wire welding area

114a, 114b, 114c welding area 2 mold

20 upper mold 21 lower mold

200 bumps 3 encapsulants

4 Chip 5, 5b gold wire

6 cover

FIG. 1 is a cross-sectional view of a lead frame used in a semiconductor package according to a first embodiment of the present invention.

As shown in FIG. 1 , the lead frame 1 includes a wafer holder 10 and a plurality of guide pins 11 . The upper surface of the wafer holder 10 is formed as a wafer attachment area 101 for wafer attachment, and a concave portion 103 is recessed on its peripheral edge 102 . As for the guide pins 11, each has an outer guide pin 111 and an inner guide pin 112 connected thereto, and the upper surface of each inner guide pin 112 is formed with a supply wire at a suitable position between the end 113 and the outer guide pin 111. The soldered wire land 114, and the upper surface of the wire land 114 and the inner lead pin 112 is subsequently used to partially cover the lead frame 1 with the encapsulant (will be described in detail later) to cover the corresponding position. A concave portion 115 is recessed on the joint. In addition, the recesses 103, 115 can be formed by known punching (Stamping), etching (Etching) or other suitable methods, without specific limitations; and the depth is preferably between 0.04 to 0.15 mm, and the width is 0.5 to 0.5 mm. 2.0mm between.

Referring to FIG. 2 , the lead frame 1 is first put into a packaging mold 2 for molding to form an encapsulant 3 (shown in FIG. 3 ) for partially covering the lead frame 1 . After the upper mold 20 and the lower mold 21 of the mold 2 are clamped, the chip bonding area 101 and the wire welding area 114 of the lead frame 1 are respectively contacted to the upper mold 20 to form the slot 30 on the encapsulant 3 (refer to The bottom surface of the bump 200 in FIG. 3 ) prevents the encapsulation resin used to form the encapsulant 3 from covering the die bonding area 101 and the wire bonding area 114 of the lead frame 1 during molding. When the molten packaging resin flow flows into the recesses 103 and 115 between the lead frame 1 and the bump 200 of the upper mold 20, the resin flow flowing into the recesses 103 and 115 will be accelerated due to the narrowing of the flow channel. Absorb the heat of the mold 2, increase the viscosity and slow down the flow rate, so that the overflow of the resin mold can be avoided on the chip bonding area 101 and the wire welding area 114 of the lead frame, thereby eliminating the need to remove the overflow after the molding is completed. Simplify the packaging manufacturing process, reduce manufacturing costs, and ensure the quality of Die Bond and Wire Bond operations.

Referring to FIG. 3 , the lead frame 1 of the first embodiment of the present invention is partially covered by the molded encapsulant 3 after the aforementioned molding process is completed, so that the chip bonding area 101 and the wire bonding area 114 are respectively exposed on the The groove 30 formed by the bump 200 is convenient for the implementation of the mounting and wire bonding operations. At the same time, the outer lead 111 of the lead frame 1 will expose the packaging compound 3, and the rest of the lead frame 1 Then they are all covered by the encapsulating colloid 3 .

As shown in Figure 4, after the encapsulation compound 3 is molded, the chip 4 is glued on the chip bonding area 101 exposed in the groove 30 of the lead frame 1, and the adhesive medium for bonding the two can use known silver. Glue (Silver Paste) or adhesive sheet (Adhesive Tape). Afterwards, the chip 4 is electrically connected to the inner lead 112 with the gold wire 5, so that the chip 4 is electrically connected to the outside through the outer lead 111, and the part where the inner lead 112 is connected to the gold wire 5 is soldered on the wire. District 114 on. Finally, a cover 6 is bonded to the encapsulant 3 with an adhesive such as epoxy resin or acrylic resin, so as to airtightly cover the slot 30 and the chip exposed in the slot 30 4 and the gold wire 5 are airtightly isolated from the outside; the cover 6 can be a transparent piece such as a quartz glass sheet or a plastic sheet, or an opaque sheet such as a colored glass sheet, a ceramic sheet or a colored plastic sheet. In this way, the packaging process of the semiconductor package according to the first embodiment of the present invention is completed.

As shown in FIG. 5 , it is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention. Its structure is substantially the same as the aforementioned first embodiment, the only difference lies in the structure of the lead frame. In the lead frame 1a of the second embodiment, a recess 116a is recessed on the end 113a of each guide pin 11a; the function of the recess 116a is also the same as that of the recesses 103a and 115a on the lead frame 1a, during the molding process When the encapsulation resin mold flow flows into the concave portion 116a, the viscosity will be increased to slow down its flow rate, so that the resin mold flow will not overflow to the wire welding area 114a of the inner lead 112a, so as to further ensure that the wire welding area 114a is not tight. Infected.

FIG. 6 is a cross-sectional view of a semiconductor package according to a third embodiment of the present invention. The structure of the semiconductor package of the third embodiment is substantially the same as that of the first embodiment, the only difference lies in the lead frame used. The lead frame 1b of the third embodiment does not have a chip holder, but only consists of a plurality of guide pins 11b. Each guide pin 11b also has an outer guide pin 111b and an inner guide pin 112b connected thereto, and the upper surface of each inner guide pin 112b is sequentially formed with holes for wafer bonding from its end 113b toward the direction of the outer guide pin 111b. Chip bonding area 117b, wire bonding area 114b for wire bonding, and colloid covering area 118b covered by encapsulation gel; at the same time, the end 113b is provided with a concave portion 116b to prevent the encapsulation resin from overflowing during the molding process To the chip sticking area 117b, and the inner lead 112b is provided with a recess 115b at the junction of the wire welding area 114b and the colloid covering area 118b, so as to avoid overflow on the wire welding area 114b during the molding process. glue. When sticking the chip 4b on the chip bonding area 117b of the inner lead 112b, and welding the gold wire 5b to electrically connect the chip 4b and the wire bonding area 114b of the inner lead 112b, the former bonding can be ensured quality and the latter welding quality.

FIG. 7 is a cross-sectional view of a semiconductor package according to a fourth embodiment of the present invention. The structure of the semiconductor package of the fourth embodiment is substantially the same as that of the first embodiment, the only difference lies in the used lead frame. The recesses 103c and 115c on the lead frame 1c used in the fourth embodiment are treated with multi-steps, that is, when the recesses 103c and 115c are formed, the depth has a step-like change from deep to shallow, so as to facilitate molding production During the process, the rate of heat absorption of the resin mold flow flowing into the recesses 103c and 115c is increased, and the flow rate must be further slowed down, so as to more effectively prevent the overflow of glue from occurring on the chip bonding area 101c and the wire bonding area 114c. .

The above-mentioned specific embodiments are only used to describe the characteristics and effects of the present invention in detail, and are not intended to limit the scope of the present invention. Without departing from the technical scope and spirit disclosed in the present invention, any implementation of the present invention, etc. Effective changes and modifications are still covered by the scope of the patent application disclosed in the present invention.

Claims (11)

1. A semiconductor package, comprising: A lead frame with a chip bonding area and a wire bonding area; a wafer attached to the wafer attachment area; a plurality of conductive elements for electrically connecting the chip to the wire bonding pads of the leadframe; an encapsulant covering the lead frame, which has a slot for exposing the chip bonding area and the wire bonding area of the lead frame; and a cover sheet for sealing the groove of the encapsulant, so as to airtightly isolate the chip and the conductive element from the outside; It is characterized by: A recess is formed at the part where the chip bonding area of the lead frame is in contact with the encapsulant, and at least one recess is formed at the part where the wire bonding area is in contact with the encapsulant, and the depth of the recess is between 0.04 mm and 0.15 mm. between. 2. The semiconductor package of claim 1, wherein the recess has a width between 0.5 and 2.0 mm. 3. The semiconductor package of claim 1, wherein the recess is formed in a stamping manner. 4. The semiconductor package of claim 1, wherein the recess is formed by etching. 5. The semiconductor package as claimed in claim 1 , wherein the lead frame is composed of a chip base and a plurality of guide pins, the upper surface of the wafer base is formed as the die bonding area, and the guide pins are adjacent to the chip The upper surface of the seat is formed as a wire bonding area. 6. The semiconductor package as claimed in claim 1, wherein the lead frame is composed of a plurality of guide pins, so that the upper surface of each guide pin forms the chip bonding area and the wire bonding area sequentially from its inner end. . 7. The semiconductor package according to claim 1, wherein a bottom surface of the concave portion is flat. 8. The semiconductor package as claimed in claim 1, wherein a bottom surface of the recess is stepped. 9. The semiconductor package as claimed in claim 1, wherein the cover sheet is a transparent sheet. 10. The semiconductor package as claimed in claim 1, wherein the cover sheet is an opaque sheet. 11. The semiconductor package of claim 1, wherein the conductive element is a gold wire.

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