CN117081513B - Gain amplifying method and circuit for voltage-controlled oscillator, phase-locked loop and clock chip - Google Patents
Gain amplifying method and circuit for voltage-controlled oscillator, phase-locked loop and clock chip Download PDFInfo
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- CN117081513B CN117081513B CN202311331073.4A CN202311331073A CN117081513B CN 117081513 B CN117081513 B CN 117081513B CN 202311331073 A CN202311331073 A CN 202311331073A CN 117081513 B CN117081513 B CN 117081513B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a gain amplifying method and circuit of a voltage-controlled oscillator, a phase-locked loop and a clock chip, wherein the method comprises the following steps: inputting control voltage into an operational amplifier with offset voltage, wherein the positive phase input end of the operational amplifier with offset voltage is connected with the control voltage, the negative phase input end of the operational amplifier with offset voltage is grounded through a second resistor, the output end of the operational amplifier with offset voltage is grounded through a first resistor and a second resistor in sequence, and the output end of the operational amplifier with offset voltage generates target voltage; and controlling the tuning frequency of the voltage-controlled oscillator through the target voltage generated by the operational amplifier with the offset voltage, wherein the value of the offset voltage comprises the voltage corresponding to the minimum tuning frequency of the voltage-controlled oscillator. Compared with the common subtracting circuit scheme, the invention does not need an extra driving circuit and driving current, does not consume extra area and power consumption, can reduce noise introduced by circuit links, improves the performance of the phase-locked loop, and saves cost and power consumption.
Description
Technical Field
The present invention relates to the field of digital data technology, and in particular, to a gain amplifying method and circuit for a voltage-controlled oscillator, a phase-locked loop, and a clock chip.
Background
In an analog phase-locked loop design, the gain of a Voltage-controlled oscillator (VCO) (Voltage-Controlled Oscillator)K VCO If designed to be smaller, then at the same control voltageV cont The frequency range that can be covered in the range is smaller. To use smaller in designGain of (2)K VCO To realize the desired control loop and solve the problem of small coverage area, a method of combining a coarse tuning slow loop and a fine tuning fast loop is often adopted. Wherein the gain is used for slow loop amplificationK VCO Is usually required to be dependent on the control voltageV cont To adjust the amplified input-output curve. At present, the common subtracting circuit scheme needs an additional driving circuit and driving current, increases noise introduced by a circuit link, reduces the performance of a phase-locked loop, and increases cost and power consumption.
Disclosure of Invention
In order to solve the above problems, the present invention provides a gain amplifying method and circuit for a voltage-controlled oscillator, a phase-locked loop and a clock chip, which do not require additional driving circuits, do not consume additional area and power consumption, and do not increase additional noise.
The technical scheme adopted by the invention is as follows:
a voltage controlled oscillator gain amplification method comprising the steps of:
s1, controlling the voltageV cont An operational amplifier with offset voltage is input, and a non-inverting input end of the operational amplifier with offset voltage is connected with a control voltageV cont The negative phase input end is grounded through the second resistor, the output end is grounded through the first resistor and the second resistor in turn, and the output end generates a target voltageV O ；
S2, generating a target voltage through the operational amplifier with the offset voltageVoAnd controlling the tuning frequency of the voltage-controlled oscillator, wherein the value of the offset voltage comprises the voltage corresponding to the minimum tuning frequency of the voltage-controlled oscillator.
Further, the operational amplifier with offset voltage comprises an NMOS input stage circuit, wherein the NMOS input stage circuit comprises a current source, a first NMOS tube, a second NMOS tube, a third resistor and a fourth resistor, the grid electrode of the first NMOS tube is used as a positive phase input end, the grid electrode of the second NMOS tube is used as a negative phase input end, the source electrode of the first NMOS tube or the second NMOS tube is connected with the current source through the third resistor, and the current source is grounded through the fourth resistor;
the calculating method of the offset voltage comprises the following steps:
V OS =I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS in order to offset the voltage of the power supply,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
Further, the operational amplifier with offset voltage comprises a PMOS input stage circuit, wherein the PMOS input stage circuit comprises a current source, a first PMOS tube, a second PMOS tube, a third resistor and a fourth resistor, the grid electrode of the first PMOS tube is used as a positive phase input end, the grid electrode of the second PMOS tube is used as a negative phase input end, the source electrode of the first PMOS tube or the second PMOS tube is connected with the current source through the third resistor, and the current source is grounded through the fourth resistor;
the calculating method of the offset voltage comprises the following steps:
V OS =I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS in order to offset the voltage of the power supply,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
Further, the target voltageVoThe calculation method of (1) comprises the following steps:
V O =((R 1 +R 2 )/R 2 )*(V cont -V OS )
wherein,R 1 is the resistance value of the first resistor,R 2 is the resistance value of the second resistor,V OS is a offset voltage.
A voltage controlled oscillator gain amplification circuit comprising:
the operational amplifier with offset voltage, the first resistor and the second resistor, wherein the non-inverting input end of the operational amplifier with offset voltage is connected with the control voltageV cont The negative phase input end is grounded through the second resistor, the output end is grounded through the first resistor and the second resistor in turn, and the output end generates a target voltageV O And controlling the tuning frequency of the voltage-controlled oscillator, wherein the value of the offset voltage comprises the voltage corresponding to the minimum tuning frequency of the voltage-controlled oscillator.
Further, the operational amplifier with offset voltage comprises an NMOS input stage circuit, wherein the NMOS input stage circuit comprises a current source, a first NMOS tube, a second NMOS tube, a third resistor and a fourth resistor, the grid electrode of the first NMOS tube is used as a non-inverting input end, and the drain electrode of the first NMOS tube is connected with the current source through the third resistor; the grid electrode of the second NMOS tube is used as a negative phase input end, and the drain electrode of the second NMOS tube is connected with a current source; the current source is grounded through a fourth resistor;
the calculating method of the offset voltage comprises the following steps:
Vos=I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS is a detuned voltage, takes a positive or negative value,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
Further, the operational amplifier with offset voltage comprises a PMOS input stage circuit, wherein the PMOS input stage circuit comprises a current source, a first PMOS tube, a second PMOS tube, a third resistor and a fourth resistor, the grid electrode of the first PMOS tube is used as a non-inverting input end, and the source electrode is connected with the current source through the third resistor; the grid electrode of the second PMOS tube is used as a negative phase input end, and the source electrode of the second PMOS tube is connected with a current source; the current source is grounded through a fourth resistor;
the calculating method of the offset voltage comprises the following steps:
V OS =I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS is a detuned voltage, takes a positive or negative value,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
Further, the target voltageVoThe calculation method of (1) comprises the following steps:
V O =((R 1 +R 2 )/R 2 )*(V cont -V OS )
wherein,R 1 is the resistance value of the first resistor,R 2 is the resistance value of the second resistor,V OS is a offset voltage.
A phase-locked loop comprises the gain amplifying circuit of the voltage-controlled oscillator, a phase detector, a low-pass filter and a voltage-controlled oscillator which are electrically connected in sequence.
A clock chip comprising the phase-locked loop described above, the phase-locked loop configured as a multi-loop controlled phase-locked loop.
The invention has the beneficial effects that:
compared with the common subtracting circuit scheme, the invention does not need an extra driving circuit and driving current, does not consume extra area and power consumption, can reduce noise introduced by circuit links, improves the performance of the phase-locked loop, and saves cost and power consumption.
Drawings
FIG. 1 is a schematic diagram of a phase locked loop;
FIG. 2 is a schematic diagram of a gain curve of a voltage controlled oscillator;
FIG. 3 is a schematic diagram of a linear model of a phase locked loop;
FIG. 4 is a schematic diagram of a dual-loop voltage controlled oscillator;
FIG. 5 is a schematic diagram of a subtracting circuit consisting of common operational amplifiers;
FIG. 6 is a schematic diagram of a subtraction amplifying circuit without quiescent current;
FIG. 7 is an operational amplifier circuit with additional drive circuitry;
FIG. 8 is a schematic diagram of a voltage controlled oscillator gain amplification circuit;
FIG. 9 is a schematic diagram of an NMOS input stage circuit;
FIG. 10 is a schematic diagram of a PMOS input stage circuit;
FIG. 11 is a schematic diagram of input/output curves corresponding to different resistance values.
Reference numerals: the device comprises a PD-phase detector, an LPF-low pass filter, a VCO-voltage controlled oscillator, a PFD-phase frequency detector, a CP-charge pump and an AMP-operational amplifier; NMOS (N-channel Metal oxide semiconductor) 1 -a first NMOS transistor, NMOS 2 -a second NMOS transistor, PMOS 1 -a first PMOS transistor, PMOS 2 -a second PMOS tube;K VCO the gain of the optical fiber is controlled,ω out the output angular frequency is chosen to be the same,V cont the control voltage is controlled so that the voltage,V C a second control voltage which is set to be equal to the first control voltage,V ref the reference voltage is a reference voltage which,V OS -an offset voltage of the current source,V O the target voltage is set to be at the target voltage,I 1 the first current is a first current which,I 2 -a second current.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
Fig. 1 shows a phase locked loop comprising a phase detector PD, a low pass filter LPF and a voltage controlled oscillator VCO, wherein the gain curve of the voltage controlled oscillator VCO is shown in fig. 2, and a control voltage is inputV cont Outputs a same control voltageV cont The related oscillation frequency isω out And has:
ω out =ω 0 +K VCO *V cont
wherein,ω out in order to output the angular frequency of the light,ω 0 for the free-running angular frequency of oscillation,K VCO in order for the gain to be a function of,V cont for controlling the voltage.
FIG. 3 shows a linearized charge pump phase locked loop model, gainK VCO As a key parameter of the voltage controlled oscillator VCO is presented to the loop interior.
As can be seen from fig. 2, if the gain isK VCO Smaller, the overall frequency range may be smaller. To achieve gainK VCO Smaller, at the same time output angular frequencyω out Is sufficient and is typically implemented with a multi-loop voltage controlled oscillator VCO.
Fig. 4 shows a dual-loop VCO, control voltageV cont The output angular frequency at low frequency is obtained by passing through an amplifying circuit (X2 in the figure) and then a low-pass filter LPF:
ω out =V cont *K VCO +V C *K VCO =V cont *K VCO +2*V cont *K VCO =K VCO *3*V cont
wherein,V C is the second control voltage. The same control voltage is realized by adjusting the amplification factor of the amplifying circuitV cont Variable range, wider output angular frequencyω out 。
Based on the gain curve of fig. 2, the amplifying circuit needs to subtract a fixed voltage before amplifying, so that the amplifying circuit with subtraction is generally needed for implementation. An amplifying circuit with subtraction is shown in fig. 5, in whichV p =V cont =V n ，V O /R 1 =(V p -V ref ) R2, ifR 1 =2R，R 2 =r, then target voltageV O =(R 1 /R 2 )*(V cont -V ref )=2*(V cont -V ref ) Due to the second currentI 2 Is the presence of reference voltageV ref Must have driving capability because of the second currentI 2 The magnitude of (2) will follow the control voltageV cont Is changed by a change in (a).
As shown in fig. 7, the reference voltage of fig. 6V ref The generation needs to be implemented by an extra driving circuit, which has two disadvantages: (1) consume additional current and area; (2) operational amplifier AMP1 introduces additional noise.
As shown in fig. 8, the present embodiment provides a gain amplifying method and circuit for a voltage-controlled oscillator, which uses a band offset voltageV OS Control voltage for implementing subtraction and amplification by operational amplifier AMP of (a)V cont Wherein the target voltage is:
V O =((R 1 +R 2 )/R 2 )*(V cont -V OS )
wherein,R 1 is the resistance value of the first resistor,R 2 the second resistance value.
Second resistor of the present embodimentR 2 The ground connection does not require an additional driving circuit, does not consume additional area and power consumption, and does not add additional noise.
Specifically, the gain amplifying circuit of the voltage controlled oscillator of the present embodiment includes a gain amplifier with offset voltageV OS An operational amplifier AMP, a first resistorR 1 And a second resistorR 2 Wherein the non-inverting input terminal of the operational amplifier AMP is connected to the control voltageV cont The negative phase input end passes through the second resistorR 2 The output end is grounded and sequentially connected with the first resistorR 1 And a second resistorR 2 Grounded, and the output terminal generates a target voltageV O The tuning frequency of the voltage controlled oscillator VCO is controlled,offset voltageV OS The value of (2) includes the voltage corresponding to the minimum tuning frequency of the voltage controlled oscillator VCO.
Accordingly, the gain amplification method of the voltage controlled oscillator of the present embodiment includes the following steps:
s1, controlling the voltageV cont Input band offset voltageV OS An operational amplifier AMP of (2) having a non-inverting input terminal connected to a control voltageV cont The negative phase input end passes through the second resistorR 2 The output end is grounded and sequentially connected with the first resistorR 1 And a second resistorR 2 Grounded, and the output terminal generates a target voltageV O ；
S2. Target voltage generated by operational amplifier AMPV O Controlling tuning frequency, offset voltage of VCOV OS The value of (2) includes the voltage corresponding to the minimum tuning frequency of the voltage controlled oscillator VCO.
Fig. 9 and 10 show two implementations of the offset op-amp of the present embodiment, where the PMOS and NMOS input stage circuits correspond to different operating voltages, respectively.
The NMOS input stage circuit comprises a current source and a first NMOS tube NMOS 1 A second NMOS transistor NMOS 2 Third resistorR 3 And a fourth resistorR 4 A first NMOS tube NMOS 1 A gate of the second NMOS transistor is used as a non-inverting input end 2 A grid electrode of the first NMOS transistor is used as a negative phase input end 1 Or a second NMOS transistor NMOS 2 The source electrode of (a) passes through a third resistorR 3 A current source is connected and passes through the fourth resistorR 4 And (5) grounding. Wherein, when the first NMOS tube NMOS 1 The source electrode of (a) passes through a third resistorR 3 When the current source is connected, as shown in FIG. 9, the offset voltage is adjustedV OS The value is positive; when the second NMOS tube NMOS 2 The source electrode of (a) passes through a third resistorR 3 When the current source is connected, the offset voltage is adjustedV OS The value is negative.
The PMOS input stage circuit comprises a current source, a first PMOS tube and a PMOS 1 PMOS of the second PMOS tube 2 Third resistorR 3 And a fourth resistorR 4 A first PMOS tube PMOS 1 The grid electrode of the second PMOS tube is used as a positive input end 2 The grid electrode of the first PMOS tube is used as a negative phase input end 1 Or a second PMOS tube PMOS 2 The source electrode of (a) passes through a third resistorR 3 A current source is connected and passes through the fourth resistorR 4 And (5) grounding. When the first PMOS tube is PMOS 1 The source electrode of (a) passes through a third resistorR 3 When the current source is connected, as shown in fig. 10, the offset voltage is adjustedV OS The value is negative; when the second PMOS tube is PMOS 2 The source electrode of (a) passes through a third resistorR 3 When the current source is connected, the offset voltage is adjustedV OS The value is positive.
Preferably, the calculating method of the offset voltage may be:
Vos=I 1 *R 3 =(V ref /R 4 )*R 3
wherein,I 1 the current provided to the current source is provided,V ref is the reference voltage.
Fig. 11 shows input/output curves corresponding to different resistance values.
Example 2
This example is based on example 1:
the present embodiment provides a phase locked loop, including the voltage controlled oscillator gain amplifying circuit of embodiment 1, further including a phase detector PD, a low pass filter LPF and a voltage controlled oscillator VCO electrically connected in sequence.
Example 3
This example is based on example 2:
the present embodiment provides a clock chip comprising the phase-locked loop of embodiment 2 configured as a multi-loop controlled phase-locked loop.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (10)
1. A method for amplifying gain of a voltage controlled oscillator, comprising the steps of:
s1, outputting control voltage from a low-pass filter in a phase-locked loop circuitV cont An operational amplifier with offset voltage is input, and a non-inverting input end of the operational amplifier with offset voltage is connected with a control voltageV cont The negative phase input end is grounded through the second resistor, the output end is grounded through the first resistor and the second resistor in turn, and the output end generates a target voltageV O ；
S2, generating a target voltage through the operational amplifier with the offset voltageV O And controlling the tuning frequency of the voltage-controlled oscillator, wherein the value of the offset voltage comprises the voltage corresponding to the minimum tuning frequency of the voltage-controlled oscillator.
2. The gain amplification method of a voltage controlled oscillator according to claim 1, wherein the operational amplifier with offset voltage comprises an NMOS input stage circuit, the NMOS input stage circuit comprises a current source, a first NMOS transistor, a second NMOS transistor, a third resistor and a fourth resistor, a gate of the first NMOS transistor is used as a positive phase input terminal, a gate of the second NMOS transistor is used as a negative phase input terminal, a source of the first NMOS transistor is connected with the current source through the third resistor and a source of the second NMOS transistor is directly connected with the current source, or a source of the second NMOS transistor is connected with the current source through the third resistor and a source of the first NMOS transistor is directly connected with the current source; the current magnitude of the current source is controlled by a reference voltage acting on a fourth resistor;
the calculating method of the offset voltage comprises the following steps:
V OS =I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS in order to offset the voltage of the power supply,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
3. The gain amplification method of a voltage controlled oscillator according to claim 1, wherein the operational amplifier with offset voltage comprises a PMOS input stage circuit, the PMOS input stage circuit comprises a current source, a first PMOS transistor, a second PMOS transistor, a third resistor and a fourth resistor, a gate of the first PMOS transistor is used as a positive phase input terminal, a gate of the second PMOS transistor is used as a negative phase input terminal, a source of the first PMOS transistor is connected with the current source through the third resistor and a source of the second PMOS transistor is directly connected with the current source, or a source of the second PMOS transistor is connected with the current source through the third resistor and a source of the first PMOS transistor is directly connected with the current source; the current magnitude of the current source is controlled by a reference voltage acting on a fourth resistor;
the calculating method of the offset voltage comprises the following steps:
V OS =I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS in order to offset the voltage of the power supply,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
4. The method of gain amplification of a voltage controlled oscillator of claim 1, wherein the target voltageVoThe calculation method of (1) comprises the following steps:
V O =((R 1 +R 2 )/R 2 )*(V cont -V OS )
wherein,R 1 is the resistance value of the first resistor,R 2 is the resistance value of the second resistor,V OS is a offset voltage.
5. A voltage controlled oscillator gain amplification circuit comprising:
the operational amplifier with offset voltage, the first resistor and the second resistor, wherein the non-inverting input end of the operational amplifier with offset voltage is connected with the control voltage output by the low-pass filter in the phase-locked loop circuitV cont The negative phase input end is grounded through the second resistor, the output end is grounded through the first resistor and the second resistor in turn, and the output end generates a target voltageV O And controlling the tuning frequency of the voltage-controlled oscillator, wherein the value of the offset voltage comprises the voltage corresponding to the minimum tuning frequency of the voltage-controlled oscillator.
6. The gain amplifying circuit of the voltage controlled oscillator according to claim 5, wherein the operational amplifier with offset voltage comprises an NMOS input stage circuit, the NMOS input stage circuit comprises a current source, a first NMOS transistor, a second NMOS transistor, a third resistor and a fourth resistor, the gate of the first NMOS transistor is used as a positive phase input terminal, the gate of the second NMOS transistor is used as a negative phase input terminal, the source of the first NMOS transistor is connected with the current source through the third resistor and the source of the second NMOS transistor is directly connected with the current source, or the source of the second NMOS transistor is connected with the current source through the third resistor and the source of the first NMOS transistor is directly connected with the current source; the current magnitude of the current source is controlled by a reference voltage acting on a fourth resistor;
the calculating method of the offset voltage comprises the following steps:
Vos=I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS in order to offset the voltage of the power supply,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref as reference electricityPressing.
7. The gain amplifying circuit of the voltage controlled oscillator according to claim 5, wherein the operational amplifier with offset voltage comprises a PMOS input stage circuit, the PMOS input stage circuit comprises a current source, a first PMOS transistor, a second PMOS transistor, a third resistor and a fourth resistor, a gate of the first PMOS transistor is used as a positive phase input end, a gate of the second PMOS transistor is used as a negative phase input end, a source of the first PMOS transistor is connected with the current source through the third resistor and a source of the second PMOS transistor is directly connected with the current source, or a source of the second PMOS transistor is connected with the current source through the third resistor and a source of the first PMOS transistor is directly connected with the current source; the current magnitude of the current source is controlled by a reference voltage acting on a fourth resistor;
the calculating method of the offset voltage comprises the following steps:
V OS =I 1 *R 3 =(V ref /R 4 )*R 3
wherein,V OS in order to offset the voltage of the power supply,I 1 the current provided to the current source is provided,R 3 is the resistance value of the third resistor,R 4 for the resistance value of the fourth resistor,V ref is the reference voltage.
8. The voltage controlled oscillator gain amplification circuit of claim 5, wherein the target voltageVoThe calculation method of (1) comprises the following steps:
V O =((R 1 +R 2 )/R 2 )*(V cont -V OS )
wherein,R 1 is the resistance value of the first resistor,R 2 is the resistance value of the second resistor,V OS is a offset voltage.
9. A phase locked loop comprising a voltage controlled oscillator gain amplifying circuit according to any of claims 5 to 8, further comprising a phase detector, a low pass filter and a voltage controlled oscillator electrically connected in sequence.
10. A clock chip comprising the phase-locked loop of claim 9, the phase-locked loop configured as a multi-loop controlled phase-locked loop.
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