CN114793108A - Duty cycle correction circuit and method, crystal oscillator circuit, and electronic equipment - Google Patents

Abstract

The present invention provides a duty cycle correction circuit and method, a crystal oscillator circuit and an electronic device. The duty cycle correction circuit includes an inverter chain, a third inverter and a feedback control module; the inverter chain includes an inverter The inverter group includes a first inverter, a second inverter, a first adjustment circuit, and a second adjustment circuit. The output end of the first inverter is connected to the input end of the second inverter. The first adjustment circuit The circuit is connected to the first inverter and the feedback control module, the second adjustment circuit is connected to the second inverter and the feedback control module; the third inverter is used for outputting the inverted signal of the output signal of the inverter chain to the feedback control module, The feedback control module is used for outputting the second voltage signal according to the output signal of the inverter chain and outputting the first voltage signal according to the output signal of the third inverter. The duty ratio correction circuit of the present invention is beneficial to achieve a better stable speed, and is beneficial to reduce the occupied area and power consumption of the circuit.

Description

Duty cycle correction circuit and method, crystal oscillator circuit, and electronic equipment

technical field

The present invention relates to the technical field of integrated circuits, and in particular, to a duty cycle correction circuit and method, a crystal oscillator circuit, and an electronic device.

Background technique

In the current electronic system, the crystal oscillator circuit is an indispensable circuit module as a reference clock source. As shown in Figure 1, the current crystal oscillator circuit usually includes a crystal oscillator, an amplifier circuit, and a square wave conversion circuit. Converted to a square wave signal.

However, due to the influence of PVT (Process Voltage and Temperature) characteristics, the current crystal oscillator circuit is prone to problems such as oscillation amplitude change and circuit operating point offset, which easily lead to the square wave signal output by the crystal oscillator circuit. The change of the duty cycle means that the duty cycle of the square wave signal output by the crystal oscillator circuit is relatively unstable, and it is difficult to directly use it in the design of a high-performance clock system.

The patent document with the publication number CN110957998A provides a circuit for accurately correcting the duty cycle of a clock signal, the circuit includes an inverter chain, a delay unit, a phase detection unit and a low-pass filter, and the input signal is adjusted through the inverter chain The duty cycle of the inverter chain, and the delay unit and the phase detection unit output an indication signal indicating whether the duty cycle of the output signal of the inverter chain reaches the target value. The indication signal can be output to the inverter after being filtered by a low-pass filter. The gate of a PMOS tube in the chain (the PMOS tube is connected between the power supply voltage VDD and an inverter), so as to realize the calibration of the duty cycle, but this method not only occupies a large area due to the use of a delay unit , the power consumption is high, and it is not conducive to achieving a better correction speed, and the circuit stabilization time is long.

SUMMARY OF THE INVENTION

Based on the above status quo, the main purpose of the present invention is to provide a duty cycle correction circuit and method, a crystal oscillator circuit, and an electronic device, which are conducive to achieving better stable speed and reducing circuit occupation area and power consumption.

To achieve the above purpose, the technical solution of the present invention provides a duty cycle correction circuit for a square wave clock signal, comprising an inverter chain, a third inverter and a feedback control module;

The inverter chain includes an inverter group, the inverter group includes a first inverter, a second inverter, a first adjustment circuit, and a second adjustment circuit, and the output of the first inverter The terminal is connected to the input terminal of the second inverter, and the first adjustment circuit is connected to the first inverter and the feedback control module to adjust the first voltage signal output by the feedback control module. The output signal of the first inverter, the size of the duty cycle of the output signal of the first inverter is negatively correlated with the size of the first voltage signal, and the second adjustment circuit is connected to the second inverter and the feedback control module, so as to adjust the output signal of the second inverter according to the second voltage signal output by the feedback control module, and the duty cycle of the output signal of the second inverter is the same as that of the second inverter. The magnitude of the second voltage signal is negatively correlated;

The third inverter is configured to output an inverted signal of the output signal of the inverter chain to the feedback control module, and the feedback control module is configured to output the first inverter according to the output signal of the inverter chain. Two voltage signals and outputting the first voltage signal according to the output signal of the third inverter, wherein the magnitude of the second voltage signal is positively correlated with the duty cycle of the output signal of the inverter chain , the magnitude of the first voltage signal is positively correlated with the duty cycle of the output signal of the third inverter.

Further, the first adjustment circuit includes a first current source and a second current source, the first current source is connected to the power supply terminal of the first inverter to adjust the pull-up capability of the first inverter , the second current source is connected to the ground terminal of the first inverter to adjust the pull-down capability of the first inverter, and the magnitude of the current of the first current source is proportional to the magnitude of the first voltage signal Negative correlation, the magnitude of the current of the second current source is positively correlated with the magnitude of the first voltage signal;

The second adjustment circuit includes a third current source and a fourth current source, the third current source is connected to the power supply terminal of the second inverter to adjust the pull-up capability of the second inverter, the The fourth current source is connected to the ground terminal of the second inverter to adjust the pull-down capability of the second inverter, and the current of the third current source is negatively correlated with the second voltage signal, The magnitude of the current of the fourth current source is positively correlated with the magnitude of the second voltage signal.

Further, the inverter chain includes a plurality of inverter groups connected in series.

Further, the feedback control module is configured to obtain the first voltage signal and the second voltage signal in the following manner: obtaining a third voltage by performing low-pass filtering on the output signal of the third inverter signal, a fourth voltage signal is obtained by performing low-pass filtering on the output signal of the inverter chain, and then fully differential amplification is performed on the third voltage signal and the fourth voltage signal, so as to obtain the fourth voltage signal. a voltage signal and the second voltage signal.

Further, the feedback control module includes a first low-pass filtering unit, a second low-pass filtering unit and a fully differential amplifier;

The input end of the first low-pass filtering unit is connected to the output end of the inverter chain to receive the output signal of the inverter chain;

The input end of the second low-pass filtering unit is connected to the output end of the third inverter to receive the output signal of the third inverter;

The positive input terminal of the fully differential amplifier is connected to the output terminal of the first low-pass filtering unit, the negative input terminal of the fully differential amplifier is connected to the output terminal of the second low-pass filtering unit, and the fully differential amplifier is connected to the output terminal of the second low-pass filtering unit. The positive output terminal is used for outputting the second voltage signal, and the negative output terminal of the fully differential amplifier is used for outputting the first voltage signal.

Further, the feedback control module further includes a common mode circuit, the output end of the common mode circuit is connected to the reference voltage terminal of the fully differential amplifier, so as to provide a common mode reference voltage to the fully differential amplifier, the common mode circuit is connected to the reference voltage terminal of the fully differential amplifier. The common mode reference voltage provided by the circuit is variable.

Further, a first buffer is arranged between the output end of the inverter chain and the feedback control module to balance the signal delay time of the third inverter.

In order to achieve the above purpose, the technical solution of the present invention also provides a crystal oscillator circuit, including a crystal oscillator, an amplifier circuit, a square wave conversion circuit and the above-mentioned duty cycle correction circuit, wherein the output end of the crystal oscillator is connected to The input end of the amplifying circuit and the output end of the amplifying circuit are connected to the input end of the square wave conversion circuit, and the output end of the square wave conversion circuit is connected to the duty ratio correction circuit.

Further, it also includes a frequency doubling circuit, the frequency doubling circuit is connected to the output end of the inverter chain to perform frequency doubling processing on the output signal of the inverter chain, and the frequency doubling circuit It includes a delay unit and an XOR gate, the first input terminal of the XOR gate is connected to the output terminal of the inverter chain, the second input terminal of the XOR gate is connected to the output terminal of the delay unit, and the The input of the delay unit is connected to the output of the inverter chain.

Further, the frequency doubling circuit further includes a second buffer, and the first input terminal of the XOR gate is connected to the output terminal of the inverter chain through the second buffer.

Further, the crystal oscillator circuit further includes a PLL phase-locked loop, and the input end of the PLL phase-locked loop is connected to the output end of the frequency doubling circuit, so as to perform frequency doubling processing on the output signal of the frequency doubling circuit.

Further, the amplifying circuit includes a fifth current source, a first PMOS transistor, a first NMOS transistor, a first resistor, a first capacitor, and a second capacitor;

The positive terminal of the fifth current source is connected to the power supply, the negative terminal of the fifth current source is connected to the source of the first PMOS transistor, the gate of the first PMOS transistor, and the first terminal of the first resistor. terminal, the gate of the first NMOS transistor, and the first terminal of the first capacitor are connected to the first terminal of the crystal oscillator and the input terminal of the square wave conversion circuit, and the drain of the first PMOS transistor pole, the second end of the first resistor, the drain of the first NMOS transistor, the first end of the second capacitor are connected to the second end of the crystal oscillator, the source of the first NMOS transistor, the second end of the first capacitor and the second end of the second capacitor are grounded;

The square wave conversion circuit includes a third capacitor, a second PMOS transistor, a second NMOS transistor, and a second resistor;

The first end of the third capacitor is connected to the amplifying circuit as the input end of the square wave conversion circuit, the gate of the second PMOS transistor, the first end of the second resistor, and the second NMOS The gate of the transistor is connected to the second end of the third capacitor, the drain of the second PMOS transistor, the second end of the second resistor, and the drain of the second NMOS transistor are connected together as the The output of the square wave conversion circuit.

In order to achieve the above object, the technical solution of the present invention also provides an electronic device including the above-mentioned duty cycle correction circuit or the above-mentioned crystal oscillator circuit.

In order to achieve the above purpose, the technical solution of the present invention also provides a duty cycle correction method for a square wave clock signal, which is applied to a duty cycle correction circuit, wherein the duty cycle correction circuit includes an inverter chain, a third inverter an inverter and a feedback control module, the inverter chain includes an inverter group, the inverter group includes a first inverter, a second inverter, a first regulating circuit, and a second regulating circuit, the The output end of the first inverter is connected to the input end of the second inverter, and the third inverter is used to output the inverted signal of the output signal of the inverter chain to the feedback control module, so The methods described include:

The first regulating circuit regulates the output signal of the first inverter according to the first voltage signal output by the feedback control module, and the second regulating circuit regulates the output signal according to the second voltage signal output by the feedback control module The output signal of the second inverter, wherein the size of the duty cycle of the output signal of the first inverter is negatively correlated with the size of the first voltage signal, and the output of the second inverter The size of the duty cycle of the signal is negatively correlated with the size of the second voltage signal;

The feedback control module outputs the second voltage signal according to the output signal of the inverter chain and outputs the first voltage signal according to the output signal of the third inverter, wherein the second voltage signal The magnitude of , is positively correlated with the duty cycle of the output signal of the inverter chain, and the magnitude of the first voltage signal is positively correlated with the duty cycle of the output signal of the third inverter.

The duty cycle correction circuit provided by the present invention outputs the first voltage signal and the second voltage signal to the inverter chain through the feedback control module, and the magnitude of the first voltage signal is related to the duty cycle of the inverted signal of the output signal of the inverter chain. The magnitude of the duty cycle is positively correlated, and the magnitude of the second voltage signal is positively correlated with the duty cycle of the output signal of the inverter chain. At the same time, the first adjustment circuit in the inverter chain adjusts the first inverter according to the first voltage signal VN. The duty cycle of the output signal of the inverter INV3 is adjusted by the second adjustment circuit according to the second voltage signal VN, and the duty cycle of the output signal of the second inverter INV4 is adjusted. The size of the duty cycle is negatively correlated with the size of the first voltage signal VN, and the size of the duty cycle of the output signal of the second inverter INV4 is negatively correlated with the size of the second voltage signal VP, so that when the output of the inverter chain is negatively correlated When the duty cycle of the signal is greater than the target value, the first adjustment circuit and the second adjustment circuit in the inverter chain can quickly reduce the duty cycle of the output signal of the inverter chain. When the duty cycle of the output signal is smaller than the target value, the first regulation circuit and the second regulation circuit can quickly increase the duty cycle of the output signal of the inverter chain, so that the duty cycle correction circuit can quickly enter into a stable state. It is beneficial to achieve a better stable speed and reduce the time required for the circuit to enter a stable state. Compared with the prior art, the implementation of the duty cycle correction circuit does not require a delay unit, which is beneficial to reduce the circuit occupation area and power consumption. consumption.

Description of drawings

Preferred embodiments according to the present application will be described below with reference to the accompanying drawings. In the picture:

1 is a schematic diagram of a crystal oscillator circuit in the prior art;

2 is a schematic diagram of an empty ratio correction circuit provided by an embodiment of the present invention;

3 is a schematic diagram of another empty ratio correction circuit provided by an embodiment of the present invention;

4 is a schematic diagram of a crystal oscillator circuit provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of another crystal oscillator circuit provided by an embodiment of the present invention.

Detailed ways

The present application is described below based on examples, but the present application is not limited to these examples only. In the following detailed description of the present application, some specific details are described in detail. In order to avoid obscuring the essence of the present application, well-known methods, procedures, procedures and elements are not described in detail.

Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless clearly required by the context, words such as "including", "comprising" and the like throughout the specification and claims should be construed in an inclusive rather than an exclusive or exhaustive sense; that is, "including but not limited to" meaning.

In the description of the present application, it should be understood that the terms "first", "second" and the like are used for descriptive purposes only, and should not be construed as indicating or implying relative importance. Also, in the description of this application, unless otherwise specified, "plurality" means two or more.

Referring to FIG. 2, FIG. 2 is a schematic diagram of a duty cycle correction circuit of a square wave clock signal provided by an embodiment of the present invention. The duty cycle correction circuit includes an inverter chain, a third inverter INV5 and a feedback control module 10;

The inverter chain is used to receive the square-wave clock signal to be corrected, and to correct the duty cycle of the square-wave clock signal to be corrected according to the voltage signal output by the feedback control module 10, and the inverter The output signal Fref of the chain is the corrected clock signal (that is, the output signal of the duty cycle correction circuit). The inverter chain includes an inverter group, and the inverter group includes a first inverter INV3, a first inverter Two inverters INV4, a first adjustment circuit, and a second adjustment circuit, the output end of the first inverter INV3 is connected to the input end of the second inverter INV4, and the first adjustment circuit is connected to the second inverter INV4 an inverter INV3 and the feedback control module 10 to adjust the output signal of the first inverter INV3 according to the first voltage signal VN output by the feedback control module 10 . The size of the duty cycle of the output signal is negatively correlated with the size of the first voltage signal VN, and the second adjustment circuit is connected to the second inverter INV4 and the feedback control module 10 to control the feedback according to the feedback The second voltage signal VP output by the module 10 adjusts the output signal of the second inverter INV4, and the duty cycle of the output signal of the second inverter INV4 is negative with the magnitude of the second voltage signal VP Relatedly, in this embodiment, the input terminal of the first inverter INV3 is the input terminal of the inverter chain, and the input square wave clock signal to be corrected can be the output signal of the square wave conversion circuit in the crystal oscillator circuit, and the second The output of the inverter INV4 is the output of the inverter chain;

The third inverter INV5 is used to output the inverted signal of the output signal of the inverter chain to the feedback control module 10, and the input end of the third inverter INV5 is connected to the output end of the inverter chain , the output end of the third inverter INV5 is connected to the feedback control module 10, and the feedback control module 10 is used for outputting the second voltage signal VP according to the output signal of the inverter chain and according to the third inverter The output signal of INV5 outputs the first voltage signal VN, wherein the magnitude of the second voltage signal VP is positively correlated with the duty cycle of the output signal of the inverter chain, and the magnitude of the first voltage signal VN is The magnitude is positively correlated with the duty cycle of the output signal of the third inverter INV5. For example, the feedback control module 10 can lower the output signal of the inverter chain and the output signal of the third inverter INV5 respectively. Pass filtering processing, and then perform corresponding amplification processing to obtain the second voltage signal VP and the first voltage signal VN.

The duty cycle correction circuit provided by the embodiment of the present invention outputs a first voltage signal and a second voltage signal to the inverter chain through the feedback control module, and the magnitude of the first voltage signal is the inversion signal of the output signal of the inverter chain. The size of the duty cycle of the inverter chain is positively correlated, and the size of the second voltage signal is positively correlated with the size of the duty cycle of the output signal of the inverter chain. At the same time, the first adjustment circuit in the inverter chain adjusts the first voltage signal VN according to the The duty ratio of the output signal of an inverter INV3 is adjusted by the second adjusting circuit according to the second voltage signal VN. The duty ratio of the output signal of the second inverter INV4 is adjusted, and the output of the first inverter INV3 The duty cycle of the signal is negatively correlated with the magnitude of the first voltage signal VN, and the duty cycle of the output signal of the second inverter INV4 is negatively correlated with the magnitude of the second voltage signal VP, so that when the inverter chain is When the duty cycle of the output signal is greater than the target value (that is, the duty cycle of the output signal of the duty cycle correction circuit in a steady state), the first adjustment circuit and the second adjustment circuit in the inverter chain can quickly reduce the duty cycle of the output signal of the inverter chain, when the duty cycle of the output signal of the inverter chain is smaller than the target value, the first adjustment circuit and the second adjustment circuit can quickly increase the inversion The size of the duty cycle of the output signal of the converter chain makes the duty cycle correction circuit enter a stable state quickly, which is conducive to achieving a better stable speed, reducing the time required for the circuit to enter a stable state, and compared with the prior art, it takes up less time The realization of the duty ratio correction circuit may not require a delay unit, which is beneficial to reduce the area occupied by the circuit and the power consumption.

Among them, in the embodiment of the present invention, the first adjustment circuit and the second adjustment circuit in the inverter chain can be implemented by using a current source, and the pull-up and pull-down capabilities of the first adjustment circuit and the pull-up capability of the second adjustment circuit can be adjusted through the current source. , pull-down capability, and then control the duty cycle of the output signal of the first inverter INV3 and the duty cycle of the output signal of the second inverter INV4.

For example, in the embodiment shown in FIG. 2 , the first regulating circuit may include a first current source I6 and a second current source I7 , and the first current source I6 is connected to the power supply of the first inverter INV3 terminal to adjust the pull-up capability of the first inverter (one end of the first current source I6 is connected to the power supply VDD, the other end is connected to the power supply terminal of the first inverter, the pull-up capability of the first inverter is the same as that of the first inverter. The current of the current source I6 is positively correlated), the second current source I7 is connected to the ground terminal of the first inverter to adjust the pull-down capability of the first inverter (one end of the second current source I7 is connected to the first inverter The ground terminal of the inverter is grounded, and the other terminal is grounded. The pull-down capability of the first inverter is positively correlated with the current of the first current source I7), and the magnitude of the current of the first current source is related to the magnitude of the first voltage signal VN. is negatively correlated, and the magnitude of the current of the second current source is positively correlated with the magnitude of the first voltage signal VN. It can be understood that the greater the pull-up capability of the first inverter, the higher the output of the first inverter. The larger the duty cycle of the signal, the greater the pull-down capability of the first inverter, and the smaller the duty cycle of the output signal of the first inverter. In this way, the voltage of the first voltage signal VN is larger. The adjustment circuit can make the duty cycle of the output signal of the first inverter smaller and the voltage of the first voltage signal VN smaller, and the first adjustment circuit can make the duty cycle of the output signal of the first inverter smaller. is large, and through the joint action of the first current source I6 and the second current source I7, the adjustment speed of the first inverter by the first adjustment circuit can be improved;

The second adjustment circuit may include a third current source I8 and a fourth current source I9, the third current source I8 is connected to the power supply terminal of the second inverter INV4 to adjust the voltage of the second inverter INV4. Pull-up capability (one end of the third current source I8 is connected to the power supply VDD, and the other end is connected to the power supply end of the second inverter INV4, the pull-up capability of the second inverter INV4 is positively correlated with the current of the third current source I8), The fourth current source I9 is connected to the ground terminal of the second inverter INV4 to adjust the pull-down capability of the second inverter INV4 (one end of the fourth current source I9 is connected to the ground terminal of the second inverter INV4 , the other end is grounded, the pull-down capability of the second inverter is positively correlated with the current of the fourth current source I9), the current of the third current source I8 is negatively correlated with the magnitude of the second voltage signal VP, so The magnitude of the current of the fourth current source I9 is positively correlated with the magnitude of the second voltage signal VP. It can be understood that, the greater the pull-up capability of the second inverter, the greater the duty cycle of the output signal of the second inverter. The larger the ratio is, the larger the pull-down capability of the second inverter is, and the smaller the duty cycle of the output signal of the second inverter is. In this way, the voltage of the second voltage signal VP is larger, and the second adjustment circuit can make the The smaller the duty cycle of the output signal of the second inverter, the smaller the voltage of the second voltage signal VP, the larger the duty cycle of the output signal of the second inverter can be made by the second adjustment circuit, and the The joint action of the third current source I8 and the fourth current source I9 can improve the adjustment speed of the second inverter by the second adjustment circuit.

Wherein, in the embodiment of the present invention, the current source may be implemented by a MOS transistor or a triode.

In addition, in the embodiment of the present invention, in order to balance the signal delay time caused by the third inverter INV5, a first buffer Buffer1 is arranged between the output end of the inverter chain and the feedback control module 10, which is beneficial to the feedback control The two signals input by the module are two signals with completely opposite phases. Specifically, the first buffer Buffer1 and the third inverter INV5 have approximately the same signal delay time.

Wherein, in the embodiment of the present invention, the first inverter and the second inverter in the inverter chain may be inverters composed of PMOS transistors and NMOS transistors, and may be CMOS inverters.

In the embodiment of the present invention, the target value of the duty cycle correction circuit (that is, the duty cycle of the output signal of the duty cycle correction circuit in a stable state) can be determined by the characteristic parameters of each part in the duty cycle correction circuit, that is, it can be determined by Changing the characteristic parameter of the device in the duty cycle correction circuit changes the target value of the duty cycle correction circuit. For example, the target value of the duty cycle correction circuit may be 50%. When the duty cycle of the output signal of the duty cycle correction circuit is greater than 50%, the voltage of the second voltage signal VP increases compared to the steady state, The magnitude of the voltage of the first voltage signal VN is reduced, so that the conduction capability of the first current source I6 can be increased, and the current can be increased. The pull-up capability of the phase device INV3 is strengthened, and the duty cycle of the output signal of INV3 is increased; at the same time, due to the increase in the voltage of the second voltage signal VP, the conduction capability of the fourth current source I9 is also enhanced, and the third current The conduction ability of the source I8 is weakened, so the pull-down ability of the second inverter INV4 is strengthened, and the duty cycle of the output signal of INV4 is reduced. After the output signal of INV3 is inverted by INV4, the low level of the square wave signal will be further expanded. pulse width, thereby reducing the duty cycle of the output square wave signal and reaching the target value of the duty cycle calibration.

For example, in one embodiment, the feedback control module 10 is configured to obtain the first voltage signal VN and the second voltage signal VP in the following manner: by low-passing the output signal of the third inverter Filtering to obtain a third voltage signal, performing low-pass filtering on the output signal of the inverter chain to obtain a fourth voltage signal, and then performing full differential amplification processing on the third voltage signal and the fourth voltage signal , so as to obtain the first voltage signal VN and the second voltage signal VP.

For example, the feedback control module 10 may include a first low-pass filtering unit, a second low-pass filtering unit and a fully differential amplifier;

The input end of the first low-pass filtering unit is connected to the output end of the inverter chain to receive the output signal of the inverter chain;

The input end of the second low-pass filtering unit is connected to the output end of the third inverter to receive the output signal of the third inverter;

The positive input terminal of the fully differential amplifier is connected to the output terminal of the first low-pass filtering unit, the negative input terminal of the fully differential amplifier is connected to the output terminal of the second low-pass filtering unit, and the fully differential amplifier is connected to the output terminal of the second low-pass filtering unit. The positive output terminal is used for outputting the second voltage signal, and the negative output terminal of the fully differential amplifier is used for outputting the first voltage signal. Through the fully differential amplifier, the common mode point of VP and VN can be guaranteed, the gain can be provided, and the stability of the feedback loop can be guaranteed. In addition, the fully differential amplifier in the feedback control module can also be implemented with other amplifiers.

Preferably, in an embodiment, in order to speed up the duty cycle correction, the inverter chain may include a plurality of inverter groups sequentially connected in series (cascaded), and each inverter group includes a first inverter , a second inverter, a first adjustment circuit, and a second adjustment circuit, in the same inverter group, the output end of the first inverter is connected to the input end of the second inverter, so The first adjustment circuit is connected to the first inverter and the feedback control module, so as to adjust the output signal of the first inverter according to the first voltage signal output by the feedback control module, and the first inverter The size of the duty cycle of the output signal of the inverter is negatively correlated with the size of the first voltage signal, and the second adjustment circuit is connected to the second inverter and the feedback control module to control the feedback according to the feedback The second voltage signal output by the module adjusts the output signal of the second inverter, and the magnitude of the duty cycle of the output signal of the second inverter is negatively correlated with the magnitude of the second voltage signal.

For example, the number of inverter banks in the inverter chain can be 2, 3, 4, etc.

Referring to FIG. 3 , FIG. 3 is a schematic diagram of another duty cycle correction circuit of a square wave clock signal provided by an embodiment of the present invention. The duty cycle correction circuit includes an inverter chain, a third inverter INV5 , a first Buffer Buffer1 and feedback control module;

The inverter chain includes two series (cascaded) inverter groups, the first inverter group includes a first inverter INV1, a second inverter INV2, a first current source I2 and a second inverter INV2. A first regulating circuit composed of a current source I3, a second regulating circuit composed of a third current source I4 and a fourth current source I5, and the second inverter group includes a first inverter INV3 and a second inverter INV4 , a first regulating circuit composed of a first current source I6 and a second current source I7, a second regulating circuit composed of a third current source I8 and a fourth current source I9, in this embodiment, the first inverter INV1 The input end of the inverter chain is the input end of the inverter chain, the input square wave clock signal to be corrected can be the output signal of the square wave conversion circuit in the crystal oscillator circuit, and the output end of the second inverter INV4 is the inverter chain. , which is used to output the corrected signal Fref;

The first buffer Buffer1 is arranged between the output end of the inverter chain and the feedback control module to balance the delay brought by the third inverter INV5, so that the two signals input by the feedback control module are two signals with completely opposite phases;

The feedback control module includes a first low-pass filtering unit, a second low-pass filtering unit and a fully differential amplifier 11;

Wherein, the input end of the first low-pass filtering unit is connected to the output end of the inverter chain through the first buffer Buffer1 to obtain the output signal Fref of the inverter chain, and the first low-pass filtering unit may be The RC filter circuit includes a resistor R3 and a capacitor C4. The larger the duty cycle of the output signal of the inverter chain, the larger the voltage of the output signal vp1 (the fourth voltage signal) of the first low-pass filter unit;

The input terminal of the second low-pass filtering unit is connected to the output terminal of the third inverter INV5 to receive the output signal of the third inverter INV5. The second low-pass filtering unit may be an RC filter circuit, including Resistor R4 and capacitor C5, the larger the duty cycle of the output signal of the third inverter INV5 (the inverted signal of the output signal of the inverter chain), the greater the duty cycle of the output signal vn1 of the second low-pass filtering unit (the third voltage signal ) the greater the voltage;

The positive input terminal of the fully differential amplifier 11 is connected to the output terminal of the first low-pass filtering unit to receive the signal vp1, and the negative input terminal of the fully differential amplifier 11 is connected to the output terminal of the second low-pass filtering unit to receive the signal vp1. For the signal vn1, the positive output terminal of the fully differential amplifier is used to output the second voltage signal VP, and the negative output terminal of the fully differential amplifier is used to output the first voltage signal VN.

The current sources I2, I3, I6, I7, I4, I5, I8, and I9 are all controlled current sources, wherein the current sources I4, I5, I8, and I9 are connected to the positive output terminal of the amplifier 11 to obtain the second voltage signal VP , the controlled current sources I2 , I3 , I6 , and I7 are connected to the negative output terminal VN of the amplifier 11 to obtain the first voltage signal VN. When the duty cycle of the output signal of the duty cycle correction circuit is stable (that is, in a stable state), the voltages of VP and VN remain constant, and the currents passing through the inverters INV1, INV2, INV3, and INV4 also remain constant. The rising and falling edges will also not change. INV1, INV2 and I2-I5 form the inverter group of the first stage, VN is connected to the upper and lower current sources I2 and I3 of INV1, and VP is connected to the upper and lower current sources I4 and I5 of INV2. When the duty cycle of the output signal of the duty cycle correction circuit is greater than the target value, the VP voltage increases and the VN voltage decreases compared to the steady state, thereby increasing the conduction capability of the upper current source I2 of the inverter INV1 , the current increases, the conduction capability of the lower current source I3 decreases, and the current decreases, so the pull-up capability of the inverter INV1 is strengthened, thereby increasing the duty cycle of the output signal of INV1; The conduction ability of the pull-down current source I5 of the inverter INV2 is strengthened, and the conduction ability of the pull-up current source I4 is weakened. After the output signal of INV1 is inverted by INV2, the low-level pulse width of the square wave signal will be further expanded, thereby reducing the The duty cycle of the square wave signal achieves the purpose of duty cycle calibration. In addition, INV3, INV4 and I6-I9 are the inverter group of the second stage, and the correction method is the same as that of the inverter group of the first stage, which can speed up the correction speed of the duty cycle.

Among them, for the feedback control module, the output signal Fref signal of the inverter chain is respectively connected to the RC filter after passing through Buffer1 and the third inverter INV5 respectively. The low-pass filter composed of R3 and C4, and the low-pass filter composed of R4 and C5 are respectively connected to the in-phase and inverse signals of the Fref signal. The inverted signal can output equal voltage signals vp1 and vn1 after passing through the low-pass filter, otherwise vp1 is larger or smaller than vn1. After vp1 and vn1 pass through the fully differential amplifier 11, they output the VP and VN signals. When the duty cycle is stable at 50%, the output voltage signals VP and VN are constant, and the current size of the controlled current source does not change, so the duty cycle is corrected. The duty cycle of the signal Fref output by the circuit can be kept constant.

Preferably, in this embodiment, the feedback control module may further include a common mode circuit 12, and the output end of the common mode circuit 12 is connected to the reference voltage terminal of the fully differential amplifier 11 to provide the fully differential amplifier 11 with a common mode reference voltage. The common mode reference voltage provided by circuit 12 is variable. In this embodiment, the VP and VN signals can be affected by the common mode reference voltage. By adjusting the common mode circuit 12 to output different common mode reference voltages, the output VP and VN signals are different, so that the purpose of adjustable duty cycle can be achieved. For example, in one embodiment, in order to achieve the target value of 50%, the common mode reference voltage provided by the common mode circuit 12 may be VDD/2. When the required target value increases, the common mode reference voltage can be increased. When the target value is reduced, the common-mode reference voltage can be reduced, and VDD is the voltage of the power supply VDD of the inverter group. In addition, the target value of the duty ratio correction circuit can also be adjusted by changing the characteristic parameter of the differential amplifier 11 .

The duty ratio correction circuit of the embodiment of the present invention can generate a square wave signal with a duty ratio of 50%. In addition, by adjusting different common mode voltages, it can stably output square wave signals with different duty ratios. In addition, compared with the prior art, the implementation of the duty cycle correction circuit may not require a delay unit, which is beneficial to reducing the area occupied by the circuit and the power consumption, and at the same time, it is also beneficial to improve the stabilization speed.

An embodiment of the present invention further provides a crystal oscillator circuit, including a crystal oscillator, an amplifier circuit, a square wave conversion circuit and the above duty cycle correction circuit, wherein the output end of the crystal oscillator is connected to the input of the amplifier circuit The output end of the amplifying circuit is connected to the input end of the square wave conversion circuit, and the output end of the square wave conversion circuit is connected to the duty cycle correction circuit.

Referring to FIG. 4, FIG. 4 is a schematic diagram of a crystal oscillator circuit provided by an embodiment of the present invention. The crystal oscillator circuit includes a crystal oscillator 104, an amplifier circuit 103, a square wave conversion circuit 102, and the above-mentioned duty cycle correction circuit 101, wherein, The output end of the crystal oscillator 104 is connected to the input end of the amplifying circuit 103 , the output end of the amplifying circuit 103 is connected to the input end of the square wave conversion circuit 102 , and the output end of the square wave conversion circuit 102 is connected to The input end of the duty cycle correction circuit 101, the crystal oscillator 104 can generate a sine wave signal;

The crystal oscillator circuit further includes a frequency doubling circuit 200, and the frequency doubling circuit 200 is connected to the output terminal of the duty cycle correction circuit 101 (ie, the output terminal of the inverter chain), so as to adjust the frequency of the inverter chain. The output signal is subjected to frequency doubling processing. The frequency doubling circuit 200 includes a delay unit 201, an exclusive OR gate XOR, the first input end of the exclusive OR gate XOR is connected to the output end of the inverter chain, and the exclusive OR gate XOR The second input terminal of the XOR is connected to the output terminal of the delay unit 201 , and the input terminal of the delay unit 201 is connected to the output terminal of the inverter chain. The frequency of the output signal of the double frequency circuit 200 is twice the frequency of the signal Fref. For example, the duty cycle correction circuit 101 can output the Fref signal with a constant duty cycle of 50%. Output a 2*Fref square wave signal with a constant duty cycle of 50%;

Preferably, the frequency doubling circuit 200 further includes a second buffer Buffer2, the first input end of the exclusive OR gate XOR is connected to the output end of the inverter chain through the second buffer Buffer2, and the second buffer Buffer2 can make the output signal closer to a square wave.

The amplifier circuit 103 includes a fifth current source I1, a first PMOS transistor MP1, a first NMOS transistor MN1, a first resistor R1, a first capacitor C1 and a second capacitor C2, wherein the capacitors C1 and C2 are tuning capacitors, and the current The source I1, MN1 and MP1 form an amplifier with a push-pull structure, which is used to provide gain. R1 is a feedback resistor. The amplifier circuit provides sufficient gain for the crystal oscillator to achieve stable start-up. Capacitors C1 and C2 are fully capacitive. The same tuning capacitor is used to tune the frequency of the crystal oscillator, and the crystal oscillator can provide a sine wave signal with sufficient amplitude after the amplifying circuit;

The positive terminal of the fifth current source I1 is connected to the power supply, the negative terminal of the fifth current source I1 is connected to the source of the first PMOS transistor MP1, the gate of the first PMOS transistor MP1, the first The first end of the resistor, the gate of the first NMOS transistor MN1, and the first end of the first capacitor C1 are connected to the first end of the crystal oscillator 104 and the input end of the square wave conversion circuit 102, The drain of the first PMOS transistor MP1, the second end of the first resistor R1, the drain of the first NMOS transistor MN1, and the first end of the second capacitor C2 are connected to the crystal oscillator 104 The second end of the first NMOS transistor MN1, the second end of the first capacitor C1, and the second end of the second capacitor C2 are grounded;

The square wave conversion circuit 102 includes a third capacitor C3, a second PMOS transistor MP2, a second NMOS transistor MN2, and a second resistor R2, wherein C3 is a coupling capacitor for isolating the DC point of the amplifier circuit and the square wave conversion circuit, MN2 and MP2 form an inverter, and resistor R2 is a feedback resistor, which is used to provide the DC bias voltage at the input end of the inverter;

The first end of the third capacitor C3 is connected to the amplifying circuit 103 as the input end of the square wave conversion circuit 102, the gate of the second PMOS transistor MP2, the first end of the second resistor R2, The gate of the second NMOS transistor MN2 is connected to the second end of the third capacitor C3, the drain of the second PMOS transistor MP2, the second end of the second resistor R2, and the second NMOS transistor The drains of MN2 are connected together as the output end of the square wave conversion circuit, the source of the second PMOS transistor MP2 is connected to the power supply, and the source of the second NMOS transistor MN2 is grounded.

The crystal oscillator circuit provided by the embodiment of the present invention can generate a signal with a duty cycle of 50%, and can output a square wave signal with a frequency multiplied by 2, which has the advantage of low cost in the application of a high-performance clock system, and can be adjusted by different common mode references. voltage, can stably output square wave signals with different duty cycles, which is beneficial to improve reliability and reduce power consumption and cost in the design of high-performance clock systems.

The above-mentioned crystal oscillator circuit can obtain a 2*Fref reference clock source with a stable duty cycle after the frequency doubling circuit, which can provide a reference clock source for a high-performance clock system. For example, in an embodiment, referring to FIG. 5, the The crystal oscillator circuit further includes a PLL phase-locked loop 300. The input end of the PLL phase-locked loop 300 is connected to the output end of the frequency doubling circuit 200 to perform N frequency doubling processing on the output signal of the frequency doubling circuit, and the PLL locks the phase. The ring 300 can output a clock signal with a frequency of 2*N*Fref to implement a high-performance clock system.

In the current crystal oscillator circuit, in order to realize a high-performance clock system, two cascaded PLL phase-locked loops are usually used. is the frequency of the input signal of the first-stage PLL), and then supplies it to the second-stage PLL for use as a reference clock, and obtains M'*N'*Fref' through the second-stage PLL. Two cascaded PLL phase-locked loops are likely to cause problems of large circuit occupation area and power consumption. The crystal oscillator circuit provided by the embodiment of the present invention outputs a clock signal with a double frequency through the double frequency circuit, which can save a PLL cascade connection, which is beneficial to reduce the occupied area and power consumption of the circuit.

An embodiment of the present invention provides an electronic device, which includes the above-mentioned duty cycle correction circuit or the above-mentioned crystal oscillator circuit. For example, the electronic device may be an electronic device such as a Bluetooth headset, a Bluetooth speaker, and the like.

An embodiment of the present invention further provides a duty cycle correction method for a square wave clock signal, which is applied to a duty cycle correction circuit, where the duty cycle correction circuit includes an inverter chain, a third inverter and a feedback control module , the inverter chain includes an inverter group, and the inverter group includes a first inverter, a second inverter, a first adjustment circuit, and a second adjustment circuit. The output terminal is connected to the input terminal of the second inverter, and the third inverter is configured to output the inverted signal of the output signal of the inverter chain to the feedback control module, and the method includes:

The first regulating circuit regulates the output signal of the first inverter according to the first voltage signal output by the feedback control module, and the second regulating circuit regulates the output signal according to the second voltage signal output by the feedback control module The output signal of the second inverter, wherein the size of the duty cycle of the output signal of the first inverter is negatively correlated with the size of the first voltage signal, and the output of the second inverter The size of the duty cycle of the signal is negatively correlated with the size of the second voltage signal;

The feedback control module outputs the second voltage signal according to the output signal of the inverter chain and outputs the first voltage signal according to the output signal of the third inverter, wherein the second voltage signal The magnitude of , is positively correlated with the duty cycle of the output signal of the inverter chain, and the magnitude of the first voltage signal is positively correlated with the duty cycle of the output signal of the third inverter.

Those skilled in the art can understand that, under the premise of no conflict, the above preferred solutions can be freely combined and superimposed.

It should be understood that the above-mentioned embodiments are only exemplary rather than restrictive, and those skilled in the art can make various obvious or equivalent to the above-mentioned details without departing from the basic principles of the present invention. Modifications or substitutions will be included within the scope of the claims of the present invention.

Claims (14)

1. a duty ratio correction circuit of a square wave clock signal, is characterized in that, comprises an inverter chain, a third inverter and a feedback control module; The inverter chain includes an inverter group, the inverter group includes a first inverter, a second inverter, a first adjustment circuit, and a second adjustment circuit, and the output of the first inverter The terminal is connected to the input terminal of the second inverter, and the first adjustment circuit is connected to the first inverter and the feedback control module to adjust the first voltage signal output by the feedback control module. The output signal of the first inverter, the size of the duty cycle of the output signal of the first inverter is negatively correlated with the size of the first voltage signal, and the second adjustment circuit is connected to the second inverter and the feedback control module, so as to adjust the output signal of the second inverter according to the second voltage signal output by the feedback control module, and the duty cycle of the output signal of the second inverter is the same as that of the second inverter. The magnitude of the second voltage signal is negatively correlated; The third inverter is configured to output an inverted signal of the output signal of the inverter chain to the feedback control module, and the feedback control module is configured to output the first inverter according to the output signal of the inverter chain. Two voltage signals and outputting the first voltage signal according to the output signal of the third inverter, wherein the magnitude of the second voltage signal is positively correlated with the duty cycle of the output signal of the inverter chain , the magnitude of the first voltage signal is positively correlated with the duty cycle of the output signal of the third inverter. 2 . The duty cycle correction circuit according to claim 1 , wherein the first adjustment circuit comprises a first current source and a second current source, and the first current source is connected to the first inverter. 3 . The power supply terminal of the first inverter is used to adjust the pull-up capability of the first inverter, the second current source is connected to the ground terminal of the first inverter to adjust the pull-down capability of the first inverter. The magnitude of the current of a current source is negatively correlated with the magnitude of the first voltage signal, and the magnitude of the current of the second current source is positively correlated with the magnitude of the first voltage signal; The second adjustment circuit includes a third current source and a fourth current source, the third current source is connected to the power supply terminal of the second inverter to adjust the pull-up capability of the second inverter, the The fourth current source is connected to the ground terminal of the second inverter to adjust the pull-down capability of the second inverter, and the current of the third current source is negatively correlated with the second voltage signal, The magnitude of the current of the fourth current source is positively correlated with the magnitude of the second voltage signal. 3. The duty cycle correction circuit according to claim 1 or 2, wherein the inverter chain comprises a plurality of inverter groups connected in series. 4. The duty cycle correction circuit according to any one of claims 1-3, wherein the feedback control module is configured to obtain the first voltage signal and the second voltage signal in the following manner: The third voltage signal is obtained by performing low-pass filtering on the output signal of the third inverter, the fourth voltage signal is obtained by performing low-pass filtering on the output signal of the inverter chain, and then the third voltage signal is obtained by performing low-pass filtering on the output signal of the inverter chain. The third voltage signal and the fourth voltage signal are fully differentially amplified, so as to obtain the first voltage signal and the second voltage signal. 5. The duty cycle correction circuit according to claim 4, wherein the feedback control module comprises a first low-pass filtering unit, a second low-pass filtering unit and a fully differential amplifier; The input end of the first low-pass filtering unit is connected to the output end of the inverter chain to receive the output signal of the inverter chain; The input end of the second low-pass filtering unit is connected to the output end of the third inverter to receive the output signal of the third inverter; The positive input terminal of the fully differential amplifier is connected to the output terminal of the first low-pass filtering unit, the negative input terminal of the fully differential amplifier is connected to the output terminal of the second low-pass filtering unit, and the fully differential amplifier is connected to the output terminal of the second low-pass filtering unit. The positive output terminal is used for outputting the second voltage signal, and the negative output terminal of the fully differential amplifier is used for outputting the first voltage signal. 6 . The duty cycle correction circuit according to claim 5 , wherein the feedback control module further comprises a common mode circuit, the output terminal of the common mode circuit is connected to the reference voltage terminal of the fully differential amplifier, so as to A common mode reference voltage is provided to the fully differential amplifier, and the common mode reference voltage provided by the common mode circuit is variable. 7. The duty cycle correction circuit according to any one of claims 1-6, wherein a first buffer is provided between the output end of the inverter chain and the feedback control module to balance the signal delay time of the third inverter. 8. A crystal oscillator circuit, characterized in that it comprises a crystal oscillator, an amplifier circuit, a square wave conversion circuit and the duty cycle correction circuit according to any one of claims 1-7, wherein the crystal oscillator has a The output end is connected to the input end of the amplifying circuit, the output end of the amplifying circuit is connected to the input end of the square wave conversion circuit, and the output end of the square wave conversion circuit is connected to the duty ratio correction circuit. 9 . The crystal oscillator circuit according to claim 8 , further comprising a frequency doubling circuit, the frequency doubling circuit is connected to the output end of the inverter chain, so as to control the output of the inverter chain. 10 . The signal is subjected to frequency doubling processing. The frequency doubling circuit includes a delay unit and an XOR gate. The first input end of the XOR gate is connected to the output end of the inverter chain. The second XOR gate is connected to the output end of the inverter chain. The input terminal is connected to the output terminal of the delay unit, and the input terminal of the delay unit is connected to the output terminal of the inverter chain. 10 . The crystal oscillator circuit according to claim 9 , wherein the frequency doubling circuit further comprises a second buffer, and the first input terminal of the XOR gate is connected to the second buffer through the second buffer. 11 . The output of the inverter chain. 11. The crystal oscillator circuit according to claim 9, characterized in that, the crystal oscillator circuit further comprises a PLL phase-locked loop, and the input end of the PLL phase-locked loop is connected to the output end of the frequency doubling circuit, so as to The output signal of the frequency doubling circuit is subjected to frequency doubling processing. 12. The crystal oscillator circuit according to claim 8, wherein the amplifying circuit comprises a fifth current source, a first PMOS transistor, a first NMOS transistor, a first resistor, a first capacitor, and a second capacitor; The positive terminal of the fifth current source is connected to the power supply, the negative terminal of the fifth current source is connected to the source of the first PMOS transistor, the gate of the first PMOS transistor, and the first terminal of the first resistor. terminal, the gate of the first NMOS transistor, and the first terminal of the first capacitor are connected to the first terminal of the crystal oscillator and the input terminal of the square wave conversion circuit, and the drain of the first PMOS transistor pole, the second end of the first resistor, the drain of the first NMOS transistor, the first end of the second capacitor are connected to the second end of the crystal oscillator, the source of the first NMOS transistor, the second end of the first capacitor and the second end of the second capacitor are grounded; The square wave conversion circuit includes a third capacitor, a second PMOS transistor, a second NMOS transistor, and a second resistor; The first end of the third capacitor is connected to the amplifying circuit as the input end of the square wave conversion circuit, the gate of the second PMOS transistor, the first end of the second resistor, and the second NMOS The gate of the transistor is connected to the second end of the third capacitor, the drain of the second PMOS transistor, the second end of the second resistor, and the drain of the second NMOS transistor are connected together as the The output of the square wave conversion circuit. 13. An electronic device, characterized by comprising the duty cycle correction circuit according to any one of claims 1-7 or the crystal oscillator circuit according to any one of claims 8-12. 14. A duty cycle correction method for a square wave clock signal, applied to a duty cycle correction circuit, wherein the duty cycle correction circuit comprises an inverter chain, a third inverter and a feedback control module, The inverter chain includes an inverter group, the inverter group includes a first inverter, a second inverter, a first adjustment circuit, and a second adjustment circuit, and the output of the first inverter The terminal is connected to the input terminal of the second inverter, and the third inverter is used for outputting the inverted signal of the output signal of the inverter chain to the feedback control module, and the method includes: The first regulating circuit regulates the output signal of the first inverter according to the first voltage signal output by the feedback control module, and the second regulating circuit regulates the output signal according to the second voltage signal output by the feedback control module The output signal of the second inverter, wherein the size of the duty cycle of the output signal of the first inverter is negatively correlated with the size of the first voltage signal, and the output of the second inverter The size of the duty cycle of the signal is negatively correlated with the size of the second voltage signal; The feedback control module outputs the second voltage signal according to the output signal of the inverter chain and outputs the first voltage signal according to the output signal of the third inverter, wherein the second voltage signal The magnitude of , is positively correlated with the duty cycle of the output signal of the inverter chain, and the magnitude of the first voltage signal is positively correlated with the duty cycle of the output signal of the third inverter.

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